ruby_mem_test.py revision 11662:004d34b65092
1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; 9# redistributions in binary form must reproduce the above copyright 10# notice, this list of conditions and the following disclaimer in the 11# documentation and/or other materials provided with the distribution; 12# neither the name of the copyright holders nor the names of its 13# contributors may be used to endorse or promote products derived from 14# this software without specific prior written permission. 15# 16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27# 28# Authors: Ron Dreslinski 29# Brad Beckmann 30 31import m5 32from m5.objects import * 33from m5.defines import buildEnv 34from m5.util import addToPath 35import os, optparse, sys 36addToPath('../common') 37addToPath('../ruby') 38addToPath('../network') 39addToPath('../topologies') 40 41import Options 42import Ruby 43import Network 44 45# Get paths we might need. It's expected this file is in m5/configs/example. 46config_path = os.path.dirname(os.path.abspath(__file__)) 47config_root = os.path.dirname(config_path) 48 49parser = optparse.OptionParser() 50Options.addCommonOptions(parser) 51 52parser.add_option("--maxloads", metavar="N", default=0, 53 help="Stop after N loads") 54parser.add_option("--progress", type="int", default=1000, 55 metavar="NLOADS", 56 help="Progress message interval " 57 "[default: %default]") 58parser.add_option("--num-dmas", type="int", default=0, help="# of dma testers") 59parser.add_option("--functional", type="int", default=0, 60 help="percentage of accesses that should be functional") 61parser.add_option("--suppress-func-warnings", action="store_true", 62 help="suppress warnings when functional accesses fail") 63 64# 65# Add the ruby specific and protocol specific options 66# 67Ruby.define_options(parser) 68Network.define_options(parser) 69 70execfile(os.path.join(config_root, "common", "Options.py")) 71 72(options, args) = parser.parse_args() 73 74# 75# Set the default cache size and associativity to be very small to encourage 76# races between requests and writebacks. 77# 78options.l1d_size="256B" 79options.l1i_size="256B" 80options.l2_size="512B" 81options.l3_size="1kB" 82options.l1d_assoc=2 83options.l1i_assoc=2 84options.l2_assoc=2 85options.l3_assoc=2 86 87if args: 88 print "Error: script doesn't take any positional arguments" 89 sys.exit(1) 90 91block_size = 64 92 93if options.num_cpus > block_size: 94 print "Error: Number of testers %d limited to %d because of false sharing" \ 95 % (options.num_cpus, block_size) 96 sys.exit(1) 97 98# 99# Currently ruby does not support atomic or uncacheable accesses 100# 101cpus = [ MemTest(atomic = False, 102 max_loads = options.maxloads, 103 issue_dmas = False, 104 percent_functional = options.functional, 105 percent_uncacheable = 0, 106 progress_interval = options.progress, 107 suppress_func_warnings = options.suppress_func_warnings) \ 108 for i in xrange(options.num_cpus) ] 109 110system = System(cpu = cpus, 111 funcmem = SimpleMemory(in_addr_map = False), 112 funcbus = IOXBar(), 113 clk_domain = SrcClockDomain(clock = options.sys_clock), 114 mem_ranges = [AddrRange(options.mem_size)]) 115 116if options.num_dmas > 0: 117 dmas = [ MemTest(atomic = False, 118 max_loads = options.maxloads, 119 issue_dmas = True, 120 percent_functional = 0, 121 percent_uncacheable = 0, 122 progress_interval = options.progress, 123 suppress_func_warnings = 124 not options.suppress_func_warnings) \ 125 for i in xrange(options.num_dmas) ] 126 system.dma_devices = dmas 127else: 128 dmas = [] 129 130dma_ports = [] 131for (i, dma) in enumerate(dmas): 132 dma_ports.append(dma.test) 133Ruby.create_system(options, False, system, dma_ports = dma_ports) 134 135# Create a top-level voltage domain and clock domain 136system.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 137system.clk_domain = SrcClockDomain(clock = options.sys_clock, 138 voltage_domain = system.voltage_domain) 139# Create a seperate clock domain for Ruby 140system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 141 voltage_domain = system.voltage_domain) 142 143# 144# The tester is most effective when randomization is turned on and 145# artifical delay is randomly inserted on messages 146# 147system.ruby.randomization = True 148 149assert(len(cpus) == len(system.ruby._cpu_ports)) 150 151for (i, cpu) in enumerate(cpus): 152 # 153 # Tie the cpu memtester ports to the correct system ports 154 # 155 cpu.test = system.ruby._cpu_ports[i].slave 156 cpu.functional = system.funcbus.slave 157 158 # 159 # Since the memtester is incredibly bursty, increase the deadlock 160 # threshold to 5 million cycles 161 # 162 system.ruby._cpu_ports[i].deadlock_threshold = 5000000 163 164for (i, dma) in enumerate(dmas): 165 # 166 # Tie the dma memtester ports to the correct functional port 167 # Note that the test port has already been connected to the dma_sequencer 168 # 169 dma.functional = system.funcbus.slave 170 171# connect reference memory to funcbus 172system.funcbus.master = system.funcmem.port 173 174# ----------------------- 175# run simulation 176# ----------------------- 177 178root = Root( full_system = False, system = system ) 179root.system.mem_mode = 'timing' 180 181# Not much point in this being higher than the L1 latency 182m5.ticks.setGlobalFrequency('1ns') 183 184# instantiate configuration 185m5.instantiate() 186 187# simulate until program terminates 188exit_event = m5.simulate(options.abs_max_tick) 189 190print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause() 191