ruby_mem_test.py revision 11688
17635SBrad.Beckmann@amd.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 27635SBrad.Beckmann@amd.com# Copyright (c) 2009 Advanced Micro Devices, Inc. 37635SBrad.Beckmann@amd.com# All rights reserved. 47635SBrad.Beckmann@amd.com# 57635SBrad.Beckmann@amd.com# Redistribution and use in source and binary forms, with or without 67635SBrad.Beckmann@amd.com# modification, are permitted provided that the following conditions are 77635SBrad.Beckmann@amd.com# met: redistributions of source code must retain the above copyright 87635SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer; 97635SBrad.Beckmann@amd.com# redistributions in binary form must reproduce the above copyright 107635SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer in the 117635SBrad.Beckmann@amd.com# documentation and/or other materials provided with the distribution; 127635SBrad.Beckmann@amd.com# neither the name of the copyright holders nor the names of its 137635SBrad.Beckmann@amd.com# contributors may be used to endorse or promote products derived from 147635SBrad.Beckmann@amd.com# this software without specific prior written permission. 157635SBrad.Beckmann@amd.com# 167635SBrad.Beckmann@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 177635SBrad.Beckmann@amd.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 187635SBrad.Beckmann@amd.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 197635SBrad.Beckmann@amd.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 207635SBrad.Beckmann@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 217635SBrad.Beckmann@amd.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 227635SBrad.Beckmann@amd.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 237635SBrad.Beckmann@amd.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 247635SBrad.Beckmann@amd.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 257635SBrad.Beckmann@amd.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 267635SBrad.Beckmann@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 277635SBrad.Beckmann@amd.com# 287635SBrad.Beckmann@amd.com# Authors: Ron Dreslinski 297635SBrad.Beckmann@amd.com# Brad Beckmann 307635SBrad.Beckmann@amd.com 317635SBrad.Beckmann@amd.comimport m5 327635SBrad.Beckmann@amd.comfrom m5.objects import * 337635SBrad.Beckmann@amd.comfrom m5.defines import buildEnv 347635SBrad.Beckmann@amd.comfrom m5.util import addToPath 357635SBrad.Beckmann@amd.comimport os, optparse, sys 3611682Sandreas.hansson@arm.com 3711670Sandreas.hansson@arm.comaddToPath('../') 387635SBrad.Beckmann@amd.com 3911682Sandreas.hansson@arm.comfrom common import Options 4011670Sandreas.hansson@arm.comfrom ruby import Ruby 417635SBrad.Beckmann@amd.com 427635SBrad.Beckmann@amd.com# Get paths we might need. It's expected this file is in m5/configs/example. 437635SBrad.Beckmann@amd.comconfig_path = os.path.dirname(os.path.abspath(__file__)) 447635SBrad.Beckmann@amd.comconfig_root = os.path.dirname(config_path) 457635SBrad.Beckmann@amd.com 467635SBrad.Beckmann@amd.comparser = optparse.OptionParser() 4711688Sandreas.hansson@arm.comOptions.addNoISAOptions(parser) 487635SBrad.Beckmann@amd.com 4910083Snilay@cs.wisc.eduparser.add_option("--maxloads", metavar="N", default=0, 507635SBrad.Beckmann@amd.com help="Stop after N loads") 517635SBrad.Beckmann@amd.comparser.add_option("--progress", type="int", default=1000, 527635SBrad.Beckmann@amd.com metavar="NLOADS", 537635SBrad.Beckmann@amd.com help="Progress message interval " 547635SBrad.Beckmann@amd.com "[default: %default]") 557635SBrad.Beckmann@amd.comparser.add_option("--num-dmas", type="int", default=0, help="# of dma testers") 568436SBrad.Beckmann@amd.comparser.add_option("--functional", type="int", default=0, 578436SBrad.Beckmann@amd.com help="percentage of accesses that should be functional") 588436SBrad.Beckmann@amd.comparser.add_option("--suppress-func-warnings", action="store_true", 598436SBrad.Beckmann@amd.com help="suppress warnings when functional accesses fail") 607635SBrad.Beckmann@amd.com 617635SBrad.Beckmann@amd.com# 627635SBrad.Beckmann@amd.com# Add the ruby specific and protocol specific options 637635SBrad.Beckmann@amd.com# 647635SBrad.Beckmann@amd.comRuby.define_options(parser) 657635SBrad.Beckmann@amd.com 667635SBrad.Beckmann@amd.comexecfile(os.path.join(config_root, "common", "Options.py")) 677635SBrad.Beckmann@amd.com 687635SBrad.Beckmann@amd.com(options, args) = parser.parse_args() 697635SBrad.Beckmann@amd.com 707635SBrad.Beckmann@amd.com# 717635SBrad.Beckmann@amd.com# Set the default cache size and associativity to be very small to encourage 727635SBrad.Beckmann@amd.com# races between requests and writebacks. 737635SBrad.Beckmann@amd.com# 747635SBrad.Beckmann@amd.comoptions.l1d_size="256B" 757635SBrad.Beckmann@amd.comoptions.l1i_size="256B" 767635SBrad.Beckmann@amd.comoptions.l2_size="512B" 777635SBrad.Beckmann@amd.comoptions.l3_size="1kB" 787635SBrad.Beckmann@amd.comoptions.l1d_assoc=2 797635SBrad.Beckmann@amd.comoptions.l1i_assoc=2 807635SBrad.Beckmann@amd.comoptions.l2_assoc=2 817635SBrad.Beckmann@amd.comoptions.l3_assoc=2 827635SBrad.Beckmann@amd.com 837635SBrad.Beckmann@amd.comif args: 847635SBrad.Beckmann@amd.com print "Error: script doesn't take any positional arguments" 857635SBrad.Beckmann@amd.com sys.exit(1) 867635SBrad.Beckmann@amd.com 877635SBrad.Beckmann@amd.comblock_size = 64 887635SBrad.Beckmann@amd.com 897635SBrad.Beckmann@amd.comif options.num_cpus > block_size: 907635SBrad.Beckmann@amd.com print "Error: Number of testers %d limited to %d because of false sharing" \ 917635SBrad.Beckmann@amd.com % (options.num_cpus, block_size) 927635SBrad.Beckmann@amd.com sys.exit(1) 937635SBrad.Beckmann@amd.com 947635SBrad.Beckmann@amd.com# 958436SBrad.Beckmann@amd.com# Currently ruby does not support atomic or uncacheable accesses 967635SBrad.Beckmann@amd.com# 978437SBrad.Beckmann@amd.comcpus = [ MemTest(atomic = False, 988437SBrad.Beckmann@amd.com max_loads = options.maxloads, 998437SBrad.Beckmann@amd.com issue_dmas = False, 1008437SBrad.Beckmann@amd.com percent_functional = options.functional, 1018437SBrad.Beckmann@amd.com percent_uncacheable = 0, 1028437SBrad.Beckmann@amd.com progress_interval = options.progress, 1038436SBrad.Beckmann@amd.com suppress_func_warnings = options.suppress_func_warnings) \ 1047635SBrad.Beckmann@amd.com for i in xrange(options.num_cpus) ] 1057635SBrad.Beckmann@amd.com 1067635SBrad.Beckmann@amd.comsystem = System(cpu = cpus, 1078931Sandreas.hansson@arm.com funcmem = SimpleMemory(in_addr_map = False), 10810720Sandreas.hansson@arm.com funcbus = IOXBar(), 1099909Snilay@cs.wisc.edu clk_domain = SrcClockDomain(clock = options.sys_clock), 1109909Snilay@cs.wisc.edu mem_ranges = [AddrRange(options.mem_size)]) 1117635SBrad.Beckmann@amd.com 1127635SBrad.Beckmann@amd.comif options.num_dmas > 0: 1138437SBrad.Beckmann@amd.com dmas = [ MemTest(atomic = False, 1148437SBrad.Beckmann@amd.com max_loads = options.maxloads, 1158437SBrad.Beckmann@amd.com issue_dmas = True, 1168437SBrad.Beckmann@amd.com percent_functional = 0, 1178437SBrad.Beckmann@amd.com percent_uncacheable = 0, 1188437SBrad.Beckmann@amd.com progress_interval = options.progress, 1198929Snilay@cs.wisc.edu suppress_func_warnings = 1208929Snilay@cs.wisc.edu not options.suppress_func_warnings) \ 1217635SBrad.Beckmann@amd.com for i in xrange(options.num_dmas) ] 1227635SBrad.Beckmann@amd.com system.dma_devices = dmas 1237635SBrad.Beckmann@amd.comelse: 1247635SBrad.Beckmann@amd.com dmas = [] 1257635SBrad.Beckmann@amd.com 1268929Snilay@cs.wisc.edudma_ports = [] 1278929Snilay@cs.wisc.edufor (i, dma) in enumerate(dmas): 1288929Snilay@cs.wisc.edu dma_ports.append(dma.test) 12910519Snilay@cs.wisc.eduRuby.create_system(options, False, system, dma_ports = dma_ports) 1307635SBrad.Beckmann@amd.com 1319909Snilay@cs.wisc.edu# Create a top-level voltage domain and clock domain 1329909Snilay@cs.wisc.edusystem.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 1339909Snilay@cs.wisc.edusystem.clk_domain = SrcClockDomain(clock = options.sys_clock, 1349909Snilay@cs.wisc.edu voltage_domain = system.voltage_domain) 1359793Sakash.bagdia@arm.com# Create a seperate clock domain for Ruby 1369909Snilay@cs.wisc.edusystem.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 1379909Snilay@cs.wisc.edu voltage_domain = system.voltage_domain) 1389793Sakash.bagdia@arm.com 1397635SBrad.Beckmann@amd.com# 1407635SBrad.Beckmann@amd.com# The tester is most effective when randomization is turned on and 1417635SBrad.Beckmann@amd.com# artifical delay is randomly inserted on messages 1427635SBrad.Beckmann@amd.com# 1437635SBrad.Beckmann@amd.comsystem.ruby.randomization = True 14411320Ssteve.reinhardt@amd.com 14510120Snilay@cs.wisc.eduassert(len(cpus) == len(system.ruby._cpu_ports)) 1467635SBrad.Beckmann@amd.com 1477635SBrad.Beckmann@amd.comfor (i, cpu) in enumerate(cpus): 1487635SBrad.Beckmann@amd.com # 1497635SBrad.Beckmann@amd.com # Tie the cpu memtester ports to the correct system ports 1507635SBrad.Beckmann@amd.com # 15110120Snilay@cs.wisc.edu cpu.test = system.ruby._cpu_ports[i].slave 1529120Sandreas.hansson@arm.com cpu.functional = system.funcbus.slave 1537635SBrad.Beckmann@amd.com 1547938SBrad.Beckmann@amd.com # 1557938SBrad.Beckmann@amd.com # Since the memtester is incredibly bursty, increase the deadlock 1567938SBrad.Beckmann@amd.com # threshold to 5 million cycles 1577938SBrad.Beckmann@amd.com # 15810120Snilay@cs.wisc.edu system.ruby._cpu_ports[i].deadlock_threshold = 5000000 1597938SBrad.Beckmann@amd.com 1607635SBrad.Beckmann@amd.comfor (i, dma) in enumerate(dmas): 1617635SBrad.Beckmann@amd.com # 1627635SBrad.Beckmann@amd.com # Tie the dma memtester ports to the correct functional port 1637635SBrad.Beckmann@amd.com # Note that the test port has already been connected to the dma_sequencer 1647635SBrad.Beckmann@amd.com # 1659120Sandreas.hansson@arm.com dma.functional = system.funcbus.slave 1669120Sandreas.hansson@arm.com 1679120Sandreas.hansson@arm.com# connect reference memory to funcbus 1689120Sandreas.hansson@arm.comsystem.funcbus.master = system.funcmem.port 1697635SBrad.Beckmann@amd.com 1707635SBrad.Beckmann@amd.com# ----------------------- 1717635SBrad.Beckmann@amd.com# run simulation 1727635SBrad.Beckmann@amd.com# ----------------------- 1737635SBrad.Beckmann@amd.com 1748801Sgblack@eecs.umich.eduroot = Root( full_system = False, system = system ) 1757635SBrad.Beckmann@amd.comroot.system.mem_mode = 'timing' 1767635SBrad.Beckmann@amd.com 1777635SBrad.Beckmann@amd.com# Not much point in this being higher than the L1 latency 1787635SBrad.Beckmann@amd.comm5.ticks.setGlobalFrequency('1ns') 1797635SBrad.Beckmann@amd.com 1807635SBrad.Beckmann@amd.com# instantiate configuration 1817635SBrad.Beckmann@amd.comm5.instantiate() 1827635SBrad.Beckmann@amd.com 1837635SBrad.Beckmann@amd.com# simulate until program terminates 1849909Snilay@cs.wisc.eduexit_event = m5.simulate(options.abs_max_tick) 1857635SBrad.Beckmann@amd.com 1867635SBrad.Beckmann@amd.comprint 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause() 187