ruby_direct_test.py revision 8931
1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; 9# redistributions in binary form must reproduce the above copyright 10# notice, this list of conditions and the following disclaimer in the 11# documentation and/or other materials provided with the distribution; 12# neither the name of the copyright holders nor the names of its 13# contributors may be used to endorse or promote products derived from 14# this software without specific prior written permission. 15# 16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27# 28# Authors: Ron Dreslinski 29# Brad Beckmann 30 31import m5 32from m5.objects import * 33from m5.defines import buildEnv 34from m5.util import addToPath 35import os, optparse, sys 36addToPath('../common') 37addToPath('../ruby') 38 39import Options 40import Ruby 41 42# Get paths we might need. It's expected this file is in m5/configs/example. 43config_path = os.path.dirname(os.path.abspath(__file__)) 44config_root = os.path.dirname(config_path) 45m5_root = os.path.dirname(config_root) 46 47parser = optparse.OptionParser() 48Options.addCommonOptions(parser) 49 50parser.add_option("-l", "--requests", metavar="N", default=100, 51 help="Stop after N requests") 52parser.add_option("-f", "--wakeup_freq", metavar="N", default=10, 53 help="Wakeup every N cycles") 54parser.add_option("--test-type", type="string", default="SeriesGetx", 55 help="SeriesGetx|SeriesGets|Invalidate") 56 57# 58# Add the ruby specific and protocol specific options 59# 60Ruby.define_options(parser) 61 62execfile(os.path.join(config_root, "common", "Options.py")) 63 64(options, args) = parser.parse_args() 65 66if args: 67 print "Error: script doesn't take any positional arguments" 68 sys.exit(1) 69 70# 71# Select the direct test generator 72# 73if options.test_type == "SeriesGetx": 74 generator = SeriesRequestGenerator(num_cpus = options.num_cpus, 75 issue_writes = True) 76elif options.test_type == "SeriesGets": 77 generator = SeriesRequestGenerator(num_cpus = options.num_cpus, 78 issue_writes = False) 79elif options.test_type == "Invalidate": 80 generator = InvalidateGenerator(num_cpus = options.num_cpus) 81else: 82 print "Error: unknown direct test generator" 83 sys.exit(1) 84 85# 86# Create the M5 system. Note that the Memory Object isn't 87# actually used by the rubytester, but is included to support the 88# M5 memory size == Ruby memory size checks 89# 90system = System(physmem = SimpleMemory()) 91 92# 93# Create the ruby random tester 94# 95system.tester = RubyDirectedTester(requests_to_complete = \ 96 options.requests, 97 generator = generator) 98 99Ruby.create_system(options, system) 100 101assert(options.num_cpus == len(system.ruby._cpu_ruby_ports)) 102 103for ruby_port in system.ruby._cpu_ruby_ports: 104 # 105 # Tie the ruby tester ports to the ruby cpu ports 106 # 107 system.tester.cpuPort = ruby_port.slave 108 109# ----------------------- 110# run simulation 111# ----------------------- 112 113root = Root( full_system = False, system = system ) 114root.system.mem_mode = 'timing' 115 116# Not much point in this being higher than the L1 latency 117m5.ticks.setGlobalFrequency('1ns') 118 119# instantiate configuration 120m5.instantiate() 121 122# simulate until program terminates 123exit_event = m5.simulate(options.maxtick) 124 125print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause() 126