ruby_direct_test.py revision 8928:051bc173ea72
16691Stjones1@inf.ed.ac.uk# Copyright (c) 2006-2007 The Regents of The University of Michigan
26691Stjones1@inf.ed.ac.uk# Copyright (c) 2009 Advanced Micro Devices, Inc.
36691Stjones1@inf.ed.ac.uk# All rights reserved.
46691Stjones1@inf.ed.ac.uk#
56691Stjones1@inf.ed.ac.uk# Redistribution and use in source and binary forms, with or without
66691Stjones1@inf.ed.ac.uk# modification, are permitted provided that the following conditions are
76691Stjones1@inf.ed.ac.uk# met: redistributions of source code must retain the above copyright
86691Stjones1@inf.ed.ac.uk# notice, this list of conditions and the following disclaimer;
96691Stjones1@inf.ed.ac.uk# redistributions in binary form must reproduce the above copyright
106691Stjones1@inf.ed.ac.uk# notice, this list of conditions and the following disclaimer in the
116691Stjones1@inf.ed.ac.uk# documentation and/or other materials provided with the distribution;
126691Stjones1@inf.ed.ac.uk# neither the name of the copyright holders nor the names of its
136691Stjones1@inf.ed.ac.uk# contributors may be used to endorse or promote products derived from
146691Stjones1@inf.ed.ac.uk# this software without specific prior written permission.
156691Stjones1@inf.ed.ac.uk#
166691Stjones1@inf.ed.ac.uk# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
176691Stjones1@inf.ed.ac.uk# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
186691Stjones1@inf.ed.ac.uk# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
196691Stjones1@inf.ed.ac.uk# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
206691Stjones1@inf.ed.ac.uk# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
216691Stjones1@inf.ed.ac.uk# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
226691Stjones1@inf.ed.ac.uk# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
236691Stjones1@inf.ed.ac.uk# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
246691Stjones1@inf.ed.ac.uk# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
256691Stjones1@inf.ed.ac.uk# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
266691Stjones1@inf.ed.ac.uk# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
276691Stjones1@inf.ed.ac.uk#
286691Stjones1@inf.ed.ac.uk# Authors: Ron Dreslinski
296691Stjones1@inf.ed.ac.uk#          Brad Beckmann
306691Stjones1@inf.ed.ac.uk
316691Stjones1@inf.ed.ac.ukimport m5
326691Stjones1@inf.ed.ac.ukfrom m5.objects import *
336691Stjones1@inf.ed.ac.ukfrom m5.defines import buildEnv
346691Stjones1@inf.ed.ac.ukfrom m5.util import addToPath
356691Stjones1@inf.ed.ac.ukimport os, optparse, sys
366691Stjones1@inf.ed.ac.ukaddToPath('../common')
376691Stjones1@inf.ed.ac.ukaddToPath('../ruby')
386691Stjones1@inf.ed.ac.uk
396691Stjones1@inf.ed.ac.ukimport Options
406691Stjones1@inf.ed.ac.ukimport Ruby
416691Stjones1@inf.ed.ac.uk
426691Stjones1@inf.ed.ac.uk# Get paths we might need.  It's expected this file is in m5/configs/example.
436691Stjones1@inf.ed.ac.ukconfig_path = os.path.dirname(os.path.abspath(__file__))
446691Stjones1@inf.ed.ac.ukconfig_root = os.path.dirname(config_path)
456691Stjones1@inf.ed.ac.ukm5_root = os.path.dirname(config_root)
466691Stjones1@inf.ed.ac.uk
476691Stjones1@inf.ed.ac.ukparser = optparse.OptionParser()
486691Stjones1@inf.ed.ac.ukOptions.addCommonOptions(parser)
496691Stjones1@inf.ed.ac.uk
5012385Sgabeblack@google.comparser.add_option("-l", "--requests", metavar="N", default=100,
516691Stjones1@inf.ed.ac.uk                  help="Stop after N requests")
5212385Sgabeblack@google.comparser.add_option("-f", "--wakeup_freq", metavar="N", default=10,
536691Stjones1@inf.ed.ac.uk                  help="Wakeup every N cycles")
546691Stjones1@inf.ed.ac.ukparser.add_option("--test-type", type="string", default="SeriesGetx",
556691Stjones1@inf.ed.ac.uk                  help="SeriesGetx|SeriesGets|Invalidate")
5612616Sgabeblack@google.com
5712616Sgabeblack@google.com#
586691Stjones1@inf.ed.ac.uk# Add the ruby specific and protocol specific options
596691Stjones1@inf.ed.ac.uk#
606691Stjones1@inf.ed.ac.ukRuby.define_options(parser)
616691Stjones1@inf.ed.ac.uk
626691Stjones1@inf.ed.ac.ukexecfile(os.path.join(config_root, "common", "Options.py"))
636691Stjones1@inf.ed.ac.uk
646691Stjones1@inf.ed.ac.uk(options, args) = parser.parse_args()
656691Stjones1@inf.ed.ac.uk
666691Stjones1@inf.ed.ac.ukif args:
676691Stjones1@inf.ed.ac.uk     print "Error: script doesn't take any positional arguments"
686691Stjones1@inf.ed.ac.uk     sys.exit(1)
696691Stjones1@inf.ed.ac.uk
706691Stjones1@inf.ed.ac.uk#
7112385Sgabeblack@google.com# Select the direct test generator
7212385Sgabeblack@google.com#
736691Stjones1@inf.ed.ac.ukif options.test_type == "SeriesGetx":
746691Stjones1@inf.ed.ac.uk    generator = SeriesRequestGenerator(num_cpus = options.num_cpus,
756691Stjones1@inf.ed.ac.uk                                             issue_writes = True)
7612616Sgabeblack@google.comelif options.test_type == "SeriesGets":
7712616Sgabeblack@google.com    generator = SeriesRequestGenerator(num_cpus = options.num_cpus,
786691Stjones1@inf.ed.ac.uk                                             issue_writes = False)
796691Stjones1@inf.ed.ac.ukelif options.test_type == "Invalidate":
807811Ssteve.reinhardt@amd.com    generator = InvalidateGenerator(num_cpus = options.num_cpus)
816691Stjones1@inf.ed.ac.ukelse:
826691Stjones1@inf.ed.ac.uk    print "Error: unknown direct test generator"
83    sys.exit(1)
84
85#
86# Create the M5 system.  Note that the PhysicalMemory Object isn't
87# actually used by the rubytester, but is included to support the
88# M5 memory size == Ruby memory size checks
89#
90system = System(physmem = PhysicalMemory())
91
92#
93# Create the ruby random tester
94#
95system.tester = RubyDirectedTester(requests_to_complete = \
96                                   options.requests,
97                                   generator = generator)
98
99Ruby.create_system(options, system)
100
101assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
102
103for ruby_port in system.ruby._cpu_ruby_ports:
104    #
105    # Tie the ruby tester ports to the ruby cpu ports
106    #
107    system.tester.cpuPort = ruby_port.slave
108
109# -----------------------
110# run simulation
111# -----------------------
112
113root = Root( full_system = False, system = system )
114root.system.mem_mode = 'timing'
115
116# Not much point in this being higher than the L1 latency
117m5.ticks.setGlobalFrequency('1ns')
118
119# instantiate configuration
120m5.instantiate()
121
122# simulate until program terminates
123exit_event = m5.simulate(options.maxtick)
124
125print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
126