ruby_direct_test.py revision 8803:f6c5785bc8fd
16145SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 26386SN/A# Copyright (c) 2009 Advanced Micro Devices, Inc. 37553SN/A# All rights reserved. 46386SN/A# 56386SN/A# Redistribution and use in source and binary forms, with or without 66386SN/A# modification, are permitted provided that the following conditions are 76386SN/A# met: redistributions of source code must retain the above copyright 86386SN/A# notice, this list of conditions and the following disclaimer; 96386SN/A# redistributions in binary form must reproduce the above copyright 106386SN/A# notice, this list of conditions and the following disclaimer in the 116386SN/A# documentation and/or other materials provided with the distribution; 126386SN/A# neither the name of the copyright holders nor the names of its 136386SN/A# contributors may be used to endorse or promote products derived from 146386SN/A# this software without specific prior written permission. 156386SN/A# 166386SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176386SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186386SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196386SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206386SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216386SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226386SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236386SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246386SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256386SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266386SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276386SN/A# 286386SN/A# Authors: Ron Dreslinski 296145SN/A# Brad Beckmann 307632SBrad.Beckmann@amd.com 3111793Sbrandon.potter@amd.comimport m5 328832SAli.Saidi@ARM.comfrom m5.objects import * 336145SN/Afrom m5.defines import buildEnv 347553SN/Afrom m5.util import addToPath 358832SAli.Saidi@ARM.comimport os, optparse, sys 3612680Sgiacomo.travaglini@arm.comaddToPath('../common') 376145SN/AaddToPath('../ruby') 387553SN/A 397553SN/Aimport Ruby 406145SN/A 416145SN/A# Get paths we might need. It's expected this file is in m5/configs/example. 4211320Ssteve.reinhardt@amd.comconfig_path = os.path.dirname(os.path.abspath(__file__)) 437553SN/Aconfig_root = os.path.dirname(config_path) 446145SN/Am5_root = os.path.dirname(config_root) 457553SN/A 467553SN/Aparser = optparse.OptionParser() 476145SN/A 48parser.add_option("-l", "--requests", metavar="N", default=100, 49 help="Stop after N requests") 50parser.add_option("-f", "--wakeup_freq", metavar="N", default=10, 51 help="Wakeup every N cycles") 52parser.add_option("--test-type", type="string", default="SeriesGetx", 53 help="SeriesGetx|SeriesGets|Invalidate") 54 55# 56# Add the ruby specific and protocol specific options 57# 58Ruby.define_options(parser) 59 60execfile(os.path.join(config_root, "common", "Options.py")) 61 62(options, args) = parser.parse_args() 63 64if args: 65 print "Error: script doesn't take any positional arguments" 66 sys.exit(1) 67 68# 69# Select the direct test generator 70# 71if options.test_type == "SeriesGetx": 72 generator = SeriesRequestGenerator(num_cpus = options.num_cpus, 73 issue_writes = True) 74elif options.test_type == "SeriesGets": 75 generator = SeriesRequestGenerator(num_cpus = options.num_cpus, 76 issue_writes = False) 77elif options.test_type == "Invalidate": 78 generator = InvalidateGenerator(num_cpus = options.num_cpus) 79else: 80 print "Error: unknown direct test generator" 81 sys.exit(1) 82 83# 84# Create the M5 system. Note that the PhysicalMemory Object isn't 85# actually used by the rubytester, but is included to support the 86# M5 memory size == Ruby memory size checks 87# 88system = System(physmem = PhysicalMemory()) 89 90# 91# Create the ruby random tester 92# 93system.tester = RubyDirectedTester(requests_to_complete = \ 94 options.requests, 95 generator = generator) 96 97Ruby.create_system(options, system) 98 99assert(options.num_cpus == len(system.ruby._cpu_ruby_ports)) 100 101for ruby_port in system.ruby._cpu_ruby_ports: 102 # 103 # Tie the ruby tester ports to the ruby cpu ports 104 # 105 system.tester.cpuPort = ruby_port.port 106 107# ----------------------- 108# run simulation 109# ----------------------- 110 111root = Root( full_system = False, system = system ) 112root.system.mem_mode = 'timing' 113 114# Not much point in this being higher than the L1 latency 115m5.ticks.setGlobalFrequency('1ns') 116 117# instantiate configuration 118m5.instantiate() 119 120# simulate until program terminates 121exit_event = m5.simulate(options.maxtick) 122 123print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause() 124