ruby_direct_test.py revision 7632
113481Sgiacomo.travaglini@arm.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 213481Sgiacomo.travaglini@arm.com# Copyright (c) 2009 Advanced Micro Devices, Inc. 313481Sgiacomo.travaglini@arm.com# All rights reserved. 413481Sgiacomo.travaglini@arm.com# 513481Sgiacomo.travaglini@arm.com# Redistribution and use in source and binary forms, with or without 613481Sgiacomo.travaglini@arm.com# modification, are permitted provided that the following conditions are 713481Sgiacomo.travaglini@arm.com# met: redistributions of source code must retain the above copyright 813481Sgiacomo.travaglini@arm.com# notice, this list of conditions and the following disclaimer; 913481Sgiacomo.travaglini@arm.com# redistributions in binary form must reproduce the above copyright 1013481Sgiacomo.travaglini@arm.com# notice, this list of conditions and the following disclaimer in the 1113481Sgiacomo.travaglini@arm.com# documentation and/or other materials provided with the distribution; 1213481Sgiacomo.travaglini@arm.com# neither the name of the copyright holders nor the names of its 1313481Sgiacomo.travaglini@arm.com# contributors may be used to endorse or promote products derived from 1413481Sgiacomo.travaglini@arm.com# this software without specific prior written permission. 1513481Sgiacomo.travaglini@arm.com# 1613481Sgiacomo.travaglini@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1713481Sgiacomo.travaglini@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1813481Sgiacomo.travaglini@arm.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1913481Sgiacomo.travaglini@arm.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2013481Sgiacomo.travaglini@arm.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2113481Sgiacomo.travaglini@arm.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2213481Sgiacomo.travaglini@arm.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2313481Sgiacomo.travaglini@arm.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2413481Sgiacomo.travaglini@arm.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2513481Sgiacomo.travaglini@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2613481Sgiacomo.travaglini@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2713481Sgiacomo.travaglini@arm.com# 2813481Sgiacomo.travaglini@arm.com# Authors: Ron Dreslinski 2913481Sgiacomo.travaglini@arm.com# Brad Beckmann 3013481Sgiacomo.travaglini@arm.com 3113481Sgiacomo.travaglini@arm.comimport m5 3213481Sgiacomo.travaglini@arm.comfrom m5.objects import * 3313481Sgiacomo.travaglini@arm.comfrom m5.defines import buildEnv 3413481Sgiacomo.travaglini@arm.comfrom m5.util import addToPath 3513481Sgiacomo.travaglini@arm.comimport os, optparse, sys 3613481Sgiacomo.travaglini@arm.comaddToPath('../common') 3713481Sgiacomo.travaglini@arm.comaddToPath('../ruby') 3813481Sgiacomo.travaglini@arm.com 3913481Sgiacomo.travaglini@arm.comimport Ruby 4013481Sgiacomo.travaglini@arm.com 4113481Sgiacomo.travaglini@arm.comif buildEnv['FULL_SYSTEM']: 4213481Sgiacomo.travaglini@arm.com panic("This script requires system-emulation mode (*_SE).") 4313481Sgiacomo.travaglini@arm.com 4413481Sgiacomo.travaglini@arm.com# Get paths we might need. It's expected this file is in m5/configs/example. 4513481Sgiacomo.travaglini@arm.comconfig_path = os.path.dirname(os.path.abspath(__file__)) 4613481Sgiacomo.travaglini@arm.comconfig_root = os.path.dirname(config_path) 4713481Sgiacomo.travaglini@arm.comm5_root = os.path.dirname(config_root) 4813481Sgiacomo.travaglini@arm.com 4913481Sgiacomo.travaglini@arm.comparser = optparse.OptionParser() 5013481Sgiacomo.travaglini@arm.com 5113481Sgiacomo.travaglini@arm.comparser.add_option("-l", "--requests", metavar="N", default=100, 5213481Sgiacomo.travaglini@arm.com help="Stop after N requests") 5313481Sgiacomo.travaglini@arm.comparser.add_option("-f", "--wakeup_freq", metavar="N", default=10, 5413481Sgiacomo.travaglini@arm.com help="Wakeup every N cycles") 5513481Sgiacomo.travaglini@arm.comparser.add_option("--test-type", type="string", default="SeriesGetx", 5613481Sgiacomo.travaglini@arm.com help="SeriesGetx|SeriesGets|Invalidate") 5713481Sgiacomo.travaglini@arm.com 5813481Sgiacomo.travaglini@arm.com# 5913481Sgiacomo.travaglini@arm.com# Add the ruby specific and protocol specific options 6013481Sgiacomo.travaglini@arm.com# 6113481Sgiacomo.travaglini@arm.comRuby.define_options(parser) 6213481Sgiacomo.travaglini@arm.com 6313481Sgiacomo.travaglini@arm.comexecfile(os.path.join(config_root, "common", "Options.py")) 6413481Sgiacomo.travaglini@arm.com 6513481Sgiacomo.travaglini@arm.com(options, args) = parser.parse_args() 6613481Sgiacomo.travaglini@arm.com 6713481Sgiacomo.travaglini@arm.comif args: 6813481Sgiacomo.travaglini@arm.com print "Error: script doesn't take any positional arguments" 6913481Sgiacomo.travaglini@arm.com sys.exit(1) 7013481Sgiacomo.travaglini@arm.com 7113481Sgiacomo.travaglini@arm.com# 7213481Sgiacomo.travaglini@arm.com# Select the direct test generator 7313481Sgiacomo.travaglini@arm.com# 7413481Sgiacomo.travaglini@arm.comif options.test_type == "SeriesGetx": 7513481Sgiacomo.travaglini@arm.com generator = SeriesRequestGenerator(num_cpus = options.num_cpus, 7613481Sgiacomo.travaglini@arm.com issue_writes = True) 7713481Sgiacomo.travaglini@arm.comelif options.test_type == "SeriesGets": 7813481Sgiacomo.travaglini@arm.com generator = SeriesRequestGenerator(num_cpus = options.num_cpus, 7913481Sgiacomo.travaglini@arm.com issue_writes = False) 8013481Sgiacomo.travaglini@arm.comelif options.test_type == "Invalidate": 8113481Sgiacomo.travaglini@arm.com generator = InvalidateGenerator(num_cpus = options.num_cpus) 8213481Sgiacomo.travaglini@arm.comelse: 8313481Sgiacomo.travaglini@arm.com print "Error: unknown direct test generator" 8413481Sgiacomo.travaglini@arm.com sys.exit(1) 8513481Sgiacomo.travaglini@arm.com 8613481Sgiacomo.travaglini@arm.com# 8713481Sgiacomo.travaglini@arm.com# Create the M5 system. Note that the PhysicalMemory Object isn't 8813481Sgiacomo.travaglini@arm.com# actually used by the rubytester, but is included to support the 8913481Sgiacomo.travaglini@arm.com# M5 memory size == Ruby memory size checks 9013481Sgiacomo.travaglini@arm.com# 9113481Sgiacomo.travaglini@arm.comsystem = System(physmem = PhysicalMemory()) 9213481Sgiacomo.travaglini@arm.com 9313481Sgiacomo.travaglini@arm.com# 9413481Sgiacomo.travaglini@arm.com# Create the ruby random tester 9513481Sgiacomo.travaglini@arm.com# 9613481Sgiacomo.travaglini@arm.comsystem.tester = RubyDirectedTester(requests_to_complete = \ 9713481Sgiacomo.travaglini@arm.com options.requests, 9813481Sgiacomo.travaglini@arm.com generator = generator) 9913481Sgiacomo.travaglini@arm.com 10013481Sgiacomo.travaglini@arm.comsystem.ruby = Ruby.create_system(options, system) 10113481Sgiacomo.travaglini@arm.com 10213481Sgiacomo.travaglini@arm.comassert(options.num_cpus == len(system.ruby.cpu_ruby_ports)) 10313481Sgiacomo.travaglini@arm.com 10413481Sgiacomo.travaglini@arm.comfor ruby_port in system.ruby.cpu_ruby_ports: 10513481Sgiacomo.travaglini@arm.com # 10613481Sgiacomo.travaglini@arm.com # Tie the ruby tester ports to the ruby cpu ports 10713481Sgiacomo.travaglini@arm.com # 10813481Sgiacomo.travaglini@arm.com system.tester.cpuPort = ruby_port.port 10913481Sgiacomo.travaglini@arm.com 11013481Sgiacomo.travaglini@arm.com# ----------------------- 11113481Sgiacomo.travaglini@arm.com# run simulation 11213481Sgiacomo.travaglini@arm.com# ----------------------- 11313481Sgiacomo.travaglini@arm.com 11413481Sgiacomo.travaglini@arm.comroot = Root( system = system ) 11513481Sgiacomo.travaglini@arm.comroot.system.mem_mode = 'timing' 11613481Sgiacomo.travaglini@arm.com 11713481Sgiacomo.travaglini@arm.com# Not much point in this being higher than the L1 latency 11813481Sgiacomo.travaglini@arm.comm5.ticks.setGlobalFrequency('1ns') 11913481Sgiacomo.travaglini@arm.com 12013481Sgiacomo.travaglini@arm.com# instantiate configuration 12113481Sgiacomo.travaglini@arm.comm5.instantiate() 12213481Sgiacomo.travaglini@arm.com 12313481Sgiacomo.travaglini@arm.com# simulate until program terminates 12413481Sgiacomo.travaglini@arm.comexit_event = m5.simulate(options.maxtick) 12513481Sgiacomo.travaglini@arm.com 12613481Sgiacomo.travaglini@arm.comprint 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause() 12713481Sgiacomo.travaglini@arm.com