ruby_direct_test.py revision 11670
1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; 9# redistributions in binary form must reproduce the above copyright 10# notice, this list of conditions and the following disclaimer in the 11# documentation and/or other materials provided with the distribution; 12# neither the name of the copyright holders nor the names of its 13# contributors may be used to endorse or promote products derived from 14# this software without specific prior written permission. 15# 16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27# 28# Authors: Ron Dreslinski 29# Brad Beckmann 30 31import m5 32from m5.objects import * 33from m5.defines import buildEnv 34from m5.util import addToPath 35import os, optparse, sys 36addToPath('../common') 37addToPath('../') 38 39import Options 40from ruby import Ruby 41 42# Get paths we might need. It's expected this file is in m5/configs/example. 43config_path = os.path.dirname(os.path.abspath(__file__)) 44config_root = os.path.dirname(config_path) 45m5_root = os.path.dirname(config_root) 46 47parser = optparse.OptionParser() 48Options.addCommonOptions(parser) 49 50parser.add_option("--requests", metavar="N", default=100, 51 help="Stop after N requests") 52parser.add_option("-f", "--wakeup_freq", metavar="N", default=10, 53 help="Wakeup every N cycles") 54parser.add_option("--test-type", type="choice", default="SeriesGetx", 55 choices = ["SeriesGetx", "SeriesGets", "SeriesGetMixed", 56 "Invalidate"], 57 help = "Type of test") 58parser.add_option("--percent-writes", type="int", default=100, 59 help="percentage of accesses that should be writes") 60 61# 62# Add the ruby specific and protocol specific options 63# 64Ruby.define_options(parser) 65(options, args) = parser.parse_args() 66 67if args: 68 print "Error: script doesn't take any positional arguments" 69 sys.exit(1) 70 71# 72# Select the direct test generator 73# 74if options.test_type == "SeriesGetx": 75 generator = SeriesRequestGenerator(num_cpus = options.num_cpus, 76 percent_writes = 100) 77elif options.test_type == "SeriesGets": 78 generator = SeriesRequestGenerator(num_cpus = options.num_cpus, 79 percent_writes = 0) 80elif options.test_type == "SeriesGetMixed": 81 generator = SeriesRequestGenerator(num_cpus = options.num_cpus, 82 percent_writes = options.percent_writes) 83elif options.test_type == "Invalidate": 84 generator = InvalidateGenerator(num_cpus = options.num_cpus) 85else: 86 print "Error: unknown direct test generator" 87 sys.exit(1) 88 89# Create the M5 system. 90system = System(mem_ranges = [AddrRange(options.mem_size)]) 91 92 93# Create a top-level voltage domain and clock domain 94system.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 95 96system.clk_domain = SrcClockDomain(clock = options.sys_clock, 97 voltage_domain = system.voltage_domain) 98 99# Create the ruby random tester 100system.cpu = RubyDirectedTester(requests_to_complete = options.requests, 101 generator = generator) 102 103Ruby.create_system(options, False, system) 104 105# Since Ruby runs at an independent frequency, create a seperate clock 106system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 107 voltage_domain = system.voltage_domain) 108 109assert(options.num_cpus == len(system.ruby._cpu_ports)) 110 111for ruby_port in system.ruby._cpu_ports: 112 # 113 # Tie the ruby tester ports to the ruby cpu ports 114 # 115 system.cpu.cpuPort = ruby_port.slave 116 117# ----------------------- 118# run simulation 119# ----------------------- 120 121root = Root( full_system = False, system = system ) 122root.system.mem_mode = 'timing' 123 124# Not much point in this being higher than the L1 latency 125m5.ticks.setGlobalFrequency('1ns') 126 127# instantiate configuration 128m5.instantiate() 129 130# simulate until program terminates 131exit_event = m5.simulate(options.abs_max_tick) 132 133print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause() 134