ruby_direct_test.py revision 11662:004d34b65092 
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Ron Dreslinski
29#          Brad Beckmann
30
31import m5
32from m5.objects import *
33from m5.defines import buildEnv
34from m5.util import addToPath
35import os, optparse, sys
36addToPath('../common')
37addToPath('../ruby')
38addToPath('../network')
39addToPath('../topologies')
40
41import Options
42import Ruby
43import Network
44
45# Get paths we might need.  It's expected this file is in m5/configs/example.
46config_path = os.path.dirname(os.path.abspath(__file__))
47config_root = os.path.dirname(config_path)
48m5_root = os.path.dirname(config_root)
49
50parser = optparse.OptionParser()
51Options.addCommonOptions(parser)
52
53parser.add_option("--requests", metavar="N", default=100,
54                  help="Stop after N requests")
55parser.add_option("-f", "--wakeup_freq", metavar="N", default=10,
56                  help="Wakeup every N cycles")
57parser.add_option("--test-type", type="choice", default="SeriesGetx",
58                  choices = ["SeriesGetx", "SeriesGets", "SeriesGetMixed",
59                             "Invalidate"],
60                  help = "Type of test")
61parser.add_option("--percent-writes", type="int", default=100,
62                  help="percentage of accesses that should be writes")
63
64#
65# Add the ruby specific and protocol specific options
66#
67Ruby.define_options(parser)
68Network.define_options(parser)
69(options, args) = parser.parse_args()
70
71if args:
72     print "Error: script doesn't take any positional arguments"
73     sys.exit(1)
74
75#
76# Select the direct test generator
77#
78if options.test_type == "SeriesGetx":
79    generator = SeriesRequestGenerator(num_cpus = options.num_cpus,
80                                       percent_writes = 100)
81elif options.test_type == "SeriesGets":
82    generator = SeriesRequestGenerator(num_cpus = options.num_cpus,
83                                       percent_writes = 0)
84elif options.test_type == "SeriesGetMixed":
85    generator = SeriesRequestGenerator(num_cpus = options.num_cpus,
86                                       percent_writes = options.percent_writes)
87elif options.test_type == "Invalidate":
88    generator = InvalidateGenerator(num_cpus = options.num_cpus)
89else:
90    print "Error: unknown direct test generator"
91    sys.exit(1)
92
93# Create the M5 system.
94system = System(mem_ranges = [AddrRange(options.mem_size)])
95
96
97# Create a top-level voltage domain and clock domain
98system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
99
100system.clk_domain = SrcClockDomain(clock = options.sys_clock,
101                                   voltage_domain = system.voltage_domain)
102
103# Create the ruby random tester
104system.cpu = RubyDirectedTester(requests_to_complete = options.requests,
105                                generator = generator)
106
107Ruby.create_system(options, False, system)
108
109# Since Ruby runs at an independent frequency, create a seperate clock
110system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
111                                        voltage_domain = system.voltage_domain)
112
113assert(options.num_cpus == len(system.ruby._cpu_ports))
114
115for ruby_port in system.ruby._cpu_ports:
116    #
117    # Tie the ruby tester ports to the ruby cpu ports
118    #
119    system.cpu.cpuPort = ruby_port.slave
120
121# -----------------------
122# run simulation
123# -----------------------
124
125root = Root( full_system = False, system = system )
126root.system.mem_mode = 'timing'
127
128# Not much point in this being higher than the L1 latency
129m5.ticks.setGlobalFrequency('1ns')
130
131# instantiate configuration
132m5.instantiate()
133
134# simulate until program terminates
135exit_event = m5.simulate(options.abs_max_tick)
136
137print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
138