ruby_direct_test.py revision 10300
15222Sksewell@umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan 25254Sksewell@umich.edu# Copyright (c) 2009 Advanced Micro Devices, Inc. 35254Sksewell@umich.edu# All rights reserved. 45222Sksewell@umich.edu# 55254Sksewell@umich.edu# Redistribution and use in source and binary forms, with or without 65254Sksewell@umich.edu# modification, are permitted provided that the following conditions are 75254Sksewell@umich.edu# met: redistributions of source code must retain the above copyright 85254Sksewell@umich.edu# notice, this list of conditions and the following disclaimer; 95254Sksewell@umich.edu# redistributions in binary form must reproduce the above copyright 105254Sksewell@umich.edu# notice, this list of conditions and the following disclaimer in the 115254Sksewell@umich.edu# documentation and/or other materials provided with the distribution; 125254Sksewell@umich.edu# neither the name of the copyright holders nor the names of its 135254Sksewell@umich.edu# contributors may be used to endorse or promote products derived from 145254Sksewell@umich.edu# this software without specific prior written permission. 155222Sksewell@umich.edu# 165254Sksewell@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175254Sksewell@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 185254Sksewell@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 195254Sksewell@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205254Sksewell@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215254Sksewell@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225254Sksewell@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235254Sksewell@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245254Sksewell@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255254Sksewell@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265254Sksewell@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 275222Sksewell@umich.edu# 285254Sksewell@umich.edu# Authors: Ron Dreslinski 295222Sksewell@umich.edu# Brad Beckmann 305222Sksewell@umich.edu 3111793Sbrandon.potter@amd.comimport m5 3211793Sbrandon.potter@amd.comfrom m5.objects import * 335222Sksewell@umich.edufrom m5.defines import buildEnv 345222Sksewell@umich.edufrom m5.util import addToPath 355222Sksewell@umich.eduimport os, optparse, sys 365222Sksewell@umich.eduaddToPath('../common') 375222Sksewell@umich.eduaddToPath('../ruby') 385222Sksewell@umich.eduaddToPath('../topologies') 395222Sksewell@umich.edu 405222Sksewell@umich.eduimport Options 418799Sgblack@eecs.umich.eduimport Ruby 425222Sksewell@umich.edu 435222Sksewell@umich.edu# Get paths we might need. It's expected this file is in m5/configs/example. 445222Sksewell@umich.educonfig_path = os.path.dirname(os.path.abspath(__file__)) 455222Sksewell@umich.educonfig_root = os.path.dirname(config_path) 466378Sgblack@eecs.umich.edum5_root = os.path.dirname(config_root) 476378Sgblack@eecs.umich.edu 485222Sksewell@umich.eduparser = optparse.OptionParser() 495222Sksewell@umich.eduOptions.addCommonOptions(parser) 505222Sksewell@umich.edu 515222Sksewell@umich.eduparser.add_option("-l", "--requests", metavar="N", default=100, 525222Sksewell@umich.edu help="Stop after N requests") 535222Sksewell@umich.eduparser.add_option("-f", "--wakeup_freq", metavar="N", default=10, 545222Sksewell@umich.edu help="Wakeup every N cycles") 555222Sksewell@umich.eduparser.add_option("--test-type", type="choice", default="SeriesGetx", 565222Sksewell@umich.edu choices = ["SeriesGetx", "SeriesGets", "SeriesGetMixed", 575222Sksewell@umich.edu "Invalidate"], 588852Sandreas.hansson@arm.com help = "Type of test") 5913893Sgabeblack@google.comparser.add_option("--percent-writes", type="int", default=100, 605222Sksewell@umich.edu help="percentage of accesses that should be writes") 615222Sksewell@umich.edu 625222Sksewell@umich.edu# 635222Sksewell@umich.edu# Add the ruby specific and protocol specific options 645222Sksewell@umich.edu# 655222Sksewell@umich.eduRuby.define_options(parser) 665222Sksewell@umich.edu(options, args) = parser.parse_args() 675222Sksewell@umich.edu 685222Sksewell@umich.eduif args: 695222Sksewell@umich.edu print "Error: script doesn't take any positional arguments" 705222Sksewell@umich.edu sys.exit(1) 715222Sksewell@umich.edu 725222Sksewell@umich.edu# 738852Sandreas.hansson@arm.com# Select the direct test generator 7413893Sgabeblack@google.com# 755222Sksewell@umich.eduif options.test_type == "SeriesGetx": 765222Sksewell@umich.edu generator = SeriesRequestGenerator(num_cpus = options.num_cpus, 775222Sksewell@umich.edu percent_writes = 100) 785222Sksewell@umich.eduelif options.test_type == "SeriesGets": 7913893Sgabeblack@google.com generator = SeriesRequestGenerator(num_cpus = options.num_cpus, 805222Sksewell@umich.edu percent_writes = 0) 815222Sksewell@umich.eduelif options.test_type == "SeriesGetMixed": 825222Sksewell@umich.edu generator = SeriesRequestGenerator(num_cpus = options.num_cpus, 835222Sksewell@umich.edu percent_writes = options.percent_writes) 845222Sksewell@umich.eduelif options.test_type == "Invalidate": 855222Sksewell@umich.edu generator = InvalidateGenerator(num_cpus = options.num_cpus) 865222Sksewell@umich.eduelse: 8714018Sgabeblack@google.com print "Error: unknown direct test generator" 885222Sksewell@umich.edu sys.exit(1) 895222Sksewell@umich.edu 905222Sksewell@umich.edu# 915222Sksewell@umich.edu# Create the M5 system. Note that the Memory Object isn't 925222Sksewell@umich.edu# actually used by the rubytester, but is included to support the 935222Sksewell@umich.edu# M5 memory size == Ruby memory size checks 945222Sksewell@umich.edu# 955222Sksewell@umich.edusystem = System(physmem = SimpleMemory(), 965222Sksewell@umich.edu mem_ranges = [AddrRange(options.mem_size)]) 975222Sksewell@umich.edu 985222Sksewell@umich.edu 9910417Sandreas.hansson@arm.com# Create a top-level voltage domain and clock domain 1005222Sksewell@umich.edusystem.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 1015222Sksewell@umich.edu 1025222Sksewell@umich.edusystem.clk_domain = SrcClockDomain(clock = options.sys_clock, 1035222Sksewell@umich.edu voltage_domain = system.voltage_domain) 1045222Sksewell@umich.edu 1055222Sksewell@umich.edu# 1065222Sksewell@umich.edu# Create the ruby random tester 1075222Sksewell@umich.edu# 1085222Sksewell@umich.edusystem.cpu = RubyDirectedTester(requests_to_complete = \ 1095222Sksewell@umich.edu options.requests, 1105222Sksewell@umich.edu generator = generator) 1115222Sksewell@umich.edu 1125222Sksewell@umich.eduRuby.create_system(options, system) 1135222Sksewell@umich.edu 1145222Sksewell@umich.edu# Since Ruby runs at an independent frequency, create a seperate clock 1155222Sksewell@umich.edusystem.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 1165222Sksewell@umich.edu voltage_domain = system.voltage_domain) 1175222Sksewell@umich.edu 1185222Sksewell@umich.eduassert(options.num_cpus == len(system.ruby._cpu_ports)) 1195222Sksewell@umich.edu 1205222Sksewell@umich.edufor ruby_port in system.ruby._cpu_ports: 1215222Sksewell@umich.edu # 1225222Sksewell@umich.edu # Tie the ruby tester ports to the ruby cpu ports 1235222Sksewell@umich.edu # 1245222Sksewell@umich.edu system.tester.cpuPort = ruby_port.slave 1255222Sksewell@umich.edu 1265222Sksewell@umich.edu# ----------------------- 1275222Sksewell@umich.edu# run simulation 1285222Sksewell@umich.edu# ----------------------- 1295222Sksewell@umich.edu 1305222Sksewell@umich.eduroot = Root( full_system = False, system = system ) 1315222Sksewell@umich.eduroot.system.mem_mode = 'timing' 1325222Sksewell@umich.edu 1335222Sksewell@umich.edu# Not much point in this being higher than the L1 latency 1345222Sksewell@umich.edum5.ticks.setGlobalFrequency('1ns') 1355222Sksewell@umich.edu 1365222Sksewell@umich.edu# instantiate configuration 1375222Sksewell@umich.edum5.instantiate() 1385222Sksewell@umich.edu 1395222Sksewell@umich.edu# simulate until program terminates 1405222Sksewell@umich.eduexit_event = m5.simulate(options.abs_max_tick) 1415222Sksewell@umich.edu 1425222Sksewell@umich.eduprint 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause() 1435222Sksewell@umich.edu