ruby_direct_test.py revision 9909
113481Sgiacomo.travaglini@arm.com# Copyright (c) 2006-2007 The Regents of The University of Michigan
213481Sgiacomo.travaglini@arm.com# Copyright (c) 2009 Advanced Micro Devices, Inc.
313481Sgiacomo.travaglini@arm.com# All rights reserved.
413481Sgiacomo.travaglini@arm.com#
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613481Sgiacomo.travaglini@arm.com# modification, are permitted provided that the following conditions are
713481Sgiacomo.travaglini@arm.com# met: redistributions of source code must retain the above copyright
813481Sgiacomo.travaglini@arm.com# notice, this list of conditions and the following disclaimer;
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1413481Sgiacomo.travaglini@arm.com# this software without specific prior written permission.
1513481Sgiacomo.travaglini@arm.com#
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2713481Sgiacomo.travaglini@arm.com#
2813481Sgiacomo.travaglini@arm.com# Authors: Ron Dreslinski
2913481Sgiacomo.travaglini@arm.com#          Brad Beckmann
3013481Sgiacomo.travaglini@arm.com
3113481Sgiacomo.travaglini@arm.comimport m5
3213481Sgiacomo.travaglini@arm.comfrom m5.objects import *
3313481Sgiacomo.travaglini@arm.comfrom m5.defines import buildEnv
3413481Sgiacomo.travaglini@arm.comfrom m5.util import addToPath
3513481Sgiacomo.travaglini@arm.comimport os, optparse, sys
3613481Sgiacomo.travaglini@arm.comaddToPath('../common')
3713481Sgiacomo.travaglini@arm.comaddToPath('../ruby')
3813481Sgiacomo.travaglini@arm.comaddToPath('../topologies')
3913481Sgiacomo.travaglini@arm.com
4013481Sgiacomo.travaglini@arm.comimport Options
4113481Sgiacomo.travaglini@arm.comimport Ruby
4213481Sgiacomo.travaglini@arm.com
4313481Sgiacomo.travaglini@arm.com# Get paths we might need.  It's expected this file is in m5/configs/example.
4413481Sgiacomo.travaglini@arm.comconfig_path = os.path.dirname(os.path.abspath(__file__))
4513481Sgiacomo.travaglini@arm.comconfig_root = os.path.dirname(config_path)
4613481Sgiacomo.travaglini@arm.comm5_root = os.path.dirname(config_root)
4713481Sgiacomo.travaglini@arm.com
4813481Sgiacomo.travaglini@arm.comparser = optparse.OptionParser()
4913481Sgiacomo.travaglini@arm.comOptions.addCommonOptions(parser)
5013481Sgiacomo.travaglini@arm.com
5113481Sgiacomo.travaglini@arm.comparser.add_option("-l", "--requests", metavar="N", default=100,
5213481Sgiacomo.travaglini@arm.com                  help="Stop after N requests")
5313481Sgiacomo.travaglini@arm.comparser.add_option("-f", "--wakeup_freq", metavar="N", default=10,
5413481Sgiacomo.travaglini@arm.com                  help="Wakeup every N cycles")
5513481Sgiacomo.travaglini@arm.comparser.add_option("--test-type", type="choice", default="SeriesGetx",
5613481Sgiacomo.travaglini@arm.com                  choices = ["SeriesGetx", "SeriesGets", "SeriesGetMixed",
5713481Sgiacomo.travaglini@arm.com                             "Invalidate"],
5813481Sgiacomo.travaglini@arm.com                  help = "Type of test")
5913481Sgiacomo.travaglini@arm.comparser.add_option("--percent-writes", type="int", default=100,
6013481Sgiacomo.travaglini@arm.com                  help="percentage of accesses that should be writes")
6113481Sgiacomo.travaglini@arm.com
6213481Sgiacomo.travaglini@arm.com#
6313481Sgiacomo.travaglini@arm.com# Add the ruby specific and protocol specific options
6413481Sgiacomo.travaglini@arm.com#
6513481Sgiacomo.travaglini@arm.comRuby.define_options(parser)
6613481Sgiacomo.travaglini@arm.com(options, args) = parser.parse_args()
6713481Sgiacomo.travaglini@arm.com
6813481Sgiacomo.travaglini@arm.comif args:
6913481Sgiacomo.travaglini@arm.com     print "Error: script doesn't take any positional arguments"
7013481Sgiacomo.travaglini@arm.com     sys.exit(1)
7113481Sgiacomo.travaglini@arm.com
7213481Sgiacomo.travaglini@arm.com#
7313481Sgiacomo.travaglini@arm.com# Select the direct test generator
7413481Sgiacomo.travaglini@arm.com#
7513481Sgiacomo.travaglini@arm.comif options.test_type == "SeriesGetx":
7613481Sgiacomo.travaglini@arm.com    generator = SeriesRequestGenerator(num_cpus = options.num_cpus,
7713481Sgiacomo.travaglini@arm.com                                       percent_writes = 100)
7813481Sgiacomo.travaglini@arm.comelif options.test_type == "SeriesGets":
7913481Sgiacomo.travaglini@arm.com    generator = SeriesRequestGenerator(num_cpus = options.num_cpus,
8013481Sgiacomo.travaglini@arm.com                                       percent_writes = 0)
8113481Sgiacomo.travaglini@arm.comelif options.test_type == "SeriesGetMixed":
8213481Sgiacomo.travaglini@arm.com    generator = SeriesRequestGenerator(num_cpus = options.num_cpus,
8313481Sgiacomo.travaglini@arm.com                                       percent_writes = options.percent_writes)
8413481Sgiacomo.travaglini@arm.comelif options.test_type == "Invalidate":
8513481Sgiacomo.travaglini@arm.com    generator = InvalidateGenerator(num_cpus = options.num_cpus)
8613481Sgiacomo.travaglini@arm.comelse:
8713481Sgiacomo.travaglini@arm.com    print "Error: unknown direct test generator"
8813481Sgiacomo.travaglini@arm.com    sys.exit(1)
8913481Sgiacomo.travaglini@arm.com
9013481Sgiacomo.travaglini@arm.com#
9113481Sgiacomo.travaglini@arm.com# Create the M5 system.  Note that the Memory Object isn't
9213481Sgiacomo.travaglini@arm.com# actually used by the rubytester, but is included to support the
9313481Sgiacomo.travaglini@arm.com# M5 memory size == Ruby memory size checks
9413481Sgiacomo.travaglini@arm.com#
9513481Sgiacomo.travaglini@arm.comsystem = System(physmem = SimpleMemory(),
9613481Sgiacomo.travaglini@arm.com                mem_ranges = [AddrRange(options.mem_size)])
9713481Sgiacomo.travaglini@arm.com
9813481Sgiacomo.travaglini@arm.com
9913481Sgiacomo.travaglini@arm.com# Create a top-level voltage domain and clock domain
10013481Sgiacomo.travaglini@arm.comsystem.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
10113481Sgiacomo.travaglini@arm.com
10213481Sgiacomo.travaglini@arm.comsystem.clk_domain = SrcClockDomain(clock = options.sys_clock,
10313481Sgiacomo.travaglini@arm.com                                   voltage_domain = system.voltage_domain)
10413481Sgiacomo.travaglini@arm.com
10513481Sgiacomo.travaglini@arm.com#
10613481Sgiacomo.travaglini@arm.com# Create the ruby random tester
10713481Sgiacomo.travaglini@arm.com#
10813481Sgiacomo.travaglini@arm.comsystem.tester = RubyDirectedTester(requests_to_complete = \
10913481Sgiacomo.travaglini@arm.com                                   options.requests,
11013481Sgiacomo.travaglini@arm.com                                   generator = generator)
11113481Sgiacomo.travaglini@arm.com
11213481Sgiacomo.travaglini@arm.comRuby.create_system(options, system)
11313481Sgiacomo.travaglini@arm.com
11413481Sgiacomo.travaglini@arm.com# Since Ruby runs at an independent frequency, create a seperate clock
11513481Sgiacomo.travaglini@arm.comsystem.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
11613481Sgiacomo.travaglini@arm.com                                        voltage_domain = system.voltage_domain)
11713481Sgiacomo.travaglini@arm.com
11813481Sgiacomo.travaglini@arm.comassert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
11913481Sgiacomo.travaglini@arm.com
12013481Sgiacomo.travaglini@arm.comfor ruby_port in system.ruby._cpu_ruby_ports:
12113481Sgiacomo.travaglini@arm.com    #
12213481Sgiacomo.travaglini@arm.com    # Tie the ruby tester ports to the ruby cpu ports
12313481Sgiacomo.travaglini@arm.com    #
12413481Sgiacomo.travaglini@arm.com    system.tester.cpuPort = ruby_port.slave
12513481Sgiacomo.travaglini@arm.com
12613481Sgiacomo.travaglini@arm.com# -----------------------
12713481Sgiacomo.travaglini@arm.com# run simulation
12813481Sgiacomo.travaglini@arm.com# -----------------------
12913481Sgiacomo.travaglini@arm.com
13013481Sgiacomo.travaglini@arm.comroot = Root( full_system = False, system = system )
13113481Sgiacomo.travaglini@arm.comroot.system.mem_mode = 'timing'
13213481Sgiacomo.travaglini@arm.com
13313481Sgiacomo.travaglini@arm.com# Not much point in this being higher than the L1 latency
13413481Sgiacomo.travaglini@arm.comm5.ticks.setGlobalFrequency('1ns')
13513481Sgiacomo.travaglini@arm.com
13613481Sgiacomo.travaglini@arm.com# instantiate configuration
13713481Sgiacomo.travaglini@arm.comm5.instantiate()
13813481Sgiacomo.travaglini@arm.com
13913481Sgiacomo.travaglini@arm.com# simulate until program terminates
14013481Sgiacomo.travaglini@arm.comexit_event = m5.simulate(options.abs_max_tick)
14113481Sgiacomo.travaglini@arm.com
14213481Sgiacomo.travaglini@arm.comprint 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
14313481Sgiacomo.travaglini@arm.com