memcheck.py revision 11837 
1# Copyright (c) 2015-2016 ARM Limited
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38#
39# Authors: Ron Dreslinski
40#          Andreas Hansson
41
42import optparse
43import random
44import sys
45
46import m5
47from m5.objects import *
48
49parser = optparse.OptionParser()
50
51parser.add_option("-a", "--atomic", action="store_true",
52                  help="Use atomic (non-timing) mode")
53parser.add_option("-b", "--blocking", action="store_true",
54                  help="Use blocking caches")
55parser.add_option("-m", "--maxtick", type="int", default=m5.MaxTick,
56                  metavar="T",
57                  help="Stop after T ticks")
58parser.add_option("-p", "--prefetchers", action="store_true",
59                  help="Use prefetchers")
60parser.add_option("-s", "--stridepref", action="store_true",
61                  help="Use strided prefetchers")
62
63# This example script has a lot in common with the memtest.py in that
64# it is designed to stress tests the memory system. However, this
65# script uses oblivious traffic generators to create the stimuli, and
66# couples them with memcheckers to verify that the data read matches
67# the allowed outcomes. Just like memtest.py, the traffic generators
68# and checkers are placed in a tree topology. At the bottom of the
69# tree is a shared memory, and then at each level a number of
70# generators and checkers are attached, along with a number of caches
71# that them selves fan out to subtrees of generators and caches. Thus,
72# it is possible to create a system with arbitrarily deep cache
73# hierarchies, sharing or no sharing of caches, and generators not
74# only at the L1s, but also at the L2s, L3s etc.
75#
76# The tree specification consists of two colon-separated lists of one
77# or more integers, one for the caches, and one for the
78# testers/generators. The first integer is the number of
79# caches/testers closest to main memory. Each cache then fans out to a
80# subtree. The last integer in the list is the number of
81# caches/testers associated with the uppermost level of memory. The
82# other integers (if any) specify the number of caches/testers
83# connected at each level of the crossbar hierarchy. The tester string
84# should have one element more than the cache string as there should
85# always be testers attached to the uppermost caches.
86#
87# Since this script tests actual sharing, there is also a possibility
88# to stress prefetching and the interaction between prefetchers and
89# caches. The traffic generators switch between random address streams
90# and linear address streams to ensure that the prefetchers will
91# trigger. By default prefetchers are off.
92
93parser.add_option("-c", "--caches", type="string", default="3:2",
94                  help="Colon-separated cache hierarchy specification, "
95                  "see script comments for details "
96                  "[default: %default]")
97parser.add_option("-t", "--testers", type="string", default="1:0:2",
98                  help="Colon-separated tester hierarchy specification, "
99                  "see script comments for details "
100                  "[default: %default]")
101parser.add_option("-r", "--random", action="store_true",
102                  help="Generate a random tree topology")
103parser.add_option("--sys-clock", action="store", type="string",
104                  default='1GHz',
105                  help = """Top-level clock for blocks running at system
106                  speed""")
107
108(options, args) = parser.parse_args()
109
110if args:
111     print "Error: script doesn't take any positional arguments"
112     sys.exit(1)
113
114# Start by parsing the command line options and do some basic sanity
115# checking
116if options.random:
117     # Generate a tree with a valid number of testers
118     tree_depth = random.randint(1, 4)
119     cachespec = [random.randint(1, 3) for i in range(tree_depth)]
120     testerspec = [random.randint(1, 3) for i in range(tree_depth + 1)]
121     print "Generated random tree -c", ':'.join(map(str, cachespec)), \
122         "-t", ':'.join(map(str, testerspec))
123else:
124     try:
125          cachespec = [int(x) for x in options.caches.split(':')]
126          testerspec = [int(x) for x in options.testers.split(':')]
127     except:
128          print "Error: Unable to parse caches or testers option"
129          sys.exit(1)
130
131     if len(cachespec) < 1:
132          print "Error: Must have at least one level of caches"
133          sys.exit(1)
134
135     if len(cachespec) != len(testerspec) - 1:
136          print "Error: Testers must have one element more than caches"
137          sys.exit(1)
138
139     if testerspec[-1] == 0:
140          print "Error: Must have testers at the uppermost level"
141          sys.exit(1)
142
143     for t in testerspec:
144          if t < 0:
145               print "Error: Cannot have a negative number of testers"
146               sys.exit(1)
147
148     for c in cachespec:
149          if c < 1:
150               print "Error: Must have 1 or more caches at each level"
151               sys.exit(1)
152
153# Determine the tester multiplier for each level as the string
154# elements are per subsystem and it fans out
155multiplier = [1]
156for c in cachespec:
157     if c < 1:
158          print "Error: Must have at least one cache per level"
159     multiplier.append(multiplier[-1] * c)
160
161numtesters = 0
162for t, m in zip(testerspec, multiplier):
163     numtesters += t * m
164
165# Define a prototype L1 cache that we scale for all successive levels
166proto_l1 = Cache(size = '32kB', assoc = 4,
167                 tag_latency = 1, data_latency = 1, response_latency = 1,
168                 tgts_per_mshr = 8)
169
170if options.blocking:
171     proto_l1.mshrs = 1
172else:
173     proto_l1.mshrs = 4
174
175if options.prefetchers:
176     proto_l1.prefetcher = TaggedPrefetcher()
177elif options.stridepref:
178     proto_l1.prefetcher = StridePrefetcher()
179
180cache_proto = [proto_l1]
181
182# Now add additional cache levels (if any) by scaling L1 params, the
183# first element is Ln, and the last element L1
184for scale in cachespec[:-1]:
185     # Clone previous level and update params
186     prev = cache_proto[0]
187     next = prev()
188     next.size = prev.size * scale
189     next.tag_latency = prev.tag_latency * 10
190     next.data_latency = prev.data_latency * 10
191     next.response_latency = prev.response_latency * 10
192     next.assoc = prev.assoc * scale
193     next.mshrs = prev.mshrs * scale
194     cache_proto.insert(0, next)
195
196# Create a config to be used by all the traffic generators
197cfg_file_name = "configs/example/memcheck.cfg"
198cfg_file = open(cfg_file_name, 'w')
199
200# Three states, with random, linear and idle behaviours. The random
201# and linear states access memory in the range [0 : 16 Mbyte] with 8
202# byte and 64 byte accesses respectively.
203cfg_file.write("STATE 0 10000000 RANDOM 65 0 16777216 8 50000 150000 0\n")
204cfg_file.write("STATE 1 10000000 LINEAR 65 0 16777216 64 50000 150000 0\n")
205cfg_file.write("STATE 2 10000000 IDLE\n")
206cfg_file.write("INIT 0\n")
207cfg_file.write("TRANSITION 0 1 0.5\n")
208cfg_file.write("TRANSITION 0 2 0.5\n")
209cfg_file.write("TRANSITION 1 0 0.5\n")
210cfg_file.write("TRANSITION 1 2 0.5\n")
211cfg_file.write("TRANSITION 2 0 0.5\n")
212cfg_file.write("TRANSITION 2 1 0.5\n")
213cfg_file.close()
214
215# Make a prototype for the tester to be used throughout
216proto_tester = TrafficGen(config_file = cfg_file_name)
217
218# Set up the system along with a DRAM controller
219system = System(physmem = DDR3_1600_8x8())
220
221system.voltage_domain = VoltageDomain(voltage = '1V')
222
223system.clk_domain = SrcClockDomain(clock =  options.sys_clock,
224                        voltage_domain = system.voltage_domain)
225
226system.memchecker = MemChecker()
227
228# For each level, track the next subsys index to use
229next_subsys_index = [0] * (len(cachespec) + 1)
230
231# Recursive function to create a sub-tree of the cache and tester
232# hierarchy
233def make_cache_level(ncaches, prototypes, level, next_cache):
234     global next_subsys_index, proto_l1, testerspec, proto_tester
235
236     index = next_subsys_index[level]
237     next_subsys_index[level] += 1
238
239     # Create a subsystem to contain the crossbar and caches, and
240     # any testers
241     subsys = SubSystem()
242     setattr(system, 'l%dsubsys%d' % (level, index), subsys)
243
244     # The levels are indexing backwards through the list
245     ntesters = testerspec[len(cachespec) - level]
246
247     testers = [proto_tester() for i in xrange(ntesters)]
248     checkers = [MemCheckerMonitor(memchecker = system.memchecker) \
249                      for i in xrange(ntesters)]
250     if ntesters:
251          subsys.tester = testers
252          subsys.checkers = checkers
253
254     if level != 0:
255          # Create a crossbar and add it to the subsystem, note that
256          # we do this even with a single element on this level
257          xbar = L2XBar(width = 32)
258          subsys.xbar = xbar
259          if next_cache:
260               xbar.master = next_cache.cpu_side
261
262          # Create and connect the caches, both the ones fanning out
263          # to create the tree, and the ones used to connect testers
264          # on this level
265          tree_caches = [prototypes[0]() for i in xrange(ncaches[0])]
266          tester_caches = [proto_l1() for i in xrange(ntesters)]
267
268          subsys.cache = tester_caches + tree_caches
269          for cache in tree_caches:
270               cache.mem_side = xbar.slave
271               make_cache_level(ncaches[1:], prototypes[1:], level - 1, cache)
272          for tester, checker, cache in zip(testers, checkers, tester_caches):
273               tester.port = checker.slave
274               checker.master = cache.cpu_side
275               cache.mem_side = xbar.slave
276     else:
277          if not next_cache:
278               print "Error: No next-level cache at top level"
279               sys.exit(1)
280
281          if ntesters > 1:
282               # Create a crossbar and add it to the subsystem
283               xbar = L2XBar(width = 32)
284               subsys.xbar = xbar
285               xbar.master = next_cache.cpu_side
286               for tester, checker in zip(testers, checkers):
287                    tester.port = checker.slave
288                    checker.master = xbar.slave
289          else:
290               # Single tester
291               testers[0].port = checkers[0].slave
292               checkers[0].master = next_cache.cpu_side
293
294# Top level call to create the cache hierarchy, bottom up
295make_cache_level(cachespec, cache_proto, len(cachespec), None)
296
297# Connect the lowest level crossbar to the memory
298last_subsys = getattr(system, 'l%dsubsys0' % len(cachespec))
299last_subsys.xbar.master = system.physmem.port
300last_subsys.xbar.point_of_coherency = True
301
302root = Root(full_system = False, system = system)
303if options.atomic:
304    root.system.mem_mode = 'atomic'
305else:
306    root.system.mem_mode = 'timing'
307
308# The system port is never used in the tester so merely connect it
309# to avoid problems
310root.system.system_port = last_subsys.xbar.slave
311
312# Instantiate configuration
313m5.instantiate()
314
315# Simulate until program terminates
316exit_event = m5.simulate(options.maxtick)
317
318print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
319