etrace_replay.py revision 11251:a15c86af004a 
1# Copyright (c) 2015 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder.  You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Redistribution and use in source and binary forms, with or without
14# modification, are permitted provided that the following conditions are
15# met: redistributions of source code must retain the above copyright
16# notice, this list of conditions and the following disclaimer;
17# redistributions in binary form must reproduce the above copyright
18# notice, this list of conditions and the following disclaimer in the
19# documentation and/or other materials provided with the distribution;
20# neither the name of the copyright holders nor the names of its
21# contributors may be used to endorse or promote products derived from
22# this software without specific prior written permission.
23#
24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35#
36# Authors: Radhika Jagtap
37
38# Basic elastic traces replay script that configures a Trace CPU
39
40import optparse
41
42from m5.util import addToPath, fatal
43
44addToPath('../common')
45
46import Options
47import Simulation
48import CacheConfig
49import MemConfig
50from Caches import *
51
52parser = optparse.OptionParser()
53Options.addCommonOptions(parser)
54
55if '--ruby' in sys.argv:
56    print "This script does not support Ruby configuration, mainly"\
57    " because Trace CPU has been tested only with classic memory system"
58    sys.exit(1)
59
60(options, args) = parser.parse_args()
61
62if args:
63    print "Error: script doesn't take any positional arguments"
64    sys.exit(1)
65
66numThreads = 1
67
68if options.cpu_type != "trace":
69    fatal("This is a script for elastic trace replay simulation, use "\
70            "--cpu-type=trace\n");
71
72if options.num_cpus > 1:
73    fatal("This script does not support multi-processor trace replay.\n")
74
75# In this case FutureClass will be None as there is not fast forwarding or
76# switching
77(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
78CPUClass.numThreads = numThreads
79
80system = System(cpu = CPUClass(cpu_id=0),
81                mem_mode = test_mem_mode,
82                mem_ranges = [AddrRange(options.mem_size)],
83                cache_line_size = options.cacheline_size)
84
85# Create a top-level voltage domain
86system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
87
88# Create a source clock for the system. This is used as the clock period for
89# xbar and memory
90system.clk_domain = SrcClockDomain(clock =  options.sys_clock,
91                                   voltage_domain = system.voltage_domain)
92
93# Create a CPU voltage domain
94system.cpu_voltage_domain = VoltageDomain()
95
96# Create a separate clock domain for the CPUs. In case of Trace CPUs this clock
97# is actually used only by the caches connected to the CPU.
98system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
99                                       voltage_domain =
100                                       system.cpu_voltage_domain)
101
102# All cpus belong to a common cpu_clk_domain, therefore running at a common
103# frequency.
104for cpu in system.cpu:
105    cpu.clk_domain = system.cpu_clk_domain
106
107# Assign input trace files to the Trace CPU
108system.cpu.instTraceFile=options.inst_trace_file
109system.cpu.dataTraceFile=options.data_trace_file
110
111# Configure the classic memory system options
112MemClass = Simulation.setMemClass(options)
113system.membus = SystemXBar()
114system.system_port = system.membus.slave
115CacheConfig.config_cache(options, system)
116MemConfig.config_mem(options, system)
117
118root = Root(full_system = False, system = system)
119Simulation.run(options, root, system, FutureClass)
120