etrace_replay.py revision 12430
12686Sksewell@umich.edu# Copyright (c) 2015 ARM Limited 22100SN/A# All rights reserved. 32022SN/A# 42022SN/A# The license below extends only to copyright in the software and shall 52043SN/A# not be construed as granting a license to any other intellectual 62024SN/A# property including but not limited to intellectual property relating 72024SN/A# to a hardware implementation of the functionality of the software 82043SN/A# licensed hereunder. You may use the software subject to the license 92686Sksewell@umich.edu# terms below provided that you ensure that this notice is replicated 102024SN/A# unmodified and in its entirety in all distributions of the software, 112022SN/A# modified or unmodified, in source code or in binary form. 122083SN/A# 132686Sksewell@umich.edu# Redistribution and use in source and binary forms, with or without 142101SN/A# modification, are permitted provided that the following conditions are 152043SN/A# met: redistributions of source code must retain the above copyright 162043SN/A# notice, this list of conditions and the following disclaimer; 172101SN/A# redistributions in binary form must reproduce the above copyright 182101SN/A# notice, this list of conditions and the following disclaimer in the 192686Sksewell@umich.edu# documentation and/or other materials provided with the distribution; 202686Sksewell@umich.edu# neither the name of the copyright holders nor the names of its 212101SN/A# contributors may be used to endorse or promote products derived from 222101SN/A# this software without specific prior written permission. 232101SN/A# 242046SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 252686Sksewell@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 262686Sksewell@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 272686Sksewell@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 282470SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 292686Sksewell@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 302686Sksewell@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 312686Sksewell@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 322686Sksewell@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 332686Sksewell@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 342686Sksewell@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 352470SN/A# 362241SN/A# Authors: Radhika Jagtap 372101SN/A 382495SN/A# Basic elastic traces replay script that configures a Trace CPU 392495SN/A 402495SN/Aimport optparse 412101SN/A 422495SN/Afrom m5.util import addToPath, fatal 432495SN/A 442495SN/AaddToPath('../') 452101SN/A 462101SN/Afrom common import Options 472495SN/Afrom common import Simulation 482495SN/Afrom common import CacheConfig 492495SN/Afrom common import MemConfig 502495SN/Afrom common.Caches import * 512495SN/A 522495SN/Aparser = optparse.OptionParser() 532495SN/AOptions.addCommonOptions(parser) 542495SN/A 552495SN/Aif '--ruby' in sys.argv: 562495SN/A print "This script does not support Ruby configuration, mainly"\ 572495SN/A " because Trace CPU has been tested only with classic memory system" 582495SN/A sys.exit(1) 592495SN/A 602101SN/A(options, args) = parser.parse_args() 612101SN/A 622101SN/Aif args: 632101SN/A print "Error: script doesn't take any positional arguments" 642101SN/A sys.exit(1) 652101SN/A 662101SN/AnumThreads = 1 672101SN/A 682101SN/Aif options.cpu_type != "TraceCPU": 692101SN/A fatal("This is a script for elastic trace replay simulation, use "\ 702495SN/A "--cpu-type=TraceCPU\n"); 712495SN/A 722495SN/Aif options.num_cpus > 1: 732495SN/A fatal("This script does not support multi-processor trace replay.\n") 742495SN/A 752495SN/A# In this case FutureClass will be None as there is not fast forwarding or 762495SN/A# switching 772495SN/A(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 782495SN/ACPUClass.numThreads = numThreads 792495SN/A 802495SN/Asystem = System(cpu = CPUClass(cpu_id=0), 812495SN/A mem_mode = test_mem_mode, 822495SN/A mem_ranges = [AddrRange(options.mem_size)], 832495SN/A cache_line_size = options.cacheline_size) 842495SN/A 852043SN/A# Create a top-level voltage domain 862043SN/Asystem.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 872025SN/A 882043SN/A# Create a source clock for the system. This is used as the clock period for 892686Sksewell@umich.edu# xbar and memory 902686Sksewell@umich.edusystem.clk_domain = SrcClockDomain(clock = options.sys_clock, 912123SN/A voltage_domain = system.voltage_domain) 922101SN/A 932686Sksewell@umich.edu# Create a CPU voltage domain 942686Sksewell@umich.edusystem.cpu_voltage_domain = VoltageDomain() 952101SN/A 962042SN/A# Create a separate clock domain for the CPUs. In case of Trace CPUs this clock 972101SN/A# is actually used only by the caches connected to the CPU. 982686Sksewell@umich.edusystem.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 992686Sksewell@umich.edu voltage_domain = 1002686Sksewell@umich.edu system.cpu_voltage_domain) 1012686Sksewell@umich.edu 1022101SN/A# All cpus belong to a common cpu_clk_domain, therefore running at a common 1032101SN/A# frequency. 1042042SN/Afor cpu in system.cpu: 1052101SN/A cpu.clk_domain = system.cpu_clk_domain 1062686Sksewell@umich.edu 1072686Sksewell@umich.edu# BaseCPU no longer has default values for the BaseCPU.isa 1082686Sksewell@umich.edu# createThreads() is needed to fill in the cpu.isa 1092686Sksewell@umich.edufor cpu in system.cpu: 1102101SN/A cpu.createThreads() 1112083SN/A 1122686Sksewell@umich.edu# Assign input trace files to the Trace CPU 1132686Sksewell@umich.edusystem.cpu.instTraceFile=options.inst_trace_file 1142101SN/Asystem.cpu.dataTraceFile=options.data_trace_file 1152043SN/A 1162025SN/A# Configure the classic memory system options 1172043SN/AMemClass = Simulation.setMemClass(options) 1182686Sksewell@umich.edusystem.membus = SystemXBar() 1192616SN/Asystem.system_port = system.membus.slave 1202616SN/ACacheConfig.config_cache(options, system) 1212616SN/AMemConfig.config_mem(options, system) 1222616SN/A 1232101SN/Aroot = Root(full_system = False, system = system) 1242083SN/ASimulation.run(options, root, system, FutureClass) 1252025SN/A