sweep.py revision 10392:0100f00a229e
110259SAndrew.Bardsley@arm.com# Copyright (c) 2014 ARM Limited 210259SAndrew.Bardsley@arm.com# All rights reserved. 310259SAndrew.Bardsley@arm.com# 410259SAndrew.Bardsley@arm.com# The license below extends only to copyright in the software and shall 510259SAndrew.Bardsley@arm.com# not be construed as granting a license to any other intellectual 610259SAndrew.Bardsley@arm.com# property including but not limited to intellectual property relating 710259SAndrew.Bardsley@arm.com# to a hardware implementation of the functionality of the software 810259SAndrew.Bardsley@arm.com# licensed hereunder. You may use the software subject to the license 910259SAndrew.Bardsley@arm.com# terms below provided that you ensure that this notice is replicated 1010259SAndrew.Bardsley@arm.com# unmodified and in its entirety in all distributions of the software, 1110259SAndrew.Bardsley@arm.com# modified or unmodified, in source code or in binary form. 1210259SAndrew.Bardsley@arm.com# 1310259SAndrew.Bardsley@arm.com# Redistribution and use in source and binary forms, with or without 1410259SAndrew.Bardsley@arm.com# modification, are permitted provided that the following conditions are 1510259SAndrew.Bardsley@arm.com# met: redistributions of source code must retain the above copyright 1610259SAndrew.Bardsley@arm.com# notice, this list of conditions and the following disclaimer; 1710259SAndrew.Bardsley@arm.com# redistributions in binary form must reproduce the above copyright 1810259SAndrew.Bardsley@arm.com# notice, this list of conditions and the following disclaimer in the 1910259SAndrew.Bardsley@arm.com# documentation and/or other materials provided with the distribution; 2010259SAndrew.Bardsley@arm.com# neither the name of the copyright holders nor the names of its 2110259SAndrew.Bardsley@arm.com# contributors may be used to endorse or promote products derived from 2210259SAndrew.Bardsley@arm.com# this software without specific prior written permission. 2310259SAndrew.Bardsley@arm.com# 2410259SAndrew.Bardsley@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2510259SAndrew.Bardsley@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2610259SAndrew.Bardsley@arm.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2710259SAndrew.Bardsley@arm.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2810259SAndrew.Bardsley@arm.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2910259SAndrew.Bardsley@arm.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3010259SAndrew.Bardsley@arm.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3110259SAndrew.Bardsley@arm.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3210259SAndrew.Bardsley@arm.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3310259SAndrew.Bardsley@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3410259SAndrew.Bardsley@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3510259SAndrew.Bardsley@arm.com# 3610259SAndrew.Bardsley@arm.com# Authors: Andreas Hansson 3710259SAndrew.Bardsley@arm.com 3810259SAndrew.Bardsley@arm.comimport optparse 3910259SAndrew.Bardsley@arm.com 4010259SAndrew.Bardsley@arm.comimport m5 4110259SAndrew.Bardsley@arm.comfrom m5.objects import * 4210259SAndrew.Bardsley@arm.comfrom m5.util import addToPath 4310259SAndrew.Bardsley@arm.comfrom m5.internal.stats import periodicStatDump 4410259SAndrew.Bardsley@arm.com 4510259SAndrew.Bardsley@arm.comaddToPath('../common') 4610259SAndrew.Bardsley@arm.com 4710259SAndrew.Bardsley@arm.comimport MemConfig 4810259SAndrew.Bardsley@arm.com 4910259SAndrew.Bardsley@arm.com# this script is helpful to sweep the efficiency of a specific memory 5010259SAndrew.Bardsley@arm.com# controller configuration, by varying the number of banks accessed, 5110259SAndrew.Bardsley@arm.com# and the sequential stride size (how many bytes per activate), and 5210259SAndrew.Bardsley@arm.com# observe what bus utilisation (bandwidth) is achieved 5310259SAndrew.Bardsley@arm.com 5410259SAndrew.Bardsley@arm.comparser = optparse.OptionParser() 5510259SAndrew.Bardsley@arm.com 5610259SAndrew.Bardsley@arm.com# Use a single-channel DDR3-1600 x64 by default 5710259SAndrew.Bardsley@arm.comparser.add_option("--mem-type", type="choice", default="ddr3_1600_x64", 5810259SAndrew.Bardsley@arm.com choices=MemConfig.mem_names(), 5910259SAndrew.Bardsley@arm.com help = "type of memory to use") 6010259SAndrew.Bardsley@arm.com 6110259SAndrew.Bardsley@arm.comparser.add_option("--ranks", "-r", type="int", default=1, 6210259SAndrew.Bardsley@arm.com help = "Number of ranks to iterate across") 6310259SAndrew.Bardsley@arm.com 6410259SAndrew.Bardsley@arm.comparser.add_option("--rd_perc", type="int", default=100, 6510259SAndrew.Bardsley@arm.com help = "Percentage of read commands") 6610259SAndrew.Bardsley@arm.com 6710259SAndrew.Bardsley@arm.comparser.add_option("--mode", type="choice", default="DRAM", 6810259SAndrew.Bardsley@arm.com choices=["DRAM", "DRAM_ROTATE"], 6910259SAndrew.Bardsley@arm.com help = "DRAM: Random traffic; \ 7010259SAndrew.Bardsley@arm.com DRAM_ROTATE: Traffic rotating across banks and ranks") 7110259SAndrew.Bardsley@arm.com 7210259SAndrew.Bardsley@arm.comparser.add_option("--addr_map", type="int", default=1, 7310259SAndrew.Bardsley@arm.com help = "0: RoCoRaBaCh; 1: RoRaBaCoCh/RoRaBaChCo") 7410259SAndrew.Bardsley@arm.com 7510259SAndrew.Bardsley@arm.com(options, args) = parser.parse_args() 7610259SAndrew.Bardsley@arm.com 7710259SAndrew.Bardsley@arm.comif args: 7810259SAndrew.Bardsley@arm.com print "Error: script doesn't take any positional arguments" 7910259SAndrew.Bardsley@arm.com sys.exit(1) 8010259SAndrew.Bardsley@arm.com 8110259SAndrew.Bardsley@arm.com# at the moment we stay with the default open-adaptive page policy, 8210259SAndrew.Bardsley@arm.com# and address mapping 8310259SAndrew.Bardsley@arm.com 8410259SAndrew.Bardsley@arm.com# start with the system itself, using a multi-layer 1.5 GHz 8510259SAndrew.Bardsley@arm.com# bus/crossbar, delivering 64 bytes / 5 cycles (one header cycle) 8610259SAndrew.Bardsley@arm.com# which amounts to 19.2 GByte/s per layer and thus per port 8710259SAndrew.Bardsley@arm.comsystem = System(membus = NoncoherentBus(width = 16)) 8810259SAndrew.Bardsley@arm.comsystem.clk_domain = SrcClockDomain(clock = '1.5GHz', 8910259SAndrew.Bardsley@arm.com voltage_domain = 9010259SAndrew.Bardsley@arm.com VoltageDomain(voltage = '1V')) 9110259SAndrew.Bardsley@arm.com 9210259SAndrew.Bardsley@arm.com# we are fine with 256 MB memory for now 9310259SAndrew.Bardsley@arm.commem_range = AddrRange('256MB') 9410259SAndrew.Bardsley@arm.comsystem.mem_ranges = [mem_range] 9510259SAndrew.Bardsley@arm.com 9610259SAndrew.Bardsley@arm.com# force a single channel to match the assumptions in the DRAM traffic 9710259SAndrew.Bardsley@arm.com# generator 9810259SAndrew.Bardsley@arm.comoptions.mem_channels = 1 9910259SAndrew.Bardsley@arm.comMemConfig.config_mem(options, system) 10010259SAndrew.Bardsley@arm.com 10110259SAndrew.Bardsley@arm.com# the following assumes that we are using the native DRAM 10210259SAndrew.Bardsley@arm.com# controller, check to be sure 10310259SAndrew.Bardsley@arm.comif not isinstance(system.mem_ctrls[0], m5.objects.DRAMCtrl): 10410259SAndrew.Bardsley@arm.com fatal("This script assumes the memory is a DRAMCtrl subclass") 10510259SAndrew.Bardsley@arm.com 10610259SAndrew.Bardsley@arm.com# Set number of ranks based on input argument; default is 1 rank 10710259SAndrew.Bardsley@arm.comsystem.mem_ctrls[0].ranks_per_channel = options.ranks 10810259SAndrew.Bardsley@arm.com 10910259SAndrew.Bardsley@arm.com# Set the address mapping based on input argument 11010259SAndrew.Bardsley@arm.com# Default to RoRaBaCoCh 11110259SAndrew.Bardsley@arm.comif options.addr_map == 0: 11210259SAndrew.Bardsley@arm.com system.mem_ctrls[0].addr_mapping = "RoCoRaBaCh" 11310259SAndrew.Bardsley@arm.comelif options.addr_map == 1: 11410259SAndrew.Bardsley@arm.com system.mem_ctrls[0].addr_mapping = "RoRaBaCoCh" 11510259SAndrew.Bardsley@arm.comelse: 11610259SAndrew.Bardsley@arm.com fatal("Did not specify a valid address map argument") 11710259SAndrew.Bardsley@arm.com 11810259SAndrew.Bardsley@arm.com# stay in each state for 0.25 ms, long enough to warm things up, and 11910259SAndrew.Bardsley@arm.com# short enough to avoid hitting a refresh 12010259SAndrew.Bardsley@arm.comperiod = 250000000 12110259SAndrew.Bardsley@arm.com 12210259SAndrew.Bardsley@arm.com# this is where we go off piste, and print the traffic generator 12310259SAndrew.Bardsley@arm.com# configuration that we will later use, crazy but it works 12410259SAndrew.Bardsley@arm.comcfg_file_name = "configs/dram/sweep.cfg" 12510259SAndrew.Bardsley@arm.comcfg_file = open(cfg_file_name, 'w') 12610259SAndrew.Bardsley@arm.com 12710259SAndrew.Bardsley@arm.com# stay in each state as long as the dump/reset period, use the entire 12810259SAndrew.Bardsley@arm.com# range, issue transactions of the right DRAM burst size, and match 12910259SAndrew.Bardsley@arm.com# the DRAM maximum bandwidth to ensure that it is saturated 13010259SAndrew.Bardsley@arm.com 13110259SAndrew.Bardsley@arm.com# get the number of banks 13210259SAndrew.Bardsley@arm.comnbr_banks = system.mem_ctrls[0].banks_per_rank.value 13310259SAndrew.Bardsley@arm.com 13410259SAndrew.Bardsley@arm.com# determine the burst length in bytes 13510259SAndrew.Bardsley@arm.comburst_size = int((system.mem_ctrls[0].devices_per_rank.value * 13610259SAndrew.Bardsley@arm.com system.mem_ctrls[0].device_bus_width.value * 13710259SAndrew.Bardsley@arm.com system.mem_ctrls[0].burst_length.value) / 8) 13810259SAndrew.Bardsley@arm.com 13910259SAndrew.Bardsley@arm.com# next, get the page size in bytes 14010259SAndrew.Bardsley@arm.compage_size = system.mem_ctrls[0].devices_per_rank.value * \ 14110259SAndrew.Bardsley@arm.com system.mem_ctrls[0].device_rowbuffer_size.value 14210259SAndrew.Bardsley@arm.com 14310259SAndrew.Bardsley@arm.com# match the maximum bandwidth of the memory, the parameter is in ns 14410259SAndrew.Bardsley@arm.com# and we need it in ticks 14510259SAndrew.Bardsley@arm.comitt = system.mem_ctrls[0].tBURST.value * 1000000000000 14610259SAndrew.Bardsley@arm.com 14710259SAndrew.Bardsley@arm.com# assume we start at 0 14810259SAndrew.Bardsley@arm.commax_addr = mem_range.end 14910259SAndrew.Bardsley@arm.com 15010259SAndrew.Bardsley@arm.com# use min of the page size and 512 bytes as that should be more than 15110259SAndrew.Bardsley@arm.com# enough 15210259SAndrew.Bardsley@arm.commax_stride = min(512, page_size) 15310259SAndrew.Bardsley@arm.com 15410259SAndrew.Bardsley@arm.com# now we create the state by iterating over the stride size from burst 15510259SAndrew.Bardsley@arm.com# size to the max stride, and from using only a single bank up to the 15610259SAndrew.Bardsley@arm.com# number of banks available 15710259SAndrew.Bardsley@arm.comnxt_state = 0 15810259SAndrew.Bardsley@arm.comfor bank in range(1, nbr_banks + 1): 15910259SAndrew.Bardsley@arm.com for stride_size in range(burst_size, max_stride + 1, burst_size): 16010259SAndrew.Bardsley@arm.com cfg_file.write("STATE %d %d %s %d 0 %d %d " 16110259SAndrew.Bardsley@arm.com "%d %d %d %d %d %d %d %d %d\n" % 16210259SAndrew.Bardsley@arm.com (nxt_state, period, options.mode, options.rd_perc, 16310259SAndrew.Bardsley@arm.com max_addr, burst_size, itt, itt, 0, stride_size, 16410259SAndrew.Bardsley@arm.com page_size, nbr_banks, bank, options.addr_map, 16510259SAndrew.Bardsley@arm.com options.ranks)) 16610259SAndrew.Bardsley@arm.com nxt_state = nxt_state + 1 16710259SAndrew.Bardsley@arm.com 16810259SAndrew.Bardsley@arm.comcfg_file.write("INIT 0\n") 16910259SAndrew.Bardsley@arm.com 17010259SAndrew.Bardsley@arm.com# go through the states one by one 17110259SAndrew.Bardsley@arm.comfor state in range(1, nxt_state): 17210259SAndrew.Bardsley@arm.com cfg_file.write("TRANSITION %d %d 1\n" % (state - 1, state)) 17310259SAndrew.Bardsley@arm.com 17410259SAndrew.Bardsley@arm.comcfg_file.write("TRANSITION %d %d 1\n" % (nxt_state - 1, nxt_state - 1)) 17510259SAndrew.Bardsley@arm.com 17610259SAndrew.Bardsley@arm.comcfg_file.close() 17710259SAndrew.Bardsley@arm.com 17810259SAndrew.Bardsley@arm.com# create a traffic generator, and point it to the file we just created 17910259SAndrew.Bardsley@arm.comsystem.tgen = TrafficGen(config_file = cfg_file_name) 18010259SAndrew.Bardsley@arm.com 18110259SAndrew.Bardsley@arm.com# add a communication monitor 18210259SAndrew.Bardsley@arm.comsystem.monitor = CommMonitor() 18310259SAndrew.Bardsley@arm.com 18410259SAndrew.Bardsley@arm.com# connect the traffic generator to the bus via a communication monitor 18510259SAndrew.Bardsley@arm.comsystem.tgen.port = system.monitor.slave 18610259SAndrew.Bardsley@arm.comsystem.monitor.master = system.membus.slave 18710259SAndrew.Bardsley@arm.com 18810259SAndrew.Bardsley@arm.com# connect the system port even if it is not used in this example 18910259SAndrew.Bardsley@arm.comsystem.system_port = system.membus.slave 19010259SAndrew.Bardsley@arm.com 19110259SAndrew.Bardsley@arm.com# every period, dump and reset all stats 19210259SAndrew.Bardsley@arm.comperiodicStatDump(period) 19310259SAndrew.Bardsley@arm.com 19410259SAndrew.Bardsley@arm.com# run Forrest, run! 19510259SAndrew.Bardsley@arm.comroot = Root(full_system = False, system = system) 19610259SAndrew.Bardsley@arm.comroot.system.mem_mode = 'timing' 19710259SAndrew.Bardsley@arm.com 19810259SAndrew.Bardsley@arm.comm5.instantiate() 19910259SAndrew.Bardsley@arm.comm5.simulate(nxt_state * period) 20010259SAndrew.Bardsley@arm.com 20110259SAndrew.Bardsley@arm.comprint "DRAM sweep with burst: %d, banks: %d, max stride: %d" % \ 20210259SAndrew.Bardsley@arm.com (burst_size, nbr_banks, max_stride) 20310259SAndrew.Bardsley@arm.com