low_power_sweep.py revision 12564
1# Copyright (c) 2014-2015, 2017 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Redistribution and use in source and binary forms, with or without 14# modification, are permitted provided that the following conditions are 15# met: redistributions of source code must retain the above copyright 16# notice, this list of conditions and the following disclaimer; 17# redistributions in binary form must reproduce the above copyright 18# notice, this list of conditions and the following disclaimer in the 19# documentation and/or other materials provided with the distribution; 20# neither the name of the copyright holders nor the names of its 21# contributors may be used to endorse or promote products derived from 22# this software without specific prior written permission. 23# 24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35# 36# Authors: Radhika Jagtap 37# Andreas Hansson 38 39from __future__ import print_function 40 41import argparse 42 43import m5 44from m5.objects import * 45from m5.util import addToPath 46from m5.stats import periodicStatDump 47 48addToPath(os.getcwd() + '/configs/common') 49import MemConfig 50 51# This script aims at triggering low power state transitions in the DRAM 52# controller. The traffic generator is used in DRAM mode and traffic 53# states target a different levels of bank utilization and strides. 54# At the end after sweeping through bank utilization and strides, we go 55# through an idle state with no requests to enforce self-refresh. 56 57parser = argparse.ArgumentParser( 58 formatter_class=argparse.ArgumentDefaultsHelpFormatter) 59 60# Use a single-channel DDR4-2400 in 16x4 configuration by default 61parser.add_argument("--mem-type", default="DDR4_2400_16x4", 62 choices=MemConfig.mem_names(), 63 help = "type of memory to use") 64 65parser.add_argument("--mem-ranks", "-r", type=int, default=1, 66 help = "Number of ranks to iterate across") 67 68parser.add_argument("--page-policy", "-p", 69 choices=["close_adaptive", "open_adaptive"], 70 default="close_adaptive", help="controller page policy") 71 72parser.add_argument("--itt-list", "-t", default="1 20 100", 73 help="a list of multipliers for the max value of itt, " \ 74 "e.g. \"1 20 100\"") 75 76parser.add_argument("--rd-perc", type=int, default=100, 77 help = "Percentage of read commands") 78 79parser.add_argument("--addr-map", type=int, default=1, 80 help = "0: RoCoRaBaCh; 1: RoRaBaCoCh/RoRaBaChCo") 81 82parser.add_argument("--idle-end", type=int, default=50000000, 83 help = "time in ps of an idle period at the end ") 84 85args = parser.parse_args() 86 87# Start with the system itself, using a multi-layer 2.0 GHz 88# crossbar, delivering 64 bytes / 3 cycles (one header cycle) 89# which amounts to 42.7 GByte/s per layer and thus per port. 90system = System(membus = IOXBar(width = 32)) 91system.clk_domain = SrcClockDomain(clock = '2.0GHz', 92 voltage_domain = 93 VoltageDomain(voltage = '1V')) 94 95# We are fine with 256 MB memory for now. 96mem_range = AddrRange('256MB') 97# Start address is 0 98system.mem_ranges = [mem_range] 99 100# Do not worry about reserving space for the backing store 101system.mmap_using_noreserve = True 102 103# Force a single channel to match the assumptions in the DRAM traffic 104# generator 105args.mem_channels = 1 106args.external_memory_system = 0 107args.tlm_memory = 0 108args.elastic_trace_en = 0 109MemConfig.config_mem(args, system) 110 111# Sanity check for memory controller class. 112if not isinstance(system.mem_ctrls[0], m5.objects.DRAMCtrl): 113 fatal("This script assumes the memory is a DRAMCtrl subclass") 114 115# There is no point slowing things down by saving any data. 116system.mem_ctrls[0].null = True 117 118# Set the address mapping based on input argument 119# Default to RoRaBaCoCh 120if args.addr_map == 0: 121 system.mem_ctrls[0].addr_mapping = "RoCoRaBaCh" 122elif args.addr_map == 1: 123 system.mem_ctrls[0].addr_mapping = "RoRaBaCoCh" 124else: 125 fatal("Did not specify a valid address map argument") 126 127system.mem_ctrls[0].page_policy = args.page_policy 128 129# We create a traffic generator state for each param combination we want to 130# test. Each traffic generator state is specified in the config file and the 131# generator remains in the state for specific period. This period is 0.25 ms. 132# Stats are dumped and reset at the state transition. 133period = 250000000 134 135# We specify the states in a config file input to the traffic generator. 136cfg_file_name = "configs/dram/lowp_sweep.cfg" 137cfg_file = open(cfg_file_name, 'w') 138 139# Get the number of banks 140nbr_banks = int(system.mem_ctrls[0].banks_per_rank.value) 141 142# determine the burst size in bytes 143burst_size = int((system.mem_ctrls[0].devices_per_rank.value * 144 system.mem_ctrls[0].device_bus_width.value * 145 system.mem_ctrls[0].burst_length.value) / 8) 146 147# next, get the page size in bytes (the rowbuffer size is already in bytes) 148page_size = system.mem_ctrls[0].devices_per_rank.value * \ 149 system.mem_ctrls[0].device_rowbuffer_size.value 150 151# Inter-request delay should be such that we can hit as many transitions 152# to/from low power states as possible to. We provide a min and max itt to the 153# traffic generator and it randomises in the range. The parameter is in 154# seconds and we need it in ticks (ps). 155itt_min = system.mem_ctrls[0].tBURST.value * 1000000000000 156 157#The itt value when set to (tRAS + tRP + tCK) covers the case where 158# a read command is delayed beyond the delay from ACT to PRE_PDN entry of the 159# previous command. For write command followed by precharge, this delay 160# between a write and power down entry will be tRCD + tCL + tWR + tRP + tCK. 161# As we use this delay as a unit and create multiples of it as bigger delays 162# for the sweep, this parameter works for reads, writes and mix of them. 163pd_entry_time = (system.mem_ctrls[0].tRAS.value + 164 system.mem_ctrls[0].tRP.value + 165 system.mem_ctrls[0].tCK.value) * 1000000000000 166 167# We sweep itt max using the multipliers specified by the user. 168itt_max_str = args.itt_list.strip().split() 169itt_max_multiples = map(lambda x : int(x), itt_max_str) 170if len(itt_max_multiples) == 0: 171 fatal("String for itt-max-list detected empty\n") 172 173itt_max_values = map(lambda m : pd_entry_time * m, itt_max_multiples) 174 175# Generate request addresses in the entire range, assume we start at 0 176max_addr = mem_range.end 177 178# For max stride, use min of the page size and 512 bytes as that should be 179# more than enough 180max_stride = min(512, page_size) 181mid_stride = 4 * burst_size 182stride_values = [burst_size, mid_stride, max_stride] 183 184# be selective about bank utilization instead of going from 1 to the number of 185# banks 186bank_util_values = [1, int(nbr_banks/2), nbr_banks] 187 188# Next we create the config file, but first a comment 189cfg_file.write("""# STATE state# period mode=DRAM 190# read_percent start_addr end_addr req_size min_itt max_itt data_limit 191# stride_size page_size #banks #banks_util addr_map #ranks\n""") 192 193nxt_state = 0 194for itt_max in itt_max_values: 195 for bank in bank_util_values: 196 for stride_size in stride_values: 197 cfg_file.write("STATE %d %d %s %d 0 %d %d " 198 "%d %d %d %d %d %d %d %d %d\n" % 199 (nxt_state, period, "DRAM", args.rd_perc, max_addr, 200 burst_size, itt_min, itt_max, 0, stride_size, 201 page_size, nbr_banks, bank, args.addr_map, 202 args.mem_ranks)) 203 nxt_state = nxt_state + 1 204 205# State for idle period 206idle_period = args.idle_end 207cfg_file.write("STATE %d %d IDLE\n" % (nxt_state, idle_period)) 208 209# Init state is state 0 210cfg_file.write("INIT 0\n") 211 212# Go through the states one by one 213for state in range(1, nxt_state + 1): 214 cfg_file.write("TRANSITION %d %d 1\n" % (state - 1, state)) 215 216# Transition from last state to itself to not break the probability math 217cfg_file.write("TRANSITION %d %d 1\n" % (nxt_state, nxt_state)) 218cfg_file.close() 219 220# create a traffic generator, and point it to the file we just created 221system.tgen = TrafficGen(config_file = cfg_file_name) 222 223# add a communication monitor 224system.monitor = CommMonitor() 225 226# connect the traffic generator to the bus via a communication monitor 227system.tgen.port = system.monitor.slave 228system.monitor.master = system.membus.slave 229 230# connect the system port even if it is not used in this example 231system.system_port = system.membus.slave 232 233# every period, dump and reset all stats 234periodicStatDump(period) 235 236root = Root(full_system = False, system = system) 237root.system.mem_mode = 'timing' 238 239m5.instantiate() 240 241# Simulate for exactly as long as it takes to go through all the states 242# This is why sim exists. 243m5.simulate(nxt_state * period + idle_period) 244print("--- Done DRAM low power sweep ---") 245print("Fixed params - ") 246print("\tburst: %d, banks: %d, max stride: %d, itt min: %s ns" % \ 247 (burst_size, nbr_banks, max_stride, itt_min)) 248print("Swept params - ") 249print("\titt max multiples input:", itt_max_multiples) 250print("\titt max values", itt_max_values) 251print("\tbank utilization values", bank_util_values) 252print("\tstride values:", stride_values) 253print("Traffic gen config file:", cfg_file_name) 254