Simulation.py revision 5869:acbe11bbfe68 
1# Copyright (c) 2006-2008 The Regents of The University of Michigan
2# All rights reserved.
3#
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5# modification, are permitted provided that the following conditions are
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7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
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11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Lisa Hsu
28
29from os import getcwd
30from os.path import join as joinpath
31import m5
32from m5.objects import *
33m5.AddToPath('../common')
34from Caches import L1Cache
35
36def setCPUClass(options):
37
38    atomic = False
39    if options.timing:
40        class TmpClass(TimingSimpleCPU): pass
41    elif options.detailed:
42        if not options.caches:
43            print "O3 CPU must be used with caches"
44            sys.exit(1)
45        class TmpClass(DerivO3CPU): pass
46    elif options.inorder:
47        if not options.caches:
48            print "InOrder CPU must be used with caches"
49            sys.exit(1)
50        class TmpClass(InOrderCPU): pass
51    else:
52        class TmpClass(AtomicSimpleCPU): pass
53        atomic = True
54
55    CPUClass = None
56    test_mem_mode = 'atomic'
57
58    if not atomic:
59        if options.checkpoint_restore != None or options.fast_forward:
60            CPUClass = TmpClass
61            class TmpClass(AtomicSimpleCPU): pass
62        else:
63            test_mem_mode = 'timing'
64
65    return (TmpClass, test_mem_mode, CPUClass)
66
67
68def run(options, root, testsys, cpu_class):
69    if options.maxtick:
70        maxtick = options.maxtick
71    elif options.maxtime:
72        simtime = m5.ticks.seconds(simtime)
73        print "simulating for: ", simtime
74        maxtick = simtime
75    else:
76        maxtick = m5.MaxTick
77
78    if options.checkpoint_dir:
79        cptdir = options.checkpoint_dir
80    elif m5.options.outdir:
81        cptdir = m5.options.outdir
82    else:
83        cptdir = getcwd()
84
85    if options.fast_forward and options.checkpoint_restore != None:
86        m5.fatal("Error: Can't specify both --fast-forward and --checkpoint-restore")
87
88    if options.standard_switch and not options.caches:
89        m5.fatal("Error: Must specify --caches when using --standard-switch")
90
91    np = options.num_cpus
92    max_checkpoints = options.max_checkpoints
93    switch_cpus = None
94
95    if cpu_class:
96        switch_cpus = [cpu_class(defer_registration=True, cpu_id=(np+i))
97                       for i in xrange(np)]
98
99        for i in xrange(np):
100            if options.fast_forward:
101                testsys.cpu[i].max_insts_any_thread = int(options.fast_forward)
102            switch_cpus[i].system =  testsys
103            if not m5.build_env['FULL_SYSTEM']:
104                switch_cpus[i].workload = testsys.cpu[i].workload
105            switch_cpus[i].clock = testsys.cpu[0].clock
106            # simulation period
107            if options.max_inst:
108                switch_cpus[i].max_insts_any_thread = options.max_inst
109
110        testsys.switch_cpus = switch_cpus
111        switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
112
113    if options.standard_switch:
114        switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(np+i))
115                       for i in xrange(np)]
116        switch_cpus_1 = [DerivO3CPU(defer_registration=True, cpu_id=(2*np+i))
117                        for i in xrange(np)]
118
119        for i in xrange(np):
120            switch_cpus[i].system =  testsys
121            switch_cpus_1[i].system =  testsys
122            if not m5.build_env['FULL_SYSTEM']:
123                switch_cpus[i].workload = testsys.cpu[i].workload
124                switch_cpus_1[i].workload = testsys.cpu[i].workload
125            switch_cpus[i].clock = testsys.cpu[0].clock
126            switch_cpus_1[i].clock = testsys.cpu[0].clock
127
128            # if restoring, make atomic cpu simulate only a few instructions
129            if options.checkpoint_restore != None:
130                testsys.cpu[i].max_insts_any_thread = 1
131            # Fast forward to specified location if we are not restoring
132            elif options.fast_forward:
133                testsys.cpu[i].max_insts_any_thread = int(options.fast_forward)
134            # Fast forward to a simpoint (warning: time consuming)
135            elif options.simpoint:
136                if testsys.cpu[i].workload[0].simpoint == 0:
137                    m5.fatal('simpoint not found')
138                testsys.cpu[i].max_insts_any_thread = \
139                    testsys.cpu[i].workload[0].simpoint
140            # No distance specified, just switch
141            else:
142                testsys.cpu[i].max_insts_any_thread = 1
143
144            # warmup period
145            if options.warmup_insts:
146                switch_cpus[i].max_insts_any_thread =  options.warmup_insts
147
148            # simulation period
149            if options.max_inst:
150                switch_cpus_1[i].max_insts_any_thread = options.max_inst
151
152            if not options.caches:
153                # O3 CPU must have a cache to work.
154                switch_cpus_1[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
155                                                         L1Cache(size = '64kB'))
156                switch_cpus_1[i].connectMemPorts(testsys.membus)
157
158            testsys.switch_cpus = switch_cpus
159            testsys.switch_cpus_1 = switch_cpus_1
160            switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
161            switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)]
162
163    # set the checkpoint in the cpu before m5.instantiate is called
164    if options.take_checkpoints != None and \
165           (options.simpoint or options.at_instruction):
166        offset = int(options.take_checkpoints)
167        # Set an instruction break point
168        if options.simpoint:
169            for i in xrange(np):
170                if testsys.cpu[i].workload[0].simpoint == 0:
171                    m5.fatal('no simpoint for testsys.cpu[%d].workload[0]', i)
172                checkpoint_inst = int(testsys.cpu[i].workload[0].simpoint) + offset
173                testsys.cpu[i].max_insts_any_thread = checkpoint_inst
174                # used for output below
175                options.take_checkpoints = checkpoint_inst
176        else:
177            options.take_checkpoints = offset
178            # Set all test cpus with the right number of instructions
179            # for the upcoming simulation
180            for i in xrange(np):
181                testsys.cpu[i].max_insts_any_thread = offset
182
183    m5.instantiate(root)
184
185    if options.checkpoint_restore != None:
186        from os.path import isdir, exists
187        from os import listdir
188        import re
189
190        if not isdir(cptdir):
191            m5.fatal("checkpoint dir %s does not exist!", cptdir)
192
193        if options.at_instruction:
194            checkpoint_dir = joinpath(cptdir, "cpt.%s.%s" % \
195                    (options.bench, options.checkpoint_restore))
196            if not exists(checkpoint_dir):
197                m5.fatal("Unable to find checkpoint directory %s",
198                         checkpoint_dir)
199
200            print "Restoring checkpoint ..."
201            m5.restoreCheckpoint(root, checkpoint_dir)
202            print "Done."
203        elif options.simpoint:
204            # assume workload 0 has the simpoint
205            if testsys.cpu[0].workload[0].simpoint == 0:
206                m5.fatal('Unable to find simpoint')
207
208            options.checkpoint_restore += \
209                int(testsys.cpu[0].workload[0].simpoint)
210
211            checkpoint_dir = joinpath(cptdir, "cpt.%s.%d" % \
212                    (options.bench, options.checkpoint_restore))
213            if not exists(checkpoint_dir):
214                m5.fatal("Unable to find checkpoint directory %s.%s",
215                        options.bench, options.checkpoint_restore)
216
217            print "Restoring checkpoint ..."
218            m5.restoreCheckpoint(root,checkpoint_dir)
219            print "Done."
220        else:
221            dirs = listdir(cptdir)
222            expr = re.compile('cpt\.([0-9]*)')
223            cpts = []
224            for dir in dirs:
225                match = expr.match(dir)
226                if match:
227                    cpts.append(match.group(1))
228
229            cpts.sort(lambda a,b: cmp(long(a), long(b)))
230
231            cpt_num = options.checkpoint_restore
232
233            if cpt_num > len(cpts):
234                m5.fatal('Checkpoint %d not found', cpt_num)
235
236            ## Adjust max tick based on our starting tick
237            maxtick = maxtick - int(cpts[cpt_num - 1])
238
239            ## Restore the checkpoint
240            m5.restoreCheckpoint(root,
241                    joinpath(cptdir, "cpt.%s" % cpts[cpt_num - 1]))
242
243    if options.standard_switch or cpu_class:
244        if options.standard_switch:
245            print "Switch at instruction count:%s" % \
246                    str(testsys.cpu[0].max_insts_any_thread)
247            exit_event = m5.simulate()
248        elif cpu_class and options.fast_forward:
249            print "Switch at instruction count:%s" % \
250                    str(testsys.cpu[0].max_insts_any_thread)
251            exit_event = m5.simulate()
252        else:
253            print "Switch at curTick count:%s" % str(10000)
254            exit_event = m5.simulate(10000)
255        print "Switched CPUS @ cycle = %s" % (m5.curTick())
256
257        # when you change to Timing (or Atomic), you halt the system
258        # given as argument.  When you are finished with the system
259        # changes (including switchCpus), you must resume the system
260        # manually.  You DON'T need to resume after just switching
261        # CPUs if you haven't changed anything on the system level.
262
263        m5.changeToTiming(testsys)
264        m5.switchCpus(switch_cpu_list)
265        m5.resume(testsys)
266
267        if options.standard_switch:
268            print "Switch at instruction count:%d" % \
269                    (testsys.switch_cpus[0].max_insts_any_thread)
270
271            #warmup instruction count may have already been set
272            if options.warmup_insts:
273                exit_event = m5.simulate()
274            else:
275                exit_event = m5.simulate(options.warmup)
276            print "Switching CPUS @ cycle = %s" % (m5.curTick())
277            print "Simulation ends instruction count:%d" % \
278                    (testsys.switch_cpus_1[0].max_insts_any_thread)
279            m5.drain(testsys)
280            m5.switchCpus(switch_cpu_list1)
281            m5.resume(testsys)
282
283    num_checkpoints = 0
284    exit_cause = ''
285
286    # Checkpoints being taken via the command line at <when> and at
287    # subsequent periods of <period>.  Checkpoint instructions
288    # received from the benchmark running are ignored and skipped in
289    # favor of command line checkpoint instructions.
290    if options.take_checkpoints != None :
291        if options.at_instruction or options.simpoint:
292            checkpoint_inst = int(options.take_checkpoints)
293
294            # maintain correct offset if we restored from some instruction
295            if options.checkpoint_restore != None:
296                checkpoint_inst += options.checkpoint_restore
297
298            print "Creating checkpoint at inst:%d" % (checkpoint_inst)
299            exit_event = m5.simulate()
300            print "exit cause = %s" % (exit_event.getCause())
301
302            # skip checkpoint instructions should they exist
303            while exit_event.getCause() == "checkpoint":
304                exit_event = m5.simulate()
305
306            if exit_event.getCause() == \
307                   "a thread reached the max instruction count":
308                m5.checkpoint(root, joinpath(cptdir, "cpt.%s.%d" % \
309                        (options.bench, checkpoint_inst)))
310                print "Checkpoint written."
311                num_checkpoints += 1
312
313            if exit_event.getCause() == "user interrupt received":
314                exit_cause = exit_event.getCause();
315        else:
316            when, period = options.take_checkpoints.split(",", 1)
317            when = int(when)
318            period = int(period)
319
320            exit_event = m5.simulate(when)
321            while exit_event.getCause() == "checkpoint":
322                exit_event = m5.simulate(when - m5.curTick())
323
324            if exit_event.getCause() == "simulate() limit reached":
325                m5.checkpoint(root, joinpath(cptdir, "cpt.%d"))
326                num_checkpoints += 1
327
328            sim_ticks = when
329            exit_cause = "maximum %d checkpoints dropped" % max_checkpoints
330            while num_checkpoints < max_checkpoints and \
331                    exit_event.getCause() == "simulate() limit reached":
332                if (sim_ticks + period) > maxtick:
333                    exit_event = m5.simulate(maxtick - sim_ticks)
334                    exit_cause = exit_event.getCause()
335                    break
336                else:
337                    exit_event = m5.simulate(period)
338                    sim_ticks += period
339                    while exit_event.getCause() == "checkpoint":
340                        exit_event = m5.simulate(sim_ticks - m5.curTick())
341                    if exit_event.getCause() == "simulate() limit reached":
342                        m5.checkpoint(root, joinpath(cptdir, "cpt.%d"))
343                        num_checkpoints += 1
344
345            if exit_event.getCause() != "simulate() limit reached":
346                exit_cause = exit_event.getCause();
347
348    else: # no checkpoints being taken via this script
349        if options.fast_forward:
350            m5.stats.reset()
351        print "**** REAL SIMULATION ****"
352        exit_event = m5.simulate(maxtick)
353
354        while exit_event.getCause() == "checkpoint":
355            m5.checkpoint(root, joinpath(cptdir, "cpt.%d"))
356            num_checkpoints += 1
357            if num_checkpoints == max_checkpoints:
358                exit_cause = "maximum %d checkpoints dropped" % max_checkpoints
359                break
360
361            exit_event = m5.simulate(maxtick - m5.curTick())
362            exit_cause = exit_event.getCause()
363
364    if exit_cause == '':
365        exit_cause = exit_event.getCause()
366    print 'Exiting @ cycle %i because %s' % (m5.curTick(), exit_cause)
367
368