Simulation.py revision 3511:8cb26619b6ec 
1# Copyright (c) 2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Lisa Hsu
28
29from os import getcwd
30from os.path import join as joinpath
31import m5
32from m5.objects import *
33m5.AddToPath('../common')
34from Caches import L1Cache
35
36def setCPUClass(options):
37
38    atomic = False
39    if options.timing:
40        TmpClass = TimingSimpleCPU
41    elif options.detailed:
42        TmpClass = DerivO3CPU
43    else:
44        TmpClass = AtomicSimpleCPU
45        atomic = True
46
47    CPUClass = None
48    test_mem_mode = 'atomic'
49
50    if not atomic:
51        if options.checkpoint_restore:
52            CPUClass = TmpClass
53            TmpClass = AtomicSimpleCPU
54        else:
55            test_mem_mode = 'timing'
56
57    return (TmpClass, test_mem_mode, CPUClass)
58
59
60def run(options, root, testsys, cpu_class):
61    if options.maxtick:
62        maxtick = options.maxtick
63    elif options.maxtime:
64        simtime = int(options.maxtime * root.clock.value)
65        print "simulating for: ", simtime
66        maxtick = simtime
67    else:
68        maxtick = m5.MaxTick
69
70    if options.checkpoint_dir:
71        cptdir = options.checkpoint_dir
72    else:
73        cptdir = getcwd()
74
75    np = options.num_cpus
76    max_checkpoints = options.max_checkpoints
77    switch_cpus = None
78
79    if cpu_class:
80        switch_cpus = [cpu_class(defer_registration=True, cpu_id=(np+i))
81                       for i in xrange(np)]
82
83        for i in xrange(np):
84            switch_cpus[i].system =  testsys
85            if not m5.build_env['FULL_SYSTEM']:
86                switch_cpus[i].workload = testsys.cpu[i].workload
87            switch_cpus[i].clock = testsys.cpu[0].clock
88            if options.caches:
89                switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
90                                                       L1Cache(size = '64kB'))
91                switch_cpus[i].connectMemPorts(testsys.membus)
92
93        root.switch_cpus = switch_cpus
94        switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
95
96    if options.standard_switch:
97        switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(np+i))
98                       for i in xrange(np)]
99        switch_cpus_1 = [DerivO3CPU(defer_registration=True, cpu_id=(2*np+i))
100                        for i in xrange(np)]
101
102        for i in xrange(np):
103            switch_cpus[i].system =  testsys
104            switch_cpus_1[i].system =  testsys
105            if not m5.build_env['FULL_SYSTEM']:
106                switch_cpus[i].workload = testsys.cpu[i].workload
107                switch_cpus_1[i].workload = testsys.cpu[i].workload
108            switch_cpus[i].clock = testsys.cpu[0].clock
109            switch_cpus_1[i].clock = testsys.cpu[0].clock
110
111            if options.caches:
112                switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
113                                                       L1Cache(size = '64kB'))
114                switch_cpus[i].connectMemPorts(testsys.membus)
115            else:
116                # O3 CPU must have a cache to work.
117                switch_cpus_1[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
118                                                         L1Cache(size = '64kB'))
119                switch_cpus_1[i].connectMemPorts(testsys.membus)
120
121
122            root.switch_cpus = switch_cpus
123            root.switch_cpus_1 = switch_cpus_1
124            switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
125            switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)]
126
127    m5.instantiate(root)
128
129    if options.checkpoint_restore:
130        from os.path import isdir
131        from os import listdir
132        import re
133
134        if not isdir(cptdir):
135            m5.panic("checkpoint dir %s does not exist!" % cptdir)
136
137        dirs = listdir(cptdir)
138        expr = re.compile('cpt.([0-9]*)')
139        cpts = []
140        for dir in dirs:
141            match = expr.match(dir)
142            if match:
143                cpts.append(match.group(1))
144
145        cpts.sort(lambda a,b: cmp(long(a), long(b)))
146
147        cpt_num = options.checkpoint_restore
148
149        if cpt_num > len(cpts):
150            m5.panic('Checkpoint %d not found' % cpt_num)
151
152        m5.restoreCheckpoint(root,
153                             joinpath(cptdir, "cpt.%s" % cpts[cpt_num - 1]))
154
155    if options.standard_switch or cpu_class:
156        exit_event = m5.simulate(10000)
157
158        ## when you change to Timing (or Atomic), you halt the system given
159        ## as argument.  When you are finished with the system changes
160        ## (including switchCpus), you must resume the system manually.
161        ## You DON'T need to resume after just switching CPUs if you haven't
162        ## changed anything on the system level.
163
164        m5.changeToTiming(testsys)
165        m5.switchCpus(switch_cpu_list)
166        m5.resume(testsys)
167
168        if options.standard_switch:
169            exit_event = m5.simulate(options.warmup)
170            m5.switchCpus(switch_cpu_list1)
171
172    num_checkpoints = 0
173    exit_cause = ''
174
175    ## Checkpoints being taken via the command line at <when> and at subsequent
176    ## periods of <period>.  Checkpoint instructions received from the benchmark running
177    ## are ignored and skipped in favor of command line checkpoint instructions.
178    if options.take_checkpoints:
179        [when, period] = options.take_checkpoints.split(",", 1)
180        when = int(when)
181        period = int(period)
182
183        exit_event = m5.simulate(when)
184        while exit_event.getCause() == "checkpoint":
185            exit_event = m5.simulate(when - m5.curTick())
186
187        if exit_event.getCause() == "simulate() limit reached":
188            m5.checkpoint(root, joinpath(cptdir, "cpt.%d"))
189            num_checkpoints += 1
190
191        sim_ticks = when
192        exit_cause = "maximum %d checkpoints dropped" % max_checkpoints
193        while num_checkpoints < max_checkpoints:
194            if (sim_ticks + period) > maxtick:
195                exit_event = m5.simulate(maxtick - sim_ticks)
196                exit_cause = exit_event.getCause()
197                break
198            else:
199                exit_event = m5.simulate(period)
200                sim_ticks += period
201                while exit_event.getCause() == "checkpoint":
202                    exit_event = m5.simulate(sim_ticks - m5.curTick())
203                if exit_event.getCause() == "simulate() limit reached":
204                    m5.checkpoint(root, joinpath(cptdir, "cpt.%d"))
205                    num_checkpoints += 1
206
207    else: #no checkpoints being taken via this script
208        exit_event = m5.simulate(maxtick)
209
210        while exit_event.getCause() == "checkpoint":
211            m5.checkpoint(root, joinpath(cptdir, "cpt.%d"))
212            num_checkpoints += 1
213            if num_checkpoints == max_checkpoints:
214                exit_cause =  "maximum %d checkpoints dropped" % max_checkpoints
215                break
216
217            exit_event = m5.simulate(maxtick - m5.curTick())
218            exit_cause = exit_event.getCause()
219
220    if exit_cause == '':
221        exit_cause = exit_event.getCause()
222    print 'Exiting @ cycle', m5.curTick(), 'because ', exit_cause
223
224