Simulation.py revision 3478:b2372d54182c
16145SN/A# Copyright (c) 2006 The Regents of The University of Michigan
26386SN/A# All rights reserved.
37553SN/A#
46386SN/A# Redistribution and use in source and binary forms, with or without
56386SN/A# modification, are permitted provided that the following conditions are
66386SN/A# met: redistributions of source code must retain the above copyright
76386SN/A# notice, this list of conditions and the following disclaimer;
86386SN/A# redistributions in binary form must reproduce the above copyright
96386SN/A# notice, this list of conditions and the following disclaimer in the
106386SN/A# documentation and/or other materials provided with the distribution;
116386SN/A# neither the name of the copyright holders nor the names of its
126386SN/A# contributors may be used to endorse or promote products derived from
136386SN/A# this software without specific prior written permission.
146386SN/A#
156386SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
166386SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
176386SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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256386SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
266386SN/A#
276386SN/A# Authors: Lisa Hsu
286386SN/A
296145SN/Afrom os import getcwd
3010348Sandreas.hansson@arm.comimport m5
317632SBrad.Beckmann@amd.comfrom m5.objects import *
327632SBrad.Beckmann@amd.comm5.AddToPath('../common')
337632SBrad.Beckmann@amd.comfrom Caches import L1Cache
348232Snate@binkert.org
356145SN/Adef run(options, root, testsys):
367553SN/A    if options.maxtick:
379365Snilay@cs.wisc.edu        maxtick = options.maxtick
389365Snilay@cs.wisc.edu    elif options.maxtime:
399365Snilay@cs.wisc.edu        simtime = int(options.maxtime * root.clock.value)
406145SN/A        print "simulating for: ", simtime
417553SN/A        maxtick = simtime
427553SN/A    else:
437553SN/A        maxtick = -1
446145SN/A
456145SN/A    if options.checkpoint_dir:
467553SN/A        cptdir = options.checkpoint_dir
476145SN/A    else:
486145SN/A        cptdir = getcwd()
496145SN/A
507553SN/A    np = options.num_cpus
517553SN/A    max_checkpoints = options.max_checkpoints
526145SN/A
537553SN/A    if options.standard_switch:
547553SN/A        switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(np+i))
556145SN/A                       for i in xrange(np)]
568950Sandreas.hansson@arm.com        switch_cpus_1 = [DerivO3CPU(defer_registration=True, cpu_id=(2*np+i))
577553SN/A                        for i in xrange(np)]
587553SN/A
597553SN/A        for i in xrange(np):
607553SN/A            switch_cpus[i].system =  testsys
618832SAli.Saidi@ARM.com            switch_cpus_1[i].system =  testsys
627553SN/A            if not m5.build_env['FULL_SYSTEM']:
637553SN/A                switch_cpus[i].workload = testsys.cpu[i].workload
6410348Sandreas.hansson@arm.com                switch_cpus_1[i].workload = testsys.cpu[i].workload
659365Snilay@cs.wisc.edu            switch_cpus[i].clock = testsys.cpu[0].clock
667553SN/A            switch_cpus_1[i].clock = testsys.cpu[0].clock
677553SN/A            if options.caches:
687553SN/A                switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
696145SN/A                                                       L1Cache(size = '64kB'))
709365Snilay@cs.wisc.edu
718949Sandreas.hansson@arm.com            switch_cpus[i].connectMemPorts(testsys.membus)
7210566Sandreas.hansson@arm.com
736145SN/A            root.switch_cpus = switch_cpus
748975Sandreas.hansson@arm.com            root.switch_cpus_1 = switch_cpus_1
757553SN/A            switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
767553SN/A            switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)]
777553SN/A
787553SN/A    m5.instantiate(root)
797553SN/A
807553SN/A    if options.checkpoint_restore:
817553SN/A        from os.path import isdir
827553SN/A        from os import listdir
837553SN/A        import re
847553SN/A
857553SN/A        if not isdir(cptdir):
867553SN/A            m5.panic("checkpoint dir %s does not exist!" % cptdir)
877553SN/A
886145SN/A        dirs = listdir(cptdir)
896145SN/A        expr = re.compile('cpt.([0-9]*)')
9011320Ssteve.reinhardt@amd.com        cpts = []
918655Sandreas.hansson@arm.com        for dir in dirs:
926145SN/A            match = expr.match(dir)
937553SN/A            if match:
9411320Ssteve.reinhardt@amd.com                cpts.append(match.group(1))
957553SN/A
966145SN/A        cpts.sort(lambda a,b: cmp(long(a), long(b)))
977553SN/A
987553SN/A        cpt_num = options.checkpoint_restore
997553SN/A
1007553SN/A        if cpt_num > len(cpts):
1017553SN/A            m5.panic('Checkpoint %d not found' % cpt_num)
1027553SN/A
1037553SN/A        m5.restoreCheckpoint(root,
1047553SN/A                             "/".join([cptdir, "cpt.%s" % cpts[cpt_num - 1]]))
1057553SN/A
1067553SN/A    if options.standard_switch:
1077553SN/A        exit_event = m5.simulate(10000)
1086145SN/A
1096145SN/A        ## when you change to Timing (or Atomic), you halt the system given
1107553SN/A        ## as argument.  When you are finished with the system changes
1117553SN/A        ## (including switchCpus), you must resume the system manually.
1126145SN/A        ## You DON'T need to resume after just switching CPUs if you haven't
1137553SN/A        ## changed anything on the system level.
1146145SN/A
115        m5.changeToTiming(testsys)
116        m5.switchCpus(switch_cpu_list)
117        m5.resume(testsys)
118
119        exit_event = m5.simulate(options.warmup)
120        m5.switchCpus(switch_cpu_list1)
121
122    num_checkpoints = 0
123    exit_cause = ''
124
125    ## Checkpoints being taken via the command line at <when> and at subsequent
126    ## periods of <period>.  Checkpoint instructions received from the benchmark running
127    ## are ignored and skipped in favor of command line checkpoint instructions.
128    if options.take_checkpoints:
129        [when, period] = options.take_checkpoints.split(",", 1)
130        when = int(when)
131        period = int(period)
132
133        exit_event = m5.simulate(when)
134        while exit_event.getCause() == "checkpoint":
135            exit_event = m5.simulate(when - m5.curTick())
136
137        if exit_event.getCause() == "simulate() limit reached":
138            m5.checkpoint(root, "/".join([cptdir,"cpt.%d"]))
139            num_checkpoints += 1
140
141        sim_ticks = when
142        exit_cause = "maximum %d checkpoints dropped" % max_checkpoints
143        while num_checkpoints < max_checkpoints:
144            if (sim_ticks + period) > maxtick and maxtick != -1:
145                exit_event = m5.simulate(maxtick - sim_ticks)
146                exit_cause = exit_event.getCause()
147                break
148            else:
149                exit_event = m5.simulate(period)
150                sim_ticks += period
151                while exit_event.getCause() == "checkpoint":
152                    exit_event = m5.simulate(sim_ticks - m5.curTick())
153                if exit_event.getCause() == "simulate() limit reached":
154                    m5.checkpoint(root, "/".join([cptdir,"cpt.%d"]))
155                    num_checkpoints += 1
156
157    else: #no checkpoints being taken via this script
158        exit_event = m5.simulate(maxtick)
159
160        while exit_event.getCause() == "checkpoint":
161            m5.checkpoint(root, "/".join([cptdir,"cpt.%d"]))
162            num_checkpoints += 1
163            if num_checkpoints == max_checkpoints:
164                exit_cause =  "maximum %d checkpoints dropped" % max_checkpoints
165                break
166
167            if maxtick == -1:
168                exit_event = m5.simulate(maxtick)
169            else:
170                exit_event = m5.simulate(maxtick - m5.curTick())
171
172            exit_cause = exit_event.getCause()
173
174    if exit_cause == '':
175        exit_cause = exit_event.getCause()
176    print 'Exiting @ cycle', m5.curTick(), 'because ', exit_cause
177
178