Simulation.py revision 9457
12810SN/A# Copyright (c) 2006-2008 The Regents of The University of Michigan 211893Snikos.nikoleris@arm.com# Copyright (c) 2010 Advanced Micro Devices, Inc. 39796Sprakash.ramrakhyani@arm.com# All rights reserved. 49796Sprakash.ramrakhyani@arm.com# 59796Sprakash.ramrakhyani@arm.com# Redistribution and use in source and binary forms, with or without 69796Sprakash.ramrakhyani@arm.com# modification, are permitted provided that the following conditions are 79796Sprakash.ramrakhyani@arm.com# met: redistributions of source code must retain the above copyright 89796Sprakash.ramrakhyani@arm.com# notice, this list of conditions and the following disclaimer; 99796Sprakash.ramrakhyani@arm.com# redistributions in binary form must reproduce the above copyright 109796Sprakash.ramrakhyani@arm.com# notice, this list of conditions and the following disclaimer in the 119796Sprakash.ramrakhyani@arm.com# documentation and/or other materials provided with the distribution; 129796Sprakash.ramrakhyani@arm.com# neither the name of the copyright holders nor the names of its 139796Sprakash.ramrakhyani@arm.com# contributors may be used to endorse or promote products derived from 142810SN/A# this software without specific prior written permission. 152810SN/A# 162810SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172810SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182810SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192810SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202810SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212810SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222810SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232810SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242810SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252810SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262810SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272810SN/A# 282810SN/A# Authors: Lisa Hsu 292810SN/A 302810SN/Aimport sys 312810SN/Afrom os import getcwd 322810SN/Afrom os.path import join as joinpath 332810SN/A 342810SN/Aimport m5 352810SN/Afrom m5.defines import buildEnv 362810SN/Afrom m5.objects import * 372810SN/Afrom m5.util import * 382810SN/Afrom O3_ARM_v7a import * 392810SN/A 402810SN/AaddToPath('../common') 412810SN/A 422810SN/Adef getCPUClass(cpu_type): 432810SN/A """Returns the required cpu class and the mode of operation. 442810SN/A """ 452810SN/A 462810SN/A if cpu_type == "timing": 472810SN/A return TimingSimpleCPU, 'timing' 482810SN/A elif cpu_type == "detailed": 4911486Snikos.nikoleris@arm.com return DerivO3CPU, 'timing' 5011486Snikos.nikoleris@arm.com elif cpu_type == "arm_detailed": 518229Snate@binkert.org return O3_ARM_v7a_3, 'timing' 525338Sstever@gmail.com elif cpu_type == "inorder": 532810SN/A return InOrderCPU, 'timing' 542810SN/A else: 559796Sprakash.ramrakhyani@arm.com return AtomicSimpleCPU, 'atomic' 5611893Snikos.nikoleris@arm.com 5711893Snikos.nikoleris@arm.comdef setCPUClass(options): 5811722Ssophiane.senni@gmail.com """Returns two cpu classes and the initial mode of operation. 5911722Ssophiane.senni@gmail.com 6011722Ssophiane.senni@gmail.com Restoring from a checkpoint or fast forwarding through a benchmark 6111722Ssophiane.senni@gmail.com can be done using one type of cpu, and then the actual 6212513Sodanrc@yahoo.com.br simulation can be carried out using another type. This function 6312513Sodanrc@yahoo.com.br returns these two types of cpus and the initial mode of operation 6412629Sodanrc@yahoo.com.br depending on the options provided. 6512629Sodanrc@yahoo.com.br """ 669796Sprakash.ramrakhyani@arm.com 679796Sprakash.ramrakhyani@arm.com if options.cpu_type == "detailed" or \ 689796Sprakash.ramrakhyani@arm.com options.cpu_type == "arm_detailed" or \ 692810SN/A options.cpu_type == "inorder" : 702810SN/A if not options.caches and not options.ruby: 712810SN/A fatal("O3/Inorder CPU must be used with caches") 7210360Sandreas.hansson@arm.com 732810SN/A TmpClass, test_mem_mode = getCPUClass(options.cpu_type) 742810SN/A CPUClass = None 752810SN/A 762810SN/A if options.checkpoint_restore != None: 7712636Sodanrc@yahoo.com.br if options.restore_with_cpu != options.cpu_type: 7812636Sodanrc@yahoo.com.br CPUClass = TmpClass 7912636Sodanrc@yahoo.com.br TmpClass, test_mem_mode = getCPUClass(options.restore_with_cpu) 8012636Sodanrc@yahoo.com.br elif options.fast_forward: 8112636Sodanrc@yahoo.com.br CPUClass = TmpClass 8212636Sodanrc@yahoo.com.br TmpClass = AtomicSimpleCPU 8312636Sodanrc@yahoo.com.br test_mem_mode = 'atomic' 8412636Sodanrc@yahoo.com.br 8512636Sodanrc@yahoo.com.br return (TmpClass, test_mem_mode, CPUClass) 8612636Sodanrc@yahoo.com.br 8712636Sodanrc@yahoo.com.brdef setWorkCountOptions(system, options): 8812636Sodanrc@yahoo.com.br if options.work_item_id != None: 8912636Sodanrc@yahoo.com.br system.work_item_id = options.work_item_id 9012636Sodanrc@yahoo.com.br if options.work_begin_cpu_id_exit != None: 9112636Sodanrc@yahoo.com.br system.work_begin_cpu_id_exit = options.work_begin_cpu_id_exit 9212636Sodanrc@yahoo.com.br if options.work_end_exit_count != None: 9312636Sodanrc@yahoo.com.br system.work_end_exit_count = options.work_end_exit_count 9412636Sodanrc@yahoo.com.br if options.work_end_checkpoint_count != None: 9512636Sodanrc@yahoo.com.br system.work_end_ckpt_count = options.work_end_checkpoint_count 9612636Sodanrc@yahoo.com.br if options.work_begin_exit_count != None: 9712636Sodanrc@yahoo.com.br system.work_begin_exit_count = options.work_begin_exit_count 9812636Sodanrc@yahoo.com.br if options.work_begin_checkpoint_count != None: 9912636Sodanrc@yahoo.com.br system.work_begin_ckpt_count = options.work_begin_checkpoint_count 10012636Sodanrc@yahoo.com.br if options.work_cpus_checkpoint_count != None: 10112636Sodanrc@yahoo.com.br system.work_cpus_ckpt_count = options.work_cpus_checkpoint_count 10212636Sodanrc@yahoo.com.br 10312636Sodanrc@yahoo.com.brdef findCptDir(options, maxtick, cptdir, testsys): 10412636Sodanrc@yahoo.com.br """Figures out the directory from which the checkpointed state is read. 10512636Sodanrc@yahoo.com.br 10612636Sodanrc@yahoo.com.br There are two different ways in which the directories holding checkpoints 10712636Sodanrc@yahoo.com.br can be named -- 10812636Sodanrc@yahoo.com.br 1. cpt.<benchmark name>.<instruction count when the checkpoint was taken> 10912636Sodanrc@yahoo.com.br 2. cpt.<some number, usually the tick value when the checkpoint was taken> 11012636Sodanrc@yahoo.com.br 11112636Sodanrc@yahoo.com.br This function parses through the options to figure out which one of the 11212691Sodanrc@yahoo.com.br above should be used for selecting the checkpoint, and then figures out 11312691Sodanrc@yahoo.com.br the appropriate directory. 11412691Sodanrc@yahoo.com.br 11512636Sodanrc@yahoo.com.br It also sets the value of the maximum tick value till which the simulation 11612636Sodanrc@yahoo.com.br will run. 11712636Sodanrc@yahoo.com.br """ 11812636Sodanrc@yahoo.com.br 11912636Sodanrc@yahoo.com.br from os.path import isdir, exists 12012636Sodanrc@yahoo.com.br from os import listdir 12112636Sodanrc@yahoo.com.br import re 1229796Sprakash.ramrakhyani@arm.com 1232810SN/A if not isdir(cptdir): 12411522Sstephan.diestelhorst@arm.com fatal("checkpoint dir %s does not exist!", cptdir) 12511522Sstephan.diestelhorst@arm.com 1262810SN/A if options.at_instruction or options.simpoint: 12711522Sstephan.diestelhorst@arm.com inst = options.checkpoint_restore 1282810SN/A if options.simpoint: 1292810SN/A # assume workload 0 has the simpoint 1309796Sprakash.ramrakhyani@arm.com if testsys.cpu[0].workload[0].simpoint == 0: 1312810SN/A fatal('Unable to find simpoint') 1322810SN/A inst += int(testsys.cpu[0].workload[0].simpoint) 1332810SN/A 1342810SN/A checkpoint_dir = joinpath(cptdir, "cpt.%s.%s" % (options.bench, inst)) 1352810SN/A if not exists(checkpoint_dir): 1369796Sprakash.ramrakhyani@arm.com fatal("Unable to find checkpoint directory %s", checkpoint_dir) 1372810SN/A else: 1382810SN/A dirs = listdir(cptdir) 1392810SN/A expr = re.compile('cpt\.([0-9]*)') 1402810SN/A cpts = [] 1419796Sprakash.ramrakhyani@arm.com for dir in dirs: 1422810SN/A match = expr.match(dir) 1432810SN/A if match: 1442810SN/A cpts.append(match.group(1)) 1452810SN/A 1469796Sprakash.ramrakhyani@arm.com cpts.sort(lambda a,b: cmp(long(a), long(b))) 1472810SN/A 1482810SN/A cpt_num = options.checkpoint_restore 1492810SN/A if cpt_num > len(cpts): 1502810SN/A fatal('Checkpoint %d not found', cpt_num) 1519796Sprakash.ramrakhyani@arm.com 1522810SN/A maxtick = maxtick - int(cpts[cpt_num - 1]) 1532810SN/A checkpoint_dir = joinpath(cptdir, "cpt.%s" % cpts[cpt_num - 1]) 1542810SN/A 1552810SN/A return maxtick, checkpoint_dir 1562810SN/A 1572810SN/Adef scriptCheckpoints(options, maxtick, cptdir): 1589796Sprakash.ramrakhyani@arm.com if options.at_instruction or options.simpoint: 1592810SN/A checkpoint_inst = int(options.take_checkpoints) 1602810SN/A 1612810SN/A # maintain correct offset if we restored from some instruction 1626978SLisa.Hsu@amd.com if options.checkpoint_restore != None: 1638833Sdam.sunwoo@arm.com checkpoint_inst += options.checkpoint_restore 1649796Sprakash.ramrakhyani@arm.com 1658833Sdam.sunwoo@arm.com print "Creating checkpoint at inst:%d" % (checkpoint_inst) 1666978SLisa.Hsu@amd.com exit_event = m5.simulate() 1676978SLisa.Hsu@amd.com exit_cause = exit_event.getCause() 1688833Sdam.sunwoo@arm.com print "exit cause = %s" % exit_cause 1698833Sdam.sunwoo@arm.com 1708833Sdam.sunwoo@arm.com # skip checkpoint instructions should they exist 1716978SLisa.Hsu@amd.com while exit_cause == "checkpoint": 1726978SLisa.Hsu@amd.com exit_event = m5.simulate() 1739796Sprakash.ramrakhyani@arm.com exit_cause = exit_event.getCause() 1746978SLisa.Hsu@amd.com 1758833Sdam.sunwoo@arm.com if exit_cause == "a thread reached the max instruction count": 1766978SLisa.Hsu@amd.com m5.checkpoint(joinpath(cptdir, "cpt.%s.%d" % \ 1778833Sdam.sunwoo@arm.com (options.bench, checkpoint_inst))) 1788833Sdam.sunwoo@arm.com print "Checkpoint written." 1798833Sdam.sunwoo@arm.com 1806978SLisa.Hsu@amd.com else: 1816978SLisa.Hsu@amd.com when, period = options.take_checkpoints.split(",", 1) 1826978SLisa.Hsu@amd.com when = int(when) 18310024Sdam.sunwoo@arm.com period = int(period) 18410024Sdam.sunwoo@arm.com num_checkpoints = 0 18510024Sdam.sunwoo@arm.com 18610024Sdam.sunwoo@arm.com exit_event = m5.simulate(when) 18710024Sdam.sunwoo@arm.com exit_cause = exit_event.getCause() 18810024Sdam.sunwoo@arm.com while exit_cause == "checkpoint": 18910024Sdam.sunwoo@arm.com exit_event = m5.simulate(when - m5.curTick()) 19010024Sdam.sunwoo@arm.com exit_cause = exit_event.getCause() 19110024Sdam.sunwoo@arm.com 19210024Sdam.sunwoo@arm.com if exit_cause == "simulate() limit reached": 19310024Sdam.sunwoo@arm.com m5.checkpoint(joinpath(cptdir, "cpt.%d")) 19410024Sdam.sunwoo@arm.com num_checkpoints += 1 19510024Sdam.sunwoo@arm.com 19610024Sdam.sunwoo@arm.com sim_ticks = when 19710024Sdam.sunwoo@arm.com max_checkpoints = options.max_checkpoints 19810024Sdam.sunwoo@arm.com 19910024Sdam.sunwoo@arm.com while num_checkpoints < max_checkpoints and \ 20010024Sdam.sunwoo@arm.com exit_cause == "simulate() limit reached": 20110024Sdam.sunwoo@arm.com if (sim_ticks + period) > maxtick: 20210024Sdam.sunwoo@arm.com exit_event = m5.simulate(maxtick - sim_ticks) 20310024Sdam.sunwoo@arm.com exit_cause = exit_event.getCause() 20410024Sdam.sunwoo@arm.com break 20510025Stimothy.jones@arm.com else: 20610025Stimothy.jones@arm.com exit_event = m5.simulate(period) 20710025Stimothy.jones@arm.com exit_cause = exit_event.getCause() 20810025Stimothy.jones@arm.com sim_ticks += period 20910025Stimothy.jones@arm.com while exit_event.getCause() == "checkpoint": 21010025Stimothy.jones@arm.com exit_event = m5.simulate(sim_ticks - m5.curTick()) 21110025Stimothy.jones@arm.com if exit_event.getCause() == "simulate() limit reached": 21210025Stimothy.jones@arm.com m5.checkpoint(joinpath(cptdir, "cpt.%d")) 21310025Stimothy.jones@arm.com num_checkpoints += 1 21410025Stimothy.jones@arm.com 21510024Sdam.sunwoo@arm.com return exit_cause 2162810SN/A 2172810SN/Adef benchCheckpoints(options, maxtick, cptdir): 218 exit_event = m5.simulate(maxtick) 219 exit_cause = exit_event.getCause() 220 221 num_checkpoints = 0 222 max_checkpoints = options.max_checkpoints 223 224 while exit_cause == "checkpoint": 225 m5.checkpoint(joinpath(cptdir, "cpt.%d")) 226 num_checkpoints += 1 227 if num_checkpoints == max_checkpoints: 228 exit_cause = "maximum %d checkpoints dropped" % max_checkpoints 229 break 230 231 exit_event = m5.simulate(maxtick - m5.curTick()) 232 exit_cause = exit_event.getCause() 233 234 return exit_cause 235 236def repeatSwitch(testsys, repeat_switch_cpu_list, maxtick, switch_freq): 237 print "starting switch loop" 238 while True: 239 exit_event = m5.simulate(switch_freq) 240 exit_cause = exit_event.getCause() 241 242 if exit_cause != "simulate() limit reached": 243 return exit_cause 244 245 print "draining the system" 246 m5.drain(testsys) 247 m5.switchCpus(repeat_switch_cpu_list) 248 m5.resume(testsys) 249 250 tmp_cpu_list = [] 251 for old_cpu, new_cpu in repeat_switch_cpu_list: 252 tmp_cpu_list.append((new_cpu, old_cpu)) 253 repeat_switch_cpu_list = tmp_cpu_list 254 255 if (maxtick - m5.curTick()) <= switch_freq: 256 exit_event = m5.simulate(maxtick - m5.curTick()) 257 return exit_event.getCause() 258 259def run(options, root, testsys, cpu_class): 260 if options.maxtick: 261 maxtick = options.maxtick 262 elif options.maxtime: 263 simtime = m5.ticks.seconds(simtime) 264 print "simulating for: ", simtime 265 maxtick = simtime 266 else: 267 maxtick = m5.MaxTick 268 269 if options.checkpoint_dir: 270 cptdir = options.checkpoint_dir 271 elif m5.options.outdir: 272 cptdir = m5.options.outdir 273 else: 274 cptdir = getcwd() 275 276 if options.fast_forward and options.checkpoint_restore != None: 277 fatal("Can't specify both --fast-forward and --checkpoint-restore") 278 279 if options.standard_switch and not options.caches: 280 fatal("Must specify --caches when using --standard-switch") 281 282 if options.standard_switch and options.repeat_switch: 283 fatal("Can't specify both --standard-switch and --repeat-switch") 284 285 if options.repeat_switch and options.take_checkpoints: 286 fatal("Can't specify both --repeat-switch and --take-checkpoints") 287 288 np = options.num_cpus 289 switch_cpus = None 290 291 if options.prog_interval: 292 for i in xrange(np): 293 testsys.cpu[i].progress_interval = options.prog_interval 294 295 if options.maxinsts: 296 for i in xrange(np): 297 testsys.cpu[i].max_insts_any_thread = options.maxinsts 298 299 if cpu_class: 300 switch_cpus = [cpu_class(switched_out=True, cpu_id=(i)) 301 for i in xrange(np)] 302 303 for i in xrange(np): 304 if options.fast_forward: 305 testsys.cpu[i].max_insts_any_thread = int(options.fast_forward) 306 switch_cpus[i].system = testsys 307 switch_cpus[i].workload = testsys.cpu[i].workload 308 switch_cpus[i].clock = testsys.cpu[i].clock 309 # simulation period 310 if options.maxinsts: 311 switch_cpus[i].max_insts_any_thread = options.maxinsts 312 # Add checker cpu if selected 313 if options.checker: 314 switch_cpus[i].addCheckerCpu() 315 316 testsys.switch_cpus = switch_cpus 317 switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] 318 319 if options.repeat_switch: 320 if options.cpu_type == "arm_detailed": 321 if not options.caches: 322 print "O3 CPU must be used with caches" 323 sys.exit(1) 324 325 repeat_switch_cpus = [O3_ARM_v7a_3(switched_out=True, \ 326 cpu_id=(i)) for i in xrange(np)] 327 elif options.cpu_type == "detailed": 328 if not options.caches: 329 print "O3 CPU must be used with caches" 330 sys.exit(1) 331 332 repeat_switch_cpus = [DerivO3CPU(switched_out=True, \ 333 cpu_id=(i)) for i in xrange(np)] 334 elif options.cpu_type == "inorder": 335 print "inorder CPU switching not supported" 336 sys.exit(1) 337 elif options.cpu_type == "timing": 338 repeat_switch_cpus = [TimingSimpleCPU(switched_out=True, \ 339 cpu_id=(i)) for i in xrange(np)] 340 else: 341 repeat_switch_cpus = [AtomicSimpleCPU(switched_out=True, \ 342 cpu_id=(i)) for i in xrange(np)] 343 344 for i in xrange(np): 345 repeat_switch_cpus[i].system = testsys 346 repeat_switch_cpus[i].workload = testsys.cpu[i].workload 347 repeat_switch_cpus[i].clock = testsys.cpu[i].clock 348 349 if options.maxinsts: 350 repeat_switch_cpus[i].max_insts_any_thread = options.maxinsts 351 352 if options.checker: 353 repeat_switch_cpus[i].addCheckerCpu() 354 355 testsys.repeat_switch_cpus = repeat_switch_cpus 356 357 if cpu_class: 358 repeat_switch_cpu_list = [(switch_cpus[i], repeat_switch_cpus[i]) 359 for i in xrange(np)] 360 else: 361 repeat_switch_cpu_list = [(testsys.cpu[i], repeat_switch_cpus[i]) 362 for i in xrange(np)] 363 364 if options.standard_switch: 365 switch_cpus = [TimingSimpleCPU(switched_out=True, cpu_id=(i)) 366 for i in xrange(np)] 367 switch_cpus_1 = [DerivO3CPU(switched_out=True, cpu_id=(i)) 368 for i in xrange(np)] 369 370 for i in xrange(np): 371 switch_cpus[i].system = testsys 372 switch_cpus_1[i].system = testsys 373 switch_cpus[i].workload = testsys.cpu[i].workload 374 switch_cpus_1[i].workload = testsys.cpu[i].workload 375 switch_cpus[i].clock = testsys.cpu[i].clock 376 switch_cpus_1[i].clock = testsys.cpu[i].clock 377 378 # if restoring, make atomic cpu simulate only a few instructions 379 if options.checkpoint_restore != None: 380 testsys.cpu[i].max_insts_any_thread = 1 381 # Fast forward to specified location if we are not restoring 382 elif options.fast_forward: 383 testsys.cpu[i].max_insts_any_thread = int(options.fast_forward) 384 # Fast forward to a simpoint (warning: time consuming) 385 elif options.simpoint: 386 if testsys.cpu[i].workload[0].simpoint == 0: 387 fatal('simpoint not found') 388 testsys.cpu[i].max_insts_any_thread = \ 389 testsys.cpu[i].workload[0].simpoint 390 # No distance specified, just switch 391 else: 392 testsys.cpu[i].max_insts_any_thread = 1 393 394 # warmup period 395 if options.warmup_insts: 396 switch_cpus[i].max_insts_any_thread = options.warmup_insts 397 398 # simulation period 399 if options.maxinsts: 400 switch_cpus_1[i].max_insts_any_thread = options.maxinsts 401 402 # attach the checker cpu if selected 403 if options.checker: 404 switch_cpus[i].addCheckerCpu() 405 switch_cpus_1[i].addCheckerCpu() 406 407 testsys.switch_cpus = switch_cpus 408 testsys.switch_cpus_1 = switch_cpus_1 409 switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] 410 switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)] 411 412 # set the checkpoint in the cpu before m5.instantiate is called 413 if options.take_checkpoints != None and \ 414 (options.simpoint or options.at_instruction): 415 offset = int(options.take_checkpoints) 416 # Set an instruction break point 417 if options.simpoint: 418 for i in xrange(np): 419 if testsys.cpu[i].workload[0].simpoint == 0: 420 fatal('no simpoint for testsys.cpu[%d].workload[0]', i) 421 checkpoint_inst = int(testsys.cpu[i].workload[0].simpoint) + offset 422 testsys.cpu[i].max_insts_any_thread = checkpoint_inst 423 # used for output below 424 options.take_checkpoints = checkpoint_inst 425 else: 426 options.take_checkpoints = offset 427 # Set all test cpus with the right number of instructions 428 # for the upcoming simulation 429 for i in xrange(np): 430 testsys.cpu[i].max_insts_any_thread = offset 431 432 checkpoint_dir = None 433 if options.checkpoint_restore != None: 434 maxtick, checkpoint_dir = findCptDir(options, maxtick, cptdir, testsys) 435 m5.instantiate(checkpoint_dir) 436 437 if options.standard_switch or cpu_class: 438 if options.standard_switch: 439 print "Switch at instruction count:%s" % \ 440 str(testsys.cpu[0].max_insts_any_thread) 441 exit_event = m5.simulate() 442 elif cpu_class and options.fast_forward: 443 print "Switch at instruction count:%s" % \ 444 str(testsys.cpu[0].max_insts_any_thread) 445 exit_event = m5.simulate() 446 else: 447 print "Switch at curTick count:%s" % str(10000) 448 exit_event = m5.simulate(10000) 449 print "Switched CPUS @ tick %s" % (m5.curTick()) 450 451 # when you change to Timing (or Atomic), you halt the system 452 # given as argument. When you are finished with the system 453 # changes (including switchCpus), you must resume the system 454 # manually. You DON'T need to resume after just switching 455 # CPUs if you haven't changed anything on the system level. 456 457 m5.changeToTiming(testsys) 458 m5.switchCpus(switch_cpu_list) 459 m5.resume(testsys) 460 461 if options.standard_switch: 462 print "Switch at instruction count:%d" % \ 463 (testsys.switch_cpus[0].max_insts_any_thread) 464 465 #warmup instruction count may have already been set 466 if options.warmup_insts: 467 exit_event = m5.simulate() 468 else: 469 exit_event = m5.simulate(options.standard_switch) 470 print "Switching CPUS @ tick %s" % (m5.curTick()) 471 print "Simulation ends instruction count:%d" % \ 472 (testsys.switch_cpus_1[0].max_insts_any_thread) 473 m5.drain(testsys) 474 m5.switchCpus(switch_cpu_list1) 475 m5.resume(testsys) 476 477 # If we're taking and restoring checkpoints, use checkpoint_dir 478 # option only for finding the checkpoints to restore from. This 479 # lets us test checkpointing by restoring from one set of 480 # checkpoints, generating a second set, and then comparing them. 481 if options.take_checkpoints and options.checkpoint_restore: 482 if m5.options.outdir: 483 cptdir = m5.options.outdir 484 else: 485 cptdir = getcwd() 486 487 if options.take_checkpoints != None : 488 # Checkpoints being taken via the command line at <when> and at 489 # subsequent periods of <period>. Checkpoint instructions 490 # received from the benchmark running are ignored and skipped in 491 # favor of command line checkpoint instructions. 492 exit_cause = scriptCheckpoints(options, maxtick, cptdir) 493 else: 494 if options.fast_forward: 495 m5.stats.reset() 496 print "**** REAL SIMULATION ****" 497 498 # If checkpoints are being taken, then the checkpoint instruction 499 # will occur in the benchmark code it self. 500 if options.repeat_switch and maxtick > options.repeat_switch: 501 exit_cause = repeatSwitch(testsys, repeat_switch_cpu_list, 502 maxtick, options.repeat_switch) 503 else: 504 exit_cause = benchCheckpoints(options, maxtick, cptdir) 505 506 print 'Exiting @ tick %i because %s' % (m5.curTick(), exit_cause) 507 if options.checkpoint_at_end: 508 m5.checkpoint(joinpath(cptdir, "cpt.%d")) 509 510 sys.exit(exit_event.getCode()) 511