Simulation.py revision 9140
15347Ssaidi@eecs.umich.edu# Copyright (c) 2006-2008 The Regents of The University of Michigan 27534Ssteve.reinhardt@amd.com# Copyright (c) 2010 Advanced Micro Devices, Inc. 33395Shsul@eecs.umich.edu# All rights reserved. 43395Shsul@eecs.umich.edu# 53395Shsul@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 63395Shsul@eecs.umich.edu# modification, are permitted provided that the following conditions are 73395Shsul@eecs.umich.edu# met: redistributions of source code must retain the above copyright 83395Shsul@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 93395Shsul@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 103395Shsul@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 113395Shsul@eecs.umich.edu# documentation and/or other materials provided with the distribution; 123395Shsul@eecs.umich.edu# neither the name of the copyright holders nor the names of its 133395Shsul@eecs.umich.edu# contributors may be used to endorse or promote products derived from 143395Shsul@eecs.umich.edu# this software without specific prior written permission. 153395Shsul@eecs.umich.edu# 163395Shsul@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173395Shsul@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183395Shsul@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193395Shsul@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203395Shsul@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213395Shsul@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223395Shsul@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233395Shsul@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243395Shsul@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253395Shsul@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263395Shsul@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273395Shsul@eecs.umich.edu# 283395Shsul@eecs.umich.edu# Authors: Lisa Hsu 293395Shsul@eecs.umich.edu 303395Shsul@eecs.umich.edufrom os import getcwd 313509Shsul@eecs.umich.edufrom os.path import join as joinpath 326654Snate@binkert.org 333395Shsul@eecs.umich.eduimport m5 346654Snate@binkert.orgfrom m5.defines import buildEnv 353395Shsul@eecs.umich.edufrom m5.objects import * 366654Snate@binkert.orgfrom m5.util import * 378724Srdreslin@umich.edufrom O3_ARM_v7a import * 386654Snate@binkert.org 396654Snate@binkert.orgaddToPath('../common') 403395Shsul@eecs.umich.edu 419139Snilay@cs.wisc.edudef getCPUClass(cpu_type): 429139Snilay@cs.wisc.edu """Returns the required cpu class and the mode of operation. 439139Snilay@cs.wisc.edu """ 449139Snilay@cs.wisc.edu 459139Snilay@cs.wisc.edu if cpu_type == "timing": 469139Snilay@cs.wisc.edu return TimingSimpleCPU, 'timing' 479139Snilay@cs.wisc.edu elif cpu_type == "detailed": 489139Snilay@cs.wisc.edu return DerivO3CPU, 'timing' 499139Snilay@cs.wisc.edu elif cpu_type == "arm_detailed": 509139Snilay@cs.wisc.edu return O3_ARM_v7a_3, 'timing' 519139Snilay@cs.wisc.edu elif cpu_type == "inorder": 529139Snilay@cs.wisc.edu return InOrderCPU, 'timing' 539139Snilay@cs.wisc.edu else: 549139Snilay@cs.wisc.edu return AtomicSimpleCPU, 'atomic' 559139Snilay@cs.wisc.edu 563481Shsul@eecs.umich.edudef setCPUClass(options): 579139Snilay@cs.wisc.edu """Returns two cpu classes and the initial mode of operation. 583481Shsul@eecs.umich.edu 599139Snilay@cs.wisc.edu Restoring from a checkpoint or fast forwarding through a benchmark 609139Snilay@cs.wisc.edu can be done using one type of cpu, and then the actual 619139Snilay@cs.wisc.edu simulation can be carried out using another type. This function 629139Snilay@cs.wisc.edu returns these two types of cpus and the initial mode of operation 639139Snilay@cs.wisc.edu depending on the options provided. 649139Snilay@cs.wisc.edu """ 659139Snilay@cs.wisc.edu 669139Snilay@cs.wisc.edu if options.cpu_type == "detailed" or \ 679139Snilay@cs.wisc.edu options.cpu_type == "arm_detailed" or \ 689139Snilay@cs.wisc.edu options.cpu_type == "inorder" : 698718Snilay@cs.wisc.edu if not options.caches and not options.ruby: 709139Snilay@cs.wisc.edu fatal("O3/Inorder CPU must be used with caches") 713481Shsul@eecs.umich.edu 729139Snilay@cs.wisc.edu TmpClass, test_mem_mode = getCPUClass(options.cpu_type) 733481Shsul@eecs.umich.edu CPUClass = None 743481Shsul@eecs.umich.edu 759139Snilay@cs.wisc.edu if options.checkpoint_restore != None: 769139Snilay@cs.wisc.edu if options.restore_with_cpu != options.cpu_type: 773481Shsul@eecs.umich.edu CPUClass = TmpClass 789139Snilay@cs.wisc.edu TmpClass, test_mem_mode = getCPUClass(options.restore_with_cpu) 799139Snilay@cs.wisc.edu elif options.fast_forward: 809139Snilay@cs.wisc.edu CPUClass = TmpClass 819139Snilay@cs.wisc.edu TmpClass = AtomicSimpleCPU 829139Snilay@cs.wisc.edu test_mem_mode = 'atomic' 833481Shsul@eecs.umich.edu 843481Shsul@eecs.umich.edu return (TmpClass, test_mem_mode, CPUClass) 853481Shsul@eecs.umich.edu 868919Snilay@cs.wisc.edudef setWorkCountOptions(system, options): 878919Snilay@cs.wisc.edu if options.work_item_id != None: 888919Snilay@cs.wisc.edu system.work_item_id = options.work_item_id 898919Snilay@cs.wisc.edu if options.work_begin_cpu_id_exit != None: 908919Snilay@cs.wisc.edu system.work_begin_cpu_id_exit = options.work_begin_cpu_id_exit 918919Snilay@cs.wisc.edu if options.work_end_exit_count != None: 928919Snilay@cs.wisc.edu system.work_end_exit_count = options.work_end_exit_count 938919Snilay@cs.wisc.edu if options.work_end_checkpoint_count != None: 948919Snilay@cs.wisc.edu system.work_end_ckpt_count = options.work_end_checkpoint_count 958919Snilay@cs.wisc.edu if options.work_begin_exit_count != None: 968919Snilay@cs.wisc.edu system.work_begin_exit_count = options.work_begin_exit_count 978919Snilay@cs.wisc.edu if options.work_begin_checkpoint_count != None: 988919Snilay@cs.wisc.edu system.work_begin_ckpt_count = options.work_begin_checkpoint_count 998919Snilay@cs.wisc.edu if options.work_cpus_checkpoint_count != None: 1008919Snilay@cs.wisc.edu system.work_cpus_ckpt_count = options.work_cpus_checkpoint_count 1013481Shsul@eecs.umich.edu 1029140Snilay@cs.wisc.edudef findCptDir(options, maxtick, cptdir, testsys): 1039140Snilay@cs.wisc.edu """Figures out the directory from which the checkpointed state is read. 1049140Snilay@cs.wisc.edu 1059140Snilay@cs.wisc.edu There are two different ways in which the directories holding checkpoints 1069140Snilay@cs.wisc.edu can be named -- 1079140Snilay@cs.wisc.edu 1. cpt.<benchmark name>.<instruction count when the checkpoint was taken> 1089140Snilay@cs.wisc.edu 2. cpt.<some number, usually the tick value when the checkpoint was taken> 1099140Snilay@cs.wisc.edu 1109140Snilay@cs.wisc.edu This function parses through the options to figure out which one of the 1119140Snilay@cs.wisc.edu above should be used for selecting the checkpoint, and then figures out 1129140Snilay@cs.wisc.edu the appropriate directory. 1139140Snilay@cs.wisc.edu 1149140Snilay@cs.wisc.edu It also sets the value of the maximum tick value till which the simulation 1159140Snilay@cs.wisc.edu will run. 1169140Snilay@cs.wisc.edu """ 1179140Snilay@cs.wisc.edu 1189140Snilay@cs.wisc.edu from os.path import isdir, exists 1199140Snilay@cs.wisc.edu from os import listdir 1209140Snilay@cs.wisc.edu import re 1219140Snilay@cs.wisc.edu 1229140Snilay@cs.wisc.edu if not isdir(cptdir): 1239140Snilay@cs.wisc.edu fatal("checkpoint dir %s does not exist!", cptdir) 1249140Snilay@cs.wisc.edu 1259140Snilay@cs.wisc.edu if options.at_instruction or options.simpoint: 1269140Snilay@cs.wisc.edu inst = options.checkpoint_restore 1279140Snilay@cs.wisc.edu if options.simpoint: 1289140Snilay@cs.wisc.edu # assume workload 0 has the simpoint 1299140Snilay@cs.wisc.edu if testsys.cpu[0].workload[0].simpoint == 0: 1309140Snilay@cs.wisc.edu fatal('Unable to find simpoint') 1319140Snilay@cs.wisc.edu inst += int(testsys.cpu[0].workload[0].simpoint) 1329140Snilay@cs.wisc.edu 1339140Snilay@cs.wisc.edu checkpoint_dir = joinpath(cptdir, "cpt.%s.%s" % (options.bench, inst)) 1349140Snilay@cs.wisc.edu if not exists(checkpoint_dir): 1359140Snilay@cs.wisc.edu fatal("Unable to find checkpoint directory %s", checkpoint_dir) 1369140Snilay@cs.wisc.edu else: 1379140Snilay@cs.wisc.edu dirs = listdir(cptdir) 1389140Snilay@cs.wisc.edu expr = re.compile('cpt\.([0-9]*)') 1399140Snilay@cs.wisc.edu cpts = [] 1409140Snilay@cs.wisc.edu for dir in dirs: 1419140Snilay@cs.wisc.edu match = expr.match(dir) 1429140Snilay@cs.wisc.edu if match: 1439140Snilay@cs.wisc.edu cpts.append(match.group(1)) 1449140Snilay@cs.wisc.edu 1459140Snilay@cs.wisc.edu cpts.sort(lambda a,b: cmp(long(a), long(b))) 1469140Snilay@cs.wisc.edu 1479140Snilay@cs.wisc.edu cpt_num = options.checkpoint_restore 1489140Snilay@cs.wisc.edu if cpt_num > len(cpts): 1499140Snilay@cs.wisc.edu fatal('Checkpoint %d not found', cpt_num) 1509140Snilay@cs.wisc.edu 1519140Snilay@cs.wisc.edu maxtick = maxtick - int(cpts[cpt_num - 1]) 1529140Snilay@cs.wisc.edu checkpoint_dir = joinpath(cptdir, "cpt.%s" % cpts[cpt_num - 1]) 1539140Snilay@cs.wisc.edu 1549140Snilay@cs.wisc.edu return maxtick, checkpoint_dir 1559140Snilay@cs.wisc.edu 1569140Snilay@cs.wisc.edudef scriptCheckpoints(options): 1579140Snilay@cs.wisc.edu if options.at_instruction or options.simpoint: 1589140Snilay@cs.wisc.edu checkpoint_inst = int(options.take_checkpoints) 1599140Snilay@cs.wisc.edu 1609140Snilay@cs.wisc.edu # maintain correct offset if we restored from some instruction 1619140Snilay@cs.wisc.edu if options.checkpoint_restore != None: 1629140Snilay@cs.wisc.edu checkpoint_inst += options.checkpoint_restore 1639140Snilay@cs.wisc.edu 1649140Snilay@cs.wisc.edu print "Creating checkpoint at inst:%d" % (checkpoint_inst) 1659140Snilay@cs.wisc.edu exit_event = m5.simulate() 1669140Snilay@cs.wisc.edu exit_cause = exit_event.getCause() 1679140Snilay@cs.wisc.edu print "exit cause = %s" % exit_cause 1689140Snilay@cs.wisc.edu 1699140Snilay@cs.wisc.edu # skip checkpoint instructions should they exist 1709140Snilay@cs.wisc.edu while exit_cause == "checkpoint": 1719140Snilay@cs.wisc.edu exit_event = m5.simulate() 1729140Snilay@cs.wisc.edu exit_cause = exit_event.getCause() 1739140Snilay@cs.wisc.edu 1749140Snilay@cs.wisc.edu if exit_cause == "a thread reached the max instruction count": 1759140Snilay@cs.wisc.edu m5.checkpoint(joinpath(cptdir, "cpt.%s.%d" % \ 1769140Snilay@cs.wisc.edu (options.bench, checkpoint_inst))) 1779140Snilay@cs.wisc.edu print "Checkpoint written." 1789140Snilay@cs.wisc.edu 1799140Snilay@cs.wisc.edu else: 1809140Snilay@cs.wisc.edu when, period = options.take_checkpoints.split(",", 1) 1819140Snilay@cs.wisc.edu when = int(when) 1829140Snilay@cs.wisc.edu period = int(period) 1839140Snilay@cs.wisc.edu 1849140Snilay@cs.wisc.edu exit_event = m5.simulate(when) 1859140Snilay@cs.wisc.edu exit_cause = exit_event.getCause() 1869140Snilay@cs.wisc.edu while exit_cause == "checkpoint": 1879140Snilay@cs.wisc.edu exit_event = m5.simulate(when - m5.curTick()) 1889140Snilay@cs.wisc.edu exit_cause = exit_event.getCause() 1899140Snilay@cs.wisc.edu 1909140Snilay@cs.wisc.edu if exit_cause == "simulate() limit reached": 1919140Snilay@cs.wisc.edu m5.checkpoint(joinpath(cptdir, "cpt.%d")) 1929140Snilay@cs.wisc.edu num_checkpoints += 1 1939140Snilay@cs.wisc.edu 1949140Snilay@cs.wisc.edu sim_ticks = when 1959140Snilay@cs.wisc.edu num_checkpoints = 0 1969140Snilay@cs.wisc.edu max_checkpoints = options.max_checkpoints 1979140Snilay@cs.wisc.edu 1989140Snilay@cs.wisc.edu while num_checkpoints < max_checkpoints and \ 1999140Snilay@cs.wisc.edu exit_cause == "simulate() limit reached": 2009140Snilay@cs.wisc.edu if (sim_ticks + period) > maxtick: 2019140Snilay@cs.wisc.edu exit_event = m5.simulate(maxtick - sim_ticks) 2029140Snilay@cs.wisc.edu exit_cause = exit_event.getCause() 2039140Snilay@cs.wisc.edu break 2049140Snilay@cs.wisc.edu else: 2059140Snilay@cs.wisc.edu exit_event = m5.simulate(period) 2069140Snilay@cs.wisc.edu exit_cause = exit_event.getCause() 2079140Snilay@cs.wisc.edu sim_ticks += period 2089140Snilay@cs.wisc.edu while exit_event.getCause() == "checkpoint": 2099140Snilay@cs.wisc.edu exit_event = m5.simulate(sim_ticks - m5.curTick()) 2109140Snilay@cs.wisc.edu if exit_event.getCause() == "simulate() limit reached": 2119140Snilay@cs.wisc.edu m5.checkpoint(joinpath(cptdir, "cpt.%d")) 2129140Snilay@cs.wisc.edu num_checkpoints += 1 2139140Snilay@cs.wisc.edu 2149140Snilay@cs.wisc.edu return exit_cause 2159140Snilay@cs.wisc.edu 2169140Snilay@cs.wisc.edudef benchCheckpoints(options, maxtick, cptdir): 2179140Snilay@cs.wisc.edu if options.fast_forward: 2189140Snilay@cs.wisc.edu m5.stats.reset() 2199140Snilay@cs.wisc.edu 2209140Snilay@cs.wisc.edu print "**** REAL SIMULATION ****" 2219140Snilay@cs.wisc.edu exit_event = m5.simulate(maxtick) 2229140Snilay@cs.wisc.edu exit_cause = exit_event.getCause() 2239140Snilay@cs.wisc.edu 2249140Snilay@cs.wisc.edu num_checkpoints = 0 2259140Snilay@cs.wisc.edu max_checkpoints = options.max_checkpoints 2269140Snilay@cs.wisc.edu 2279140Snilay@cs.wisc.edu while exit_cause == "checkpoint": 2289140Snilay@cs.wisc.edu m5.checkpoint(joinpath(cptdir, "cpt.%d")) 2299140Snilay@cs.wisc.edu num_checkpoints += 1 2309140Snilay@cs.wisc.edu if num_checkpoints == max_checkpoints: 2319140Snilay@cs.wisc.edu exit_cause = "maximum %d checkpoints dropped" % max_checkpoints 2329140Snilay@cs.wisc.edu break 2339140Snilay@cs.wisc.edu 2349140Snilay@cs.wisc.edu exit_event = m5.simulate(maxtick - m5.curTick()) 2359140Snilay@cs.wisc.edu exit_cause = exit_event.getCause() 2369140Snilay@cs.wisc.edu 2379140Snilay@cs.wisc.edu return exit_cause 2389140Snilay@cs.wisc.edu 2393481Shsul@eecs.umich.edudef run(options, root, testsys, cpu_class): 2403395Shsul@eecs.umich.edu if options.maxtick: 2413395Shsul@eecs.umich.edu maxtick = options.maxtick 2423395Shsul@eecs.umich.edu elif options.maxtime: 2434167Sbinkertn@umich.edu simtime = m5.ticks.seconds(simtime) 2443395Shsul@eecs.umich.edu print "simulating for: ", simtime 2453395Shsul@eecs.umich.edu maxtick = simtime 2463395Shsul@eecs.umich.edu else: 2473511Shsul@eecs.umich.edu maxtick = m5.MaxTick 2483395Shsul@eecs.umich.edu 2493395Shsul@eecs.umich.edu if options.checkpoint_dir: 2503395Shsul@eecs.umich.edu cptdir = options.checkpoint_dir 2515211Ssaidi@eecs.umich.edu elif m5.options.outdir: 2525211Ssaidi@eecs.umich.edu cptdir = m5.options.outdir 2533395Shsul@eecs.umich.edu else: 2543395Shsul@eecs.umich.edu cptdir = getcwd() 2553395Shsul@eecs.umich.edu 2565370Ssaidi@eecs.umich.edu if options.fast_forward and options.checkpoint_restore != None: 2576654Snate@binkert.org fatal("Can't specify both --fast-forward and --checkpoint-restore") 2585370Ssaidi@eecs.umich.edu 2595371Shsul@eecs.umich.edu if options.standard_switch and not options.caches: 2606654Snate@binkert.org fatal("Must specify --caches when using --standard-switch") 2615370Ssaidi@eecs.umich.edu 2623395Shsul@eecs.umich.edu np = options.num_cpus 2633481Shsul@eecs.umich.edu switch_cpus = None 2643481Shsul@eecs.umich.edu 2658318Sksewell@umich.edu if options.prog_interval: 2666144Sksewell@umich.edu for i in xrange(np): 2678311Sksewell@umich.edu testsys.cpu[i].progress_interval = options.prog_interval 2686144Sksewell@umich.edu 2696641Sksewell@umich.edu if options.maxinsts: 2706641Sksewell@umich.edu for i in xrange(np): 2716641Sksewell@umich.edu testsys.cpu[i].max_insts_any_thread = options.maxinsts 2726641Sksewell@umich.edu 2733481Shsul@eecs.umich.edu if cpu_class: 2743481Shsul@eecs.umich.edu switch_cpus = [cpu_class(defer_registration=True, cpu_id=(np+i)) 2753481Shsul@eecs.umich.edu for i in xrange(np)] 2763481Shsul@eecs.umich.edu 2773481Shsul@eecs.umich.edu for i in xrange(np): 2785361Srstrong@cs.ucsd.edu if options.fast_forward: 2795369Ssaidi@eecs.umich.edu testsys.cpu[i].max_insts_any_thread = int(options.fast_forward) 2803481Shsul@eecs.umich.edu switch_cpus[i].system = testsys 2818803Sgblack@eecs.umich.edu switch_cpus[i].workload = testsys.cpu[i].workload 2829129Sandreas.hansson@arm.com switch_cpus[i].clock = testsys.cpu[i].clock 2835369Ssaidi@eecs.umich.edu # simulation period 2848311Sksewell@umich.edu if options.maxinsts: 2858311Sksewell@umich.edu switch_cpus[i].max_insts_any_thread = options.maxinsts 2868887Sgeoffrey.blake@arm.com # Add checker cpu if selected 2878887Sgeoffrey.blake@arm.com if options.checker: 2888887Sgeoffrey.blake@arm.com switch_cpus[i].addCheckerCpu() 2893481Shsul@eecs.umich.edu 2905311Ssaidi@eecs.umich.edu testsys.switch_cpus = switch_cpus 2913481Shsul@eecs.umich.edu switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] 2923395Shsul@eecs.umich.edu 2933395Shsul@eecs.umich.edu if options.standard_switch: 2948211Satgutier@umich.edu if not options.caches: 2958211Satgutier@umich.edu # O3 CPU must have a cache to work. 2968211Satgutier@umich.edu print "O3 CPU must be used with caches" 2978211Satgutier@umich.edu sys.exit(1) 2988211Satgutier@umich.edu 2993395Shsul@eecs.umich.edu switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(np+i)) 3003395Shsul@eecs.umich.edu for i in xrange(np)] 3013478Shsul@eecs.umich.edu switch_cpus_1 = [DerivO3CPU(defer_registration=True, cpu_id=(2*np+i)) 3023395Shsul@eecs.umich.edu for i in xrange(np)] 3033478Shsul@eecs.umich.edu 3043395Shsul@eecs.umich.edu for i in xrange(np): 3053395Shsul@eecs.umich.edu switch_cpus[i].system = testsys 3063478Shsul@eecs.umich.edu switch_cpus_1[i].system = testsys 3078803Sgblack@eecs.umich.edu switch_cpus[i].workload = testsys.cpu[i].workload 3088803Sgblack@eecs.umich.edu switch_cpus_1[i].workload = testsys.cpu[i].workload 3099129Sandreas.hansson@arm.com switch_cpus[i].clock = testsys.cpu[i].clock 3109129Sandreas.hansson@arm.com switch_cpus_1[i].clock = testsys.cpu[i].clock 3113480Shsul@eecs.umich.edu 3125361Srstrong@cs.ucsd.edu # if restoring, make atomic cpu simulate only a few instructions 3135369Ssaidi@eecs.umich.edu if options.checkpoint_restore != None: 3145361Srstrong@cs.ucsd.edu testsys.cpu[i].max_insts_any_thread = 1 3155361Srstrong@cs.ucsd.edu # Fast forward to specified location if we are not restoring 3165361Srstrong@cs.ucsd.edu elif options.fast_forward: 3175369Ssaidi@eecs.umich.edu testsys.cpu[i].max_insts_any_thread = int(options.fast_forward) 3185361Srstrong@cs.ucsd.edu # Fast forward to a simpoint (warning: time consuming) 3195361Srstrong@cs.ucsd.edu elif options.simpoint: 3205378Ssaidi@eecs.umich.edu if testsys.cpu[i].workload[0].simpoint == 0: 3216654Snate@binkert.org fatal('simpoint not found') 3225361Srstrong@cs.ucsd.edu testsys.cpu[i].max_insts_any_thread = \ 3235361Srstrong@cs.ucsd.edu testsys.cpu[i].workload[0].simpoint 3245361Srstrong@cs.ucsd.edu # No distance specified, just switch 3255361Srstrong@cs.ucsd.edu else: 3265361Srstrong@cs.ucsd.edu testsys.cpu[i].max_insts_any_thread = 1 3275361Srstrong@cs.ucsd.edu 3285361Srstrong@cs.ucsd.edu # warmup period 3295361Srstrong@cs.ucsd.edu if options.warmup_insts: 3305361Srstrong@cs.ucsd.edu switch_cpus[i].max_insts_any_thread = options.warmup_insts 3315361Srstrong@cs.ucsd.edu 3325361Srstrong@cs.ucsd.edu # simulation period 3338311Sksewell@umich.edu if options.maxinsts: 3348311Sksewell@umich.edu switch_cpus_1[i].max_insts_any_thread = options.maxinsts 3355353Svilas.sridharan@gmail.com 3368887Sgeoffrey.blake@arm.com # attach the checker cpu if selected 3378887Sgeoffrey.blake@arm.com if options.checker: 3388887Sgeoffrey.blake@arm.com switch_cpus[i].addCheckerCpu() 3398887Sgeoffrey.blake@arm.com switch_cpus_1[i].addCheckerCpu() 3408887Sgeoffrey.blake@arm.com 3418211Satgutier@umich.edu testsys.switch_cpus = switch_cpus 3428211Satgutier@umich.edu testsys.switch_cpus_1 = switch_cpus_1 3438211Satgutier@umich.edu switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] 3448211Satgutier@umich.edu switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)] 3453395Shsul@eecs.umich.edu 3465361Srstrong@cs.ucsd.edu # set the checkpoint in the cpu before m5.instantiate is called 3475369Ssaidi@eecs.umich.edu if options.take_checkpoints != None and \ 3485361Srstrong@cs.ucsd.edu (options.simpoint or options.at_instruction): 3495361Srstrong@cs.ucsd.edu offset = int(options.take_checkpoints) 3505361Srstrong@cs.ucsd.edu # Set an instruction break point 3515361Srstrong@cs.ucsd.edu if options.simpoint: 3525361Srstrong@cs.ucsd.edu for i in xrange(np): 3535378Ssaidi@eecs.umich.edu if testsys.cpu[i].workload[0].simpoint == 0: 3546654Snate@binkert.org fatal('no simpoint for testsys.cpu[%d].workload[0]', i) 3555369Ssaidi@eecs.umich.edu checkpoint_inst = int(testsys.cpu[i].workload[0].simpoint) + offset 3565361Srstrong@cs.ucsd.edu testsys.cpu[i].max_insts_any_thread = checkpoint_inst 3575361Srstrong@cs.ucsd.edu # used for output below 3585361Srstrong@cs.ucsd.edu options.take_checkpoints = checkpoint_inst 3595361Srstrong@cs.ucsd.edu else: 3605361Srstrong@cs.ucsd.edu options.take_checkpoints = offset 3615361Srstrong@cs.ucsd.edu # Set all test cpus with the right number of instructions 3625361Srstrong@cs.ucsd.edu # for the upcoming simulation 3635361Srstrong@cs.ucsd.edu for i in xrange(np): 3645361Srstrong@cs.ucsd.edu testsys.cpu[i].max_insts_any_thread = offset 3655361Srstrong@cs.ucsd.edu 3667531Ssteve.reinhardt@amd.com checkpoint_dir = None 3675369Ssaidi@eecs.umich.edu if options.checkpoint_restore != None: 3689140Snilay@cs.wisc.edu maxtick, checkpoint_dir = findCptDir(options, maxtick, cptdir, testsys) 3697531Ssteve.reinhardt@amd.com m5.instantiate(checkpoint_dir) 3703395Shsul@eecs.umich.edu 3713481Shsul@eecs.umich.edu if options.standard_switch or cpu_class: 3725361Srstrong@cs.ucsd.edu if options.standard_switch: 3735361Srstrong@cs.ucsd.edu print "Switch at instruction count:%s" % \ 3745361Srstrong@cs.ucsd.edu str(testsys.cpu[0].max_insts_any_thread) 3755361Srstrong@cs.ucsd.edu exit_event = m5.simulate() 3765361Srstrong@cs.ucsd.edu elif cpu_class and options.fast_forward: 3775361Srstrong@cs.ucsd.edu print "Switch at instruction count:%s" % \ 3785361Srstrong@cs.ucsd.edu str(testsys.cpu[0].max_insts_any_thread) 3795361Srstrong@cs.ucsd.edu exit_event = m5.simulate() 3805361Srstrong@cs.ucsd.edu else: 3815361Srstrong@cs.ucsd.edu print "Switch at curTick count:%s" % str(10000) 3825361Srstrong@cs.ucsd.edu exit_event = m5.simulate(10000) 3837766Sgblack@eecs.umich.edu print "Switched CPUS @ tick %s" % (m5.curTick()) 3843395Shsul@eecs.umich.edu 3855361Srstrong@cs.ucsd.edu # when you change to Timing (or Atomic), you halt the system 3865361Srstrong@cs.ucsd.edu # given as argument. When you are finished with the system 3875361Srstrong@cs.ucsd.edu # changes (including switchCpus), you must resume the system 3885361Srstrong@cs.ucsd.edu # manually. You DON'T need to resume after just switching 3895361Srstrong@cs.ucsd.edu # CPUs if you haven't changed anything on the system level. 3903395Shsul@eecs.umich.edu 3913395Shsul@eecs.umich.edu m5.changeToTiming(testsys) 3923395Shsul@eecs.umich.edu m5.switchCpus(switch_cpu_list) 3933395Shsul@eecs.umich.edu m5.resume(testsys) 3943395Shsul@eecs.umich.edu 3953481Shsul@eecs.umich.edu if options.standard_switch: 3965361Srstrong@cs.ucsd.edu print "Switch at instruction count:%d" % \ 3975361Srstrong@cs.ucsd.edu (testsys.switch_cpus[0].max_insts_any_thread) 3985361Srstrong@cs.ucsd.edu 3995361Srstrong@cs.ucsd.edu #warmup instruction count may have already been set 4005361Srstrong@cs.ucsd.edu if options.warmup_insts: 4015361Srstrong@cs.ucsd.edu exit_event = m5.simulate() 4025361Srstrong@cs.ucsd.edu else: 4035353Svilas.sridharan@gmail.com exit_event = m5.simulate(options.warmup) 4047766Sgblack@eecs.umich.edu print "Switching CPUS @ tick %s" % (m5.curTick()) 4055361Srstrong@cs.ucsd.edu print "Simulation ends instruction count:%d" % \ 4065361Srstrong@cs.ucsd.edu (testsys.switch_cpus_1[0].max_insts_any_thread) 4075072Ssaidi@eecs.umich.edu m5.drain(testsys) 4083481Shsul@eecs.umich.edu m5.switchCpus(switch_cpu_list1) 4095072Ssaidi@eecs.umich.edu m5.resume(testsys) 4103395Shsul@eecs.umich.edu 4117489Ssteve.reinhardt@amd.com # If we're taking and restoring checkpoints, use checkpoint_dir 4127489Ssteve.reinhardt@amd.com # option only for finding the checkpoints to restore from. This 4137489Ssteve.reinhardt@amd.com # lets us test checkpointing by restoring from one set of 4147489Ssteve.reinhardt@amd.com # checkpoints, generating a second set, and then comparing them. 4157489Ssteve.reinhardt@amd.com if options.take_checkpoints and options.checkpoint_restore: 4167489Ssteve.reinhardt@amd.com if m5.options.outdir: 4177489Ssteve.reinhardt@amd.com cptdir = m5.options.outdir 4187489Ssteve.reinhardt@amd.com else: 4197489Ssteve.reinhardt@amd.com cptdir = getcwd() 4207489Ssteve.reinhardt@amd.com 4215369Ssaidi@eecs.umich.edu if options.take_checkpoints != None : 4229140Snilay@cs.wisc.edu # Checkpoints being taken via the command line at <when> and at 4239140Snilay@cs.wisc.edu # subsequent periods of <period>. Checkpoint instructions 4249140Snilay@cs.wisc.edu # received from the benchmark running are ignored and skipped in 4259140Snilay@cs.wisc.edu # favor of command line checkpoint instructions. 4269140Snilay@cs.wisc.edu exit_cause = scriptCheckpoints(options) 4279140Snilay@cs.wisc.edu else: 4289140Snilay@cs.wisc.edu # If checkpoints are being taken, then the checkpoint instruction 4299140Snilay@cs.wisc.edu # will occur in the benchmark code it self. 4309140Snilay@cs.wisc.edu exit_cause = benchCheckpoints(options, maxtick, cptdir) 4313395Shsul@eecs.umich.edu 4327766Sgblack@eecs.umich.edu print 'Exiting @ tick %i because %s' % (m5.curTick(), exit_cause) 4336776SBrad.Beckmann@amd.com if options.checkpoint_at_end: 4347525Ssteve.reinhardt@amd.com m5.checkpoint(joinpath(cptdir, "cpt.%d")) 435