Simulation.py revision 9139
15347Ssaidi@eecs.umich.edu# Copyright (c) 2006-2008 The Regents of The University of Michigan 27534Ssteve.reinhardt@amd.com# Copyright (c) 2010 Advanced Micro Devices, Inc. 33395Shsul@eecs.umich.edu# All rights reserved. 43395Shsul@eecs.umich.edu# 53395Shsul@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 63395Shsul@eecs.umich.edu# modification, are permitted provided that the following conditions are 73395Shsul@eecs.umich.edu# met: redistributions of source code must retain the above copyright 83395Shsul@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 93395Shsul@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 103395Shsul@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 113395Shsul@eecs.umich.edu# documentation and/or other materials provided with the distribution; 123395Shsul@eecs.umich.edu# neither the name of the copyright holders nor the names of its 133395Shsul@eecs.umich.edu# contributors may be used to endorse or promote products derived from 143395Shsul@eecs.umich.edu# this software without specific prior written permission. 153395Shsul@eecs.umich.edu# 163395Shsul@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173395Shsul@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183395Shsul@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193395Shsul@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203395Shsul@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213395Shsul@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223395Shsul@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233395Shsul@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243395Shsul@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253395Shsul@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263395Shsul@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273395Shsul@eecs.umich.edu# 283395Shsul@eecs.umich.edu# Authors: Lisa Hsu 293395Shsul@eecs.umich.edu 303395Shsul@eecs.umich.edufrom os import getcwd 313509Shsul@eecs.umich.edufrom os.path import join as joinpath 326654Snate@binkert.org 333395Shsul@eecs.umich.eduimport m5 346654Snate@binkert.orgfrom m5.defines import buildEnv 353395Shsul@eecs.umich.edufrom m5.objects import * 366654Snate@binkert.orgfrom m5.util import * 378724Srdreslin@umich.edufrom O3_ARM_v7a import * 386654Snate@binkert.org 396654Snate@binkert.orgaddToPath('../common') 403395Shsul@eecs.umich.edu 419139Snilay@cs.wisc.edudef getCPUClass(cpu_type): 429139Snilay@cs.wisc.edu """Returns the required cpu class and the mode of operation. 439139Snilay@cs.wisc.edu """ 449139Snilay@cs.wisc.edu 459139Snilay@cs.wisc.edu if cpu_type == "timing": 469139Snilay@cs.wisc.edu return TimingSimpleCPU, 'timing' 479139Snilay@cs.wisc.edu elif cpu_type == "detailed": 489139Snilay@cs.wisc.edu return DerivO3CPU, 'timing' 499139Snilay@cs.wisc.edu elif cpu_type == "arm_detailed": 509139Snilay@cs.wisc.edu return O3_ARM_v7a_3, 'timing' 519139Snilay@cs.wisc.edu elif cpu_type == "inorder": 529139Snilay@cs.wisc.edu return InOrderCPU, 'timing' 539139Snilay@cs.wisc.edu else: 549139Snilay@cs.wisc.edu return AtomicSimpleCPU, 'atomic' 559139Snilay@cs.wisc.edu 563481Shsul@eecs.umich.edudef setCPUClass(options): 579139Snilay@cs.wisc.edu """Returns two cpu classes and the initial mode of operation. 583481Shsul@eecs.umich.edu 599139Snilay@cs.wisc.edu Restoring from a checkpoint or fast forwarding through a benchmark 609139Snilay@cs.wisc.edu can be done using one type of cpu, and then the actual 619139Snilay@cs.wisc.edu simulation can be carried out using another type. This function 629139Snilay@cs.wisc.edu returns these two types of cpus and the initial mode of operation 639139Snilay@cs.wisc.edu depending on the options provided. 649139Snilay@cs.wisc.edu """ 659139Snilay@cs.wisc.edu 669139Snilay@cs.wisc.edu if options.cpu_type == "detailed" or \ 679139Snilay@cs.wisc.edu options.cpu_type == "arm_detailed" or \ 689139Snilay@cs.wisc.edu options.cpu_type == "inorder" : 698718Snilay@cs.wisc.edu if not options.caches and not options.ruby: 709139Snilay@cs.wisc.edu fatal("O3/Inorder CPU must be used with caches") 713481Shsul@eecs.umich.edu 729139Snilay@cs.wisc.edu TmpClass, test_mem_mode = getCPUClass(options.cpu_type) 733481Shsul@eecs.umich.edu CPUClass = None 743481Shsul@eecs.umich.edu 759139Snilay@cs.wisc.edu if options.checkpoint_restore != None: 769139Snilay@cs.wisc.edu if options.restore_with_cpu != options.cpu_type: 773481Shsul@eecs.umich.edu CPUClass = TmpClass 789139Snilay@cs.wisc.edu TmpClass, test_mem_mode = getCPUClass(options.restore_with_cpu) 799139Snilay@cs.wisc.edu elif options.fast_forward: 809139Snilay@cs.wisc.edu CPUClass = TmpClass 819139Snilay@cs.wisc.edu TmpClass = AtomicSimpleCPU 829139Snilay@cs.wisc.edu test_mem_mode = 'atomic' 833481Shsul@eecs.umich.edu 843481Shsul@eecs.umich.edu return (TmpClass, test_mem_mode, CPUClass) 853481Shsul@eecs.umich.edu 868919Snilay@cs.wisc.edudef setWorkCountOptions(system, options): 878919Snilay@cs.wisc.edu if options.work_item_id != None: 888919Snilay@cs.wisc.edu system.work_item_id = options.work_item_id 898919Snilay@cs.wisc.edu if options.work_begin_cpu_id_exit != None: 908919Snilay@cs.wisc.edu system.work_begin_cpu_id_exit = options.work_begin_cpu_id_exit 918919Snilay@cs.wisc.edu if options.work_end_exit_count != None: 928919Snilay@cs.wisc.edu system.work_end_exit_count = options.work_end_exit_count 938919Snilay@cs.wisc.edu if options.work_end_checkpoint_count != None: 948919Snilay@cs.wisc.edu system.work_end_ckpt_count = options.work_end_checkpoint_count 958919Snilay@cs.wisc.edu if options.work_begin_exit_count != None: 968919Snilay@cs.wisc.edu system.work_begin_exit_count = options.work_begin_exit_count 978919Snilay@cs.wisc.edu if options.work_begin_checkpoint_count != None: 988919Snilay@cs.wisc.edu system.work_begin_ckpt_count = options.work_begin_checkpoint_count 998919Snilay@cs.wisc.edu if options.work_cpus_checkpoint_count != None: 1008919Snilay@cs.wisc.edu system.work_cpus_ckpt_count = options.work_cpus_checkpoint_count 1013481Shsul@eecs.umich.edu 1023481Shsul@eecs.umich.edudef run(options, root, testsys, cpu_class): 1033395Shsul@eecs.umich.edu if options.maxtick: 1043395Shsul@eecs.umich.edu maxtick = options.maxtick 1053395Shsul@eecs.umich.edu elif options.maxtime: 1064167Sbinkertn@umich.edu simtime = m5.ticks.seconds(simtime) 1073395Shsul@eecs.umich.edu print "simulating for: ", simtime 1083395Shsul@eecs.umich.edu maxtick = simtime 1093395Shsul@eecs.umich.edu else: 1103511Shsul@eecs.umich.edu maxtick = m5.MaxTick 1113395Shsul@eecs.umich.edu 1123395Shsul@eecs.umich.edu if options.checkpoint_dir: 1133395Shsul@eecs.umich.edu cptdir = options.checkpoint_dir 1145211Ssaidi@eecs.umich.edu elif m5.options.outdir: 1155211Ssaidi@eecs.umich.edu cptdir = m5.options.outdir 1163395Shsul@eecs.umich.edu else: 1173395Shsul@eecs.umich.edu cptdir = getcwd() 1183395Shsul@eecs.umich.edu 1195370Ssaidi@eecs.umich.edu if options.fast_forward and options.checkpoint_restore != None: 1206654Snate@binkert.org fatal("Can't specify both --fast-forward and --checkpoint-restore") 1215370Ssaidi@eecs.umich.edu 1225371Shsul@eecs.umich.edu if options.standard_switch and not options.caches: 1236654Snate@binkert.org fatal("Must specify --caches when using --standard-switch") 1245370Ssaidi@eecs.umich.edu 1253395Shsul@eecs.umich.edu np = options.num_cpus 1263395Shsul@eecs.umich.edu max_checkpoints = options.max_checkpoints 1273481Shsul@eecs.umich.edu switch_cpus = None 1283481Shsul@eecs.umich.edu 1298318Sksewell@umich.edu if options.prog_interval: 1306144Sksewell@umich.edu for i in xrange(np): 1318311Sksewell@umich.edu testsys.cpu[i].progress_interval = options.prog_interval 1326144Sksewell@umich.edu 1336641Sksewell@umich.edu if options.maxinsts: 1346641Sksewell@umich.edu for i in xrange(np): 1356641Sksewell@umich.edu testsys.cpu[i].max_insts_any_thread = options.maxinsts 1366641Sksewell@umich.edu 1373481Shsul@eecs.umich.edu if cpu_class: 1383481Shsul@eecs.umich.edu switch_cpus = [cpu_class(defer_registration=True, cpu_id=(np+i)) 1393481Shsul@eecs.umich.edu for i in xrange(np)] 1403481Shsul@eecs.umich.edu 1413481Shsul@eecs.umich.edu for i in xrange(np): 1425361Srstrong@cs.ucsd.edu if options.fast_forward: 1435369Ssaidi@eecs.umich.edu testsys.cpu[i].max_insts_any_thread = int(options.fast_forward) 1443481Shsul@eecs.umich.edu switch_cpus[i].system = testsys 1458803Sgblack@eecs.umich.edu switch_cpus[i].workload = testsys.cpu[i].workload 1469129Sandreas.hansson@arm.com switch_cpus[i].clock = testsys.cpu[i].clock 1475369Ssaidi@eecs.umich.edu # simulation period 1488311Sksewell@umich.edu if options.maxinsts: 1498311Sksewell@umich.edu switch_cpus[i].max_insts_any_thread = options.maxinsts 1508887Sgeoffrey.blake@arm.com # Add checker cpu if selected 1518887Sgeoffrey.blake@arm.com if options.checker: 1528887Sgeoffrey.blake@arm.com switch_cpus[i].addCheckerCpu() 1533481Shsul@eecs.umich.edu 1545311Ssaidi@eecs.umich.edu testsys.switch_cpus = switch_cpus 1553481Shsul@eecs.umich.edu switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] 1563395Shsul@eecs.umich.edu 1573395Shsul@eecs.umich.edu if options.standard_switch: 1588211Satgutier@umich.edu if not options.caches: 1598211Satgutier@umich.edu # O3 CPU must have a cache to work. 1608211Satgutier@umich.edu print "O3 CPU must be used with caches" 1618211Satgutier@umich.edu sys.exit(1) 1628211Satgutier@umich.edu 1633395Shsul@eecs.umich.edu switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(np+i)) 1643395Shsul@eecs.umich.edu for i in xrange(np)] 1653478Shsul@eecs.umich.edu switch_cpus_1 = [DerivO3CPU(defer_registration=True, cpu_id=(2*np+i)) 1663395Shsul@eecs.umich.edu for i in xrange(np)] 1673478Shsul@eecs.umich.edu 1683395Shsul@eecs.umich.edu for i in xrange(np): 1693395Shsul@eecs.umich.edu switch_cpus[i].system = testsys 1703478Shsul@eecs.umich.edu switch_cpus_1[i].system = testsys 1718803Sgblack@eecs.umich.edu switch_cpus[i].workload = testsys.cpu[i].workload 1728803Sgblack@eecs.umich.edu switch_cpus_1[i].workload = testsys.cpu[i].workload 1739129Sandreas.hansson@arm.com switch_cpus[i].clock = testsys.cpu[i].clock 1749129Sandreas.hansson@arm.com switch_cpus_1[i].clock = testsys.cpu[i].clock 1753480Shsul@eecs.umich.edu 1765361Srstrong@cs.ucsd.edu # if restoring, make atomic cpu simulate only a few instructions 1775369Ssaidi@eecs.umich.edu if options.checkpoint_restore != None: 1785361Srstrong@cs.ucsd.edu testsys.cpu[i].max_insts_any_thread = 1 1795361Srstrong@cs.ucsd.edu # Fast forward to specified location if we are not restoring 1805361Srstrong@cs.ucsd.edu elif options.fast_forward: 1815369Ssaidi@eecs.umich.edu testsys.cpu[i].max_insts_any_thread = int(options.fast_forward) 1825361Srstrong@cs.ucsd.edu # Fast forward to a simpoint (warning: time consuming) 1835361Srstrong@cs.ucsd.edu elif options.simpoint: 1845378Ssaidi@eecs.umich.edu if testsys.cpu[i].workload[0].simpoint == 0: 1856654Snate@binkert.org fatal('simpoint not found') 1865361Srstrong@cs.ucsd.edu testsys.cpu[i].max_insts_any_thread = \ 1875361Srstrong@cs.ucsd.edu testsys.cpu[i].workload[0].simpoint 1885361Srstrong@cs.ucsd.edu # No distance specified, just switch 1895361Srstrong@cs.ucsd.edu else: 1905361Srstrong@cs.ucsd.edu testsys.cpu[i].max_insts_any_thread = 1 1915361Srstrong@cs.ucsd.edu 1925361Srstrong@cs.ucsd.edu # warmup period 1935361Srstrong@cs.ucsd.edu if options.warmup_insts: 1945361Srstrong@cs.ucsd.edu switch_cpus[i].max_insts_any_thread = options.warmup_insts 1955361Srstrong@cs.ucsd.edu 1965361Srstrong@cs.ucsd.edu # simulation period 1978311Sksewell@umich.edu if options.maxinsts: 1988311Sksewell@umich.edu switch_cpus_1[i].max_insts_any_thread = options.maxinsts 1995353Svilas.sridharan@gmail.com 2008887Sgeoffrey.blake@arm.com # attach the checker cpu if selected 2018887Sgeoffrey.blake@arm.com if options.checker: 2028887Sgeoffrey.blake@arm.com switch_cpus[i].addCheckerCpu() 2038887Sgeoffrey.blake@arm.com switch_cpus_1[i].addCheckerCpu() 2048887Sgeoffrey.blake@arm.com 2058211Satgutier@umich.edu testsys.switch_cpus = switch_cpus 2068211Satgutier@umich.edu testsys.switch_cpus_1 = switch_cpus_1 2078211Satgutier@umich.edu switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] 2088211Satgutier@umich.edu switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)] 2093395Shsul@eecs.umich.edu 2105361Srstrong@cs.ucsd.edu # set the checkpoint in the cpu before m5.instantiate is called 2115369Ssaidi@eecs.umich.edu if options.take_checkpoints != None and \ 2125361Srstrong@cs.ucsd.edu (options.simpoint or options.at_instruction): 2135361Srstrong@cs.ucsd.edu offset = int(options.take_checkpoints) 2145361Srstrong@cs.ucsd.edu # Set an instruction break point 2155361Srstrong@cs.ucsd.edu if options.simpoint: 2165361Srstrong@cs.ucsd.edu for i in xrange(np): 2175378Ssaidi@eecs.umich.edu if testsys.cpu[i].workload[0].simpoint == 0: 2186654Snate@binkert.org fatal('no simpoint for testsys.cpu[%d].workload[0]', i) 2195369Ssaidi@eecs.umich.edu checkpoint_inst = int(testsys.cpu[i].workload[0].simpoint) + offset 2205361Srstrong@cs.ucsd.edu testsys.cpu[i].max_insts_any_thread = checkpoint_inst 2215361Srstrong@cs.ucsd.edu # used for output below 2225361Srstrong@cs.ucsd.edu options.take_checkpoints = checkpoint_inst 2235361Srstrong@cs.ucsd.edu else: 2245361Srstrong@cs.ucsd.edu options.take_checkpoints = offset 2255361Srstrong@cs.ucsd.edu # Set all test cpus with the right number of instructions 2265361Srstrong@cs.ucsd.edu # for the upcoming simulation 2275361Srstrong@cs.ucsd.edu for i in xrange(np): 2285361Srstrong@cs.ucsd.edu testsys.cpu[i].max_insts_any_thread = offset 2295361Srstrong@cs.ucsd.edu 2307531Ssteve.reinhardt@amd.com checkpoint_dir = None 2315369Ssaidi@eecs.umich.edu if options.checkpoint_restore != None: 2325361Srstrong@cs.ucsd.edu from os.path import isdir, exists 2333395Shsul@eecs.umich.edu from os import listdir 2343395Shsul@eecs.umich.edu import re 2353395Shsul@eecs.umich.edu 2363395Shsul@eecs.umich.edu if not isdir(cptdir): 2376654Snate@binkert.org fatal("checkpoint dir %s does not exist!", cptdir) 2383395Shsul@eecs.umich.edu 2397530Ssteve.reinhardt@amd.com if options.at_instruction or options.simpoint: 2407530Ssteve.reinhardt@amd.com inst = options.checkpoint_restore 2417530Ssteve.reinhardt@amd.com if options.simpoint: 2427530Ssteve.reinhardt@amd.com # assume workload 0 has the simpoint 2437530Ssteve.reinhardt@amd.com if testsys.cpu[0].workload[0].simpoint == 0: 2447530Ssteve.reinhardt@amd.com fatal('Unable to find simpoint') 2457530Ssteve.reinhardt@amd.com inst += int(testsys.cpu[0].workload[0].simpoint) 2467530Ssteve.reinhardt@amd.com 2477530Ssteve.reinhardt@amd.com checkpoint_dir = joinpath(cptdir, 2487530Ssteve.reinhardt@amd.com "cpt.%s.%s" % (options.bench, inst)) 2495361Srstrong@cs.ucsd.edu if not exists(checkpoint_dir): 2506654Snate@binkert.org fatal("Unable to find checkpoint directory %s", checkpoint_dir) 2515361Srstrong@cs.ucsd.edu else: 2525361Srstrong@cs.ucsd.edu dirs = listdir(cptdir) 2535361Srstrong@cs.ucsd.edu expr = re.compile('cpt\.([0-9]*)') 2545361Srstrong@cs.ucsd.edu cpts = [] 2555361Srstrong@cs.ucsd.edu for dir in dirs: 2565361Srstrong@cs.ucsd.edu match = expr.match(dir) 2575361Srstrong@cs.ucsd.edu if match: 2585361Srstrong@cs.ucsd.edu cpts.append(match.group(1)) 2593999Ssaidi@eecs.umich.edu 2605361Srstrong@cs.ucsd.edu cpts.sort(lambda a,b: cmp(long(a), long(b))) 2615361Srstrong@cs.ucsd.edu 2625361Srstrong@cs.ucsd.edu cpt_num = options.checkpoint_restore 2635361Srstrong@cs.ucsd.edu 2645361Srstrong@cs.ucsd.edu if cpt_num > len(cpts): 2656654Snate@binkert.org fatal('Checkpoint %d not found', cpt_num) 2665361Srstrong@cs.ucsd.edu 2675361Srstrong@cs.ucsd.edu ## Adjust max tick based on our starting tick 2685361Srstrong@cs.ucsd.edu maxtick = maxtick - int(cpts[cpt_num - 1]) 2697531Ssteve.reinhardt@amd.com checkpoint_dir = joinpath(cptdir, "cpt.%s" % cpts[cpt_num - 1]) 2705361Srstrong@cs.ucsd.edu 2717531Ssteve.reinhardt@amd.com m5.instantiate(checkpoint_dir) 2723395Shsul@eecs.umich.edu 2733481Shsul@eecs.umich.edu if options.standard_switch or cpu_class: 2745361Srstrong@cs.ucsd.edu if options.standard_switch: 2755361Srstrong@cs.ucsd.edu print "Switch at instruction count:%s" % \ 2765361Srstrong@cs.ucsd.edu str(testsys.cpu[0].max_insts_any_thread) 2775361Srstrong@cs.ucsd.edu exit_event = m5.simulate() 2785361Srstrong@cs.ucsd.edu elif cpu_class and options.fast_forward: 2795361Srstrong@cs.ucsd.edu print "Switch at instruction count:%s" % \ 2805361Srstrong@cs.ucsd.edu str(testsys.cpu[0].max_insts_any_thread) 2815361Srstrong@cs.ucsd.edu exit_event = m5.simulate() 2825361Srstrong@cs.ucsd.edu else: 2835361Srstrong@cs.ucsd.edu print "Switch at curTick count:%s" % str(10000) 2845361Srstrong@cs.ucsd.edu exit_event = m5.simulate(10000) 2857766Sgblack@eecs.umich.edu print "Switched CPUS @ tick %s" % (m5.curTick()) 2863395Shsul@eecs.umich.edu 2875361Srstrong@cs.ucsd.edu # when you change to Timing (or Atomic), you halt the system 2885361Srstrong@cs.ucsd.edu # given as argument. When you are finished with the system 2895361Srstrong@cs.ucsd.edu # changes (including switchCpus), you must resume the system 2905361Srstrong@cs.ucsd.edu # manually. You DON'T need to resume after just switching 2915361Srstrong@cs.ucsd.edu # CPUs if you haven't changed anything on the system level. 2923395Shsul@eecs.umich.edu 2933395Shsul@eecs.umich.edu m5.changeToTiming(testsys) 2943395Shsul@eecs.umich.edu m5.switchCpus(switch_cpu_list) 2953395Shsul@eecs.umich.edu m5.resume(testsys) 2963395Shsul@eecs.umich.edu 2973481Shsul@eecs.umich.edu if options.standard_switch: 2985361Srstrong@cs.ucsd.edu print "Switch at instruction count:%d" % \ 2995361Srstrong@cs.ucsd.edu (testsys.switch_cpus[0].max_insts_any_thread) 3005361Srstrong@cs.ucsd.edu 3015361Srstrong@cs.ucsd.edu #warmup instruction count may have already been set 3025361Srstrong@cs.ucsd.edu if options.warmup_insts: 3035361Srstrong@cs.ucsd.edu exit_event = m5.simulate() 3045361Srstrong@cs.ucsd.edu else: 3055353Svilas.sridharan@gmail.com exit_event = m5.simulate(options.warmup) 3067766Sgblack@eecs.umich.edu print "Switching CPUS @ tick %s" % (m5.curTick()) 3075361Srstrong@cs.ucsd.edu print "Simulation ends instruction count:%d" % \ 3085361Srstrong@cs.ucsd.edu (testsys.switch_cpus_1[0].max_insts_any_thread) 3095072Ssaidi@eecs.umich.edu m5.drain(testsys) 3103481Shsul@eecs.umich.edu m5.switchCpus(switch_cpu_list1) 3115072Ssaidi@eecs.umich.edu m5.resume(testsys) 3123395Shsul@eecs.umich.edu 3133395Shsul@eecs.umich.edu num_checkpoints = 0 3143395Shsul@eecs.umich.edu exit_cause = '' 3153395Shsul@eecs.umich.edu 3167489Ssteve.reinhardt@amd.com # If we're taking and restoring checkpoints, use checkpoint_dir 3177489Ssteve.reinhardt@amd.com # option only for finding the checkpoints to restore from. This 3187489Ssteve.reinhardt@amd.com # lets us test checkpointing by restoring from one set of 3197489Ssteve.reinhardt@amd.com # checkpoints, generating a second set, and then comparing them. 3207489Ssteve.reinhardt@amd.com if options.take_checkpoints and options.checkpoint_restore: 3217489Ssteve.reinhardt@amd.com if m5.options.outdir: 3227489Ssteve.reinhardt@amd.com cptdir = m5.options.outdir 3237489Ssteve.reinhardt@amd.com else: 3247489Ssteve.reinhardt@amd.com cptdir = getcwd() 3257489Ssteve.reinhardt@amd.com 3265361Srstrong@cs.ucsd.edu # Checkpoints being taken via the command line at <when> and at 3275361Srstrong@cs.ucsd.edu # subsequent periods of <period>. Checkpoint instructions 3285361Srstrong@cs.ucsd.edu # received from the benchmark running are ignored and skipped in 3295361Srstrong@cs.ucsd.edu # favor of command line checkpoint instructions. 3305369Ssaidi@eecs.umich.edu if options.take_checkpoints != None : 3315361Srstrong@cs.ucsd.edu if options.at_instruction or options.simpoint: 3325369Ssaidi@eecs.umich.edu checkpoint_inst = int(options.take_checkpoints) 3333395Shsul@eecs.umich.edu 3345361Srstrong@cs.ucsd.edu # maintain correct offset if we restored from some instruction 3355369Ssaidi@eecs.umich.edu if options.checkpoint_restore != None: 3365361Srstrong@cs.ucsd.edu checkpoint_inst += options.checkpoint_restore 3373395Shsul@eecs.umich.edu 3385361Srstrong@cs.ucsd.edu print "Creating checkpoint at inst:%d" % (checkpoint_inst) 3395361Srstrong@cs.ucsd.edu exit_event = m5.simulate() 3405361Srstrong@cs.ucsd.edu print "exit cause = %s" % (exit_event.getCause()) 3413395Shsul@eecs.umich.edu 3425361Srstrong@cs.ucsd.edu # skip checkpoint instructions should they exist 3435361Srstrong@cs.ucsd.edu while exit_event.getCause() == "checkpoint": 3445361Srstrong@cs.ucsd.edu exit_event = m5.simulate() 3453999Ssaidi@eecs.umich.edu 3465361Srstrong@cs.ucsd.edu if exit_event.getCause() == \ 3475361Srstrong@cs.ucsd.edu "a thread reached the max instruction count": 3487525Ssteve.reinhardt@amd.com m5.checkpoint(joinpath(cptdir, "cpt.%s.%d" % \ 3495361Srstrong@cs.ucsd.edu (options.bench, checkpoint_inst))) 3505361Srstrong@cs.ucsd.edu print "Checkpoint written." 3515361Srstrong@cs.ucsd.edu num_checkpoints += 1 3523999Ssaidi@eecs.umich.edu 3535361Srstrong@cs.ucsd.edu if exit_event.getCause() == "user interrupt received": 3545361Srstrong@cs.ucsd.edu exit_cause = exit_event.getCause(); 3555361Srstrong@cs.ucsd.edu else: 3565369Ssaidi@eecs.umich.edu when, period = options.take_checkpoints.split(",", 1) 3575369Ssaidi@eecs.umich.edu when = int(when) 3585369Ssaidi@eecs.umich.edu period = int(period) 3595369Ssaidi@eecs.umich.edu 3605361Srstrong@cs.ucsd.edu exit_event = m5.simulate(when) 3615361Srstrong@cs.ucsd.edu while exit_event.getCause() == "checkpoint": 3625361Srstrong@cs.ucsd.edu exit_event = m5.simulate(when - m5.curTick()) 3635361Srstrong@cs.ucsd.edu 3645361Srstrong@cs.ucsd.edu if exit_event.getCause() == "simulate() limit reached": 3657525Ssteve.reinhardt@amd.com m5.checkpoint(joinpath(cptdir, "cpt.%d")) 3665361Srstrong@cs.ucsd.edu num_checkpoints += 1 3675361Srstrong@cs.ucsd.edu 3685361Srstrong@cs.ucsd.edu sim_ticks = when 3695361Srstrong@cs.ucsd.edu exit_cause = "maximum %d checkpoints dropped" % max_checkpoints 3705361Srstrong@cs.ucsd.edu while num_checkpoints < max_checkpoints and \ 3715361Srstrong@cs.ucsd.edu exit_event.getCause() == "simulate() limit reached": 3725361Srstrong@cs.ucsd.edu if (sim_ticks + period) > maxtick: 3735361Srstrong@cs.ucsd.edu exit_event = m5.simulate(maxtick - sim_ticks) 3745361Srstrong@cs.ucsd.edu exit_cause = exit_event.getCause() 3755361Srstrong@cs.ucsd.edu break 3765361Srstrong@cs.ucsd.edu else: 3775361Srstrong@cs.ucsd.edu exit_event = m5.simulate(period) 3785361Srstrong@cs.ucsd.edu sim_ticks += period 3795361Srstrong@cs.ucsd.edu while exit_event.getCause() == "checkpoint": 3805361Srstrong@cs.ucsd.edu exit_event = m5.simulate(sim_ticks - m5.curTick()) 3815361Srstrong@cs.ucsd.edu if exit_event.getCause() == "simulate() limit reached": 3827525Ssteve.reinhardt@amd.com m5.checkpoint(joinpath(cptdir, "cpt.%d")) 3835361Srstrong@cs.ucsd.edu num_checkpoints += 1 3845361Srstrong@cs.ucsd.edu 3855361Srstrong@cs.ucsd.edu if exit_event.getCause() != "simulate() limit reached": 3865361Srstrong@cs.ucsd.edu exit_cause = exit_event.getCause(); 3875361Srstrong@cs.ucsd.edu 3885361Srstrong@cs.ucsd.edu else: # no checkpoints being taken via this script 3895361Srstrong@cs.ucsd.edu if options.fast_forward: 3905361Srstrong@cs.ucsd.edu m5.stats.reset() 3915361Srstrong@cs.ucsd.edu print "**** REAL SIMULATION ****" 3923395Shsul@eecs.umich.edu exit_event = m5.simulate(maxtick) 3933395Shsul@eecs.umich.edu 3943395Shsul@eecs.umich.edu while exit_event.getCause() == "checkpoint": 3957525Ssteve.reinhardt@amd.com m5.checkpoint(joinpath(cptdir, "cpt.%d")) 3963395Shsul@eecs.umich.edu num_checkpoints += 1 3973395Shsul@eecs.umich.edu if num_checkpoints == max_checkpoints: 3985361Srstrong@cs.ucsd.edu exit_cause = "maximum %d checkpoints dropped" % max_checkpoints 3993395Shsul@eecs.umich.edu break 4003395Shsul@eecs.umich.edu 4013511Shsul@eecs.umich.edu exit_event = m5.simulate(maxtick - m5.curTick()) 4023395Shsul@eecs.umich.edu exit_cause = exit_event.getCause() 4033395Shsul@eecs.umich.edu 4043395Shsul@eecs.umich.edu if exit_cause == '': 4053395Shsul@eecs.umich.edu exit_cause = exit_event.getCause() 4067766Sgblack@eecs.umich.edu print 'Exiting @ tick %i because %s' % (m5.curTick(), exit_cause) 4073395Shsul@eecs.umich.edu 4086776SBrad.Beckmann@amd.com if options.checkpoint_at_end: 4097525Ssteve.reinhardt@amd.com m5.checkpoint(joinpath(cptdir, "cpt.%d")) 4106776SBrad.Beckmann@amd.com 411