Simulation.py revision 8887
15347Ssaidi@eecs.umich.edu# Copyright (c) 2006-2008 The Regents of The University of Michigan 27534Ssteve.reinhardt@amd.com# Copyright (c) 2010 Advanced Micro Devices, Inc. 33395Shsul@eecs.umich.edu# All rights reserved. 43395Shsul@eecs.umich.edu# 53395Shsul@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 63395Shsul@eecs.umich.edu# modification, are permitted provided that the following conditions are 73395Shsul@eecs.umich.edu# met: redistributions of source code must retain the above copyright 83395Shsul@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 93395Shsul@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 103395Shsul@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 113395Shsul@eecs.umich.edu# documentation and/or other materials provided with the distribution; 123395Shsul@eecs.umich.edu# neither the name of the copyright holders nor the names of its 133395Shsul@eecs.umich.edu# contributors may be used to endorse or promote products derived from 143395Shsul@eecs.umich.edu# this software without specific prior written permission. 153395Shsul@eecs.umich.edu# 163395Shsul@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173395Shsul@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183395Shsul@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193395Shsul@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203395Shsul@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213395Shsul@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223395Shsul@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233395Shsul@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243395Shsul@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253395Shsul@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263395Shsul@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273395Shsul@eecs.umich.edu# 283395Shsul@eecs.umich.edu# Authors: Lisa Hsu 293395Shsul@eecs.umich.edu 303395Shsul@eecs.umich.edufrom os import getcwd 313509Shsul@eecs.umich.edufrom os.path import join as joinpath 326654Snate@binkert.org 333395Shsul@eecs.umich.eduimport m5 346654Snate@binkert.orgfrom m5.defines import buildEnv 353395Shsul@eecs.umich.edufrom m5.objects import * 366654Snate@binkert.orgfrom m5.util import * 378724Srdreslin@umich.edufrom O3_ARM_v7a import * 386654Snate@binkert.org 396654Snate@binkert.orgaddToPath('../common') 403395Shsul@eecs.umich.edu 413481Shsul@eecs.umich.edudef setCPUClass(options): 423481Shsul@eecs.umich.edu 433481Shsul@eecs.umich.edu atomic = False 448649Snilay@cs.wisc.edu if options.cpu_type == "timing": 455347Ssaidi@eecs.umich.edu class TmpClass(TimingSimpleCPU): pass 468724Srdreslin@umich.edu elif options.cpu_type == "detailed" or options.cpu_type == "arm_detailed": 478718Snilay@cs.wisc.edu if not options.caches and not options.ruby: 483681Sktlim@umich.edu print "O3 CPU must be used with caches" 493681Sktlim@umich.edu sys.exit(1) 508724Srdreslin@umich.edu if options.cpu_type == "arm_detailed": 518724Srdreslin@umich.edu class TmpClass(O3_ARM_v7a_3): pass 528724Srdreslin@umich.edu else: 538724Srdreslin@umich.edu class TmpClass(DerivO3CPU): pass 548649Snilay@cs.wisc.edu elif options.cpu_type == "inorder": 555869Sksewell@umich.edu if not options.caches: 565869Sksewell@umich.edu print "InOrder CPU must be used with caches" 575869Sksewell@umich.edu sys.exit(1) 585869Sksewell@umich.edu class TmpClass(InOrderCPU): pass 593481Shsul@eecs.umich.edu else: 605347Ssaidi@eecs.umich.edu class TmpClass(AtomicSimpleCPU): pass 613481Shsul@eecs.umich.edu atomic = True 623481Shsul@eecs.umich.edu 633481Shsul@eecs.umich.edu CPUClass = None 643481Shsul@eecs.umich.edu test_mem_mode = 'atomic' 653481Shsul@eecs.umich.edu 663481Shsul@eecs.umich.edu if not atomic: 678689Snilay@cs.wisc.edu if options.checkpoint_restore != None: 688689Snilay@cs.wisc.edu if options.restore_with_cpu != options.cpu_type: 698689Snilay@cs.wisc.edu CPUClass = TmpClass 708689Snilay@cs.wisc.edu class TmpClass(AtomicSimpleCPU): pass 718689Snilay@cs.wisc.edu else: 728689Snilay@cs.wisc.edu if options.restore_with_cpu != "atomic": 738689Snilay@cs.wisc.edu test_mem_mode = 'timing' 748689Snilay@cs.wisc.edu 758689Snilay@cs.wisc.edu elif options.fast_forward: 763481Shsul@eecs.umich.edu CPUClass = TmpClass 775347Ssaidi@eecs.umich.edu class TmpClass(AtomicSimpleCPU): pass 783481Shsul@eecs.umich.edu else: 793481Shsul@eecs.umich.edu test_mem_mode = 'timing' 803481Shsul@eecs.umich.edu 813481Shsul@eecs.umich.edu return (TmpClass, test_mem_mode, CPUClass) 823481Shsul@eecs.umich.edu 833481Shsul@eecs.umich.edu 843481Shsul@eecs.umich.edudef run(options, root, testsys, cpu_class): 853395Shsul@eecs.umich.edu if options.maxtick: 863395Shsul@eecs.umich.edu maxtick = options.maxtick 873395Shsul@eecs.umich.edu elif options.maxtime: 884167Sbinkertn@umich.edu simtime = m5.ticks.seconds(simtime) 893395Shsul@eecs.umich.edu print "simulating for: ", simtime 903395Shsul@eecs.umich.edu maxtick = simtime 913395Shsul@eecs.umich.edu else: 923511Shsul@eecs.umich.edu maxtick = m5.MaxTick 933395Shsul@eecs.umich.edu 943395Shsul@eecs.umich.edu if options.checkpoint_dir: 953395Shsul@eecs.umich.edu cptdir = options.checkpoint_dir 965211Ssaidi@eecs.umich.edu elif m5.options.outdir: 975211Ssaidi@eecs.umich.edu cptdir = m5.options.outdir 983395Shsul@eecs.umich.edu else: 993395Shsul@eecs.umich.edu cptdir = getcwd() 1003395Shsul@eecs.umich.edu 1015370Ssaidi@eecs.umich.edu if options.fast_forward and options.checkpoint_restore != None: 1026654Snate@binkert.org fatal("Can't specify both --fast-forward and --checkpoint-restore") 1035370Ssaidi@eecs.umich.edu 1045371Shsul@eecs.umich.edu if options.standard_switch and not options.caches: 1056654Snate@binkert.org fatal("Must specify --caches when using --standard-switch") 1065370Ssaidi@eecs.umich.edu 1073395Shsul@eecs.umich.edu np = options.num_cpus 1083395Shsul@eecs.umich.edu max_checkpoints = options.max_checkpoints 1093481Shsul@eecs.umich.edu switch_cpus = None 1103481Shsul@eecs.umich.edu 1118318Sksewell@umich.edu if options.prog_interval: 1126144Sksewell@umich.edu for i in xrange(np): 1138311Sksewell@umich.edu testsys.cpu[i].progress_interval = options.prog_interval 1146144Sksewell@umich.edu 1156641Sksewell@umich.edu if options.maxinsts: 1166641Sksewell@umich.edu for i in xrange(np): 1176641Sksewell@umich.edu testsys.cpu[i].max_insts_any_thread = options.maxinsts 1186641Sksewell@umich.edu 1193481Shsul@eecs.umich.edu if cpu_class: 1203481Shsul@eecs.umich.edu switch_cpus = [cpu_class(defer_registration=True, cpu_id=(np+i)) 1213481Shsul@eecs.umich.edu for i in xrange(np)] 1223481Shsul@eecs.umich.edu 1233481Shsul@eecs.umich.edu for i in xrange(np): 1245361Srstrong@cs.ucsd.edu if options.fast_forward: 1255369Ssaidi@eecs.umich.edu testsys.cpu[i].max_insts_any_thread = int(options.fast_forward) 1263481Shsul@eecs.umich.edu switch_cpus[i].system = testsys 1278803Sgblack@eecs.umich.edu switch_cpus[i].workload = testsys.cpu[i].workload 1283481Shsul@eecs.umich.edu switch_cpus[i].clock = testsys.cpu[0].clock 1295369Ssaidi@eecs.umich.edu # simulation period 1308311Sksewell@umich.edu if options.maxinsts: 1318311Sksewell@umich.edu switch_cpus[i].max_insts_any_thread = options.maxinsts 1328887Sgeoffrey.blake@arm.com # Add checker cpu if selected 1338887Sgeoffrey.blake@arm.com if options.checker: 1348887Sgeoffrey.blake@arm.com switch_cpus[i].addCheckerCpu() 1353481Shsul@eecs.umich.edu 1365311Ssaidi@eecs.umich.edu testsys.switch_cpus = switch_cpus 1373481Shsul@eecs.umich.edu switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] 1383395Shsul@eecs.umich.edu 1393395Shsul@eecs.umich.edu if options.standard_switch: 1408211Satgutier@umich.edu if not options.caches: 1418211Satgutier@umich.edu # O3 CPU must have a cache to work. 1428211Satgutier@umich.edu print "O3 CPU must be used with caches" 1438211Satgutier@umich.edu sys.exit(1) 1448211Satgutier@umich.edu 1453395Shsul@eecs.umich.edu switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(np+i)) 1463395Shsul@eecs.umich.edu for i in xrange(np)] 1473478Shsul@eecs.umich.edu switch_cpus_1 = [DerivO3CPU(defer_registration=True, cpu_id=(2*np+i)) 1483395Shsul@eecs.umich.edu for i in xrange(np)] 1493478Shsul@eecs.umich.edu 1503395Shsul@eecs.umich.edu for i in xrange(np): 1513395Shsul@eecs.umich.edu switch_cpus[i].system = testsys 1523478Shsul@eecs.umich.edu switch_cpus_1[i].system = testsys 1538803Sgblack@eecs.umich.edu switch_cpus[i].workload = testsys.cpu[i].workload 1548803Sgblack@eecs.umich.edu switch_cpus_1[i].workload = testsys.cpu[i].workload 1553395Shsul@eecs.umich.edu switch_cpus[i].clock = testsys.cpu[0].clock 1563478Shsul@eecs.umich.edu switch_cpus_1[i].clock = testsys.cpu[0].clock 1573480Shsul@eecs.umich.edu 1585361Srstrong@cs.ucsd.edu # if restoring, make atomic cpu simulate only a few instructions 1595369Ssaidi@eecs.umich.edu if options.checkpoint_restore != None: 1605361Srstrong@cs.ucsd.edu testsys.cpu[i].max_insts_any_thread = 1 1615361Srstrong@cs.ucsd.edu # Fast forward to specified location if we are not restoring 1625361Srstrong@cs.ucsd.edu elif options.fast_forward: 1635369Ssaidi@eecs.umich.edu testsys.cpu[i].max_insts_any_thread = int(options.fast_forward) 1645361Srstrong@cs.ucsd.edu # Fast forward to a simpoint (warning: time consuming) 1655361Srstrong@cs.ucsd.edu elif options.simpoint: 1665378Ssaidi@eecs.umich.edu if testsys.cpu[i].workload[0].simpoint == 0: 1676654Snate@binkert.org fatal('simpoint not found') 1685361Srstrong@cs.ucsd.edu testsys.cpu[i].max_insts_any_thread = \ 1695361Srstrong@cs.ucsd.edu testsys.cpu[i].workload[0].simpoint 1705361Srstrong@cs.ucsd.edu # No distance specified, just switch 1715361Srstrong@cs.ucsd.edu else: 1725361Srstrong@cs.ucsd.edu testsys.cpu[i].max_insts_any_thread = 1 1735361Srstrong@cs.ucsd.edu 1745361Srstrong@cs.ucsd.edu # warmup period 1755361Srstrong@cs.ucsd.edu if options.warmup_insts: 1765361Srstrong@cs.ucsd.edu switch_cpus[i].max_insts_any_thread = options.warmup_insts 1775361Srstrong@cs.ucsd.edu 1785361Srstrong@cs.ucsd.edu # simulation period 1798311Sksewell@umich.edu if options.maxinsts: 1808311Sksewell@umich.edu switch_cpus_1[i].max_insts_any_thread = options.maxinsts 1815353Svilas.sridharan@gmail.com 1828887Sgeoffrey.blake@arm.com # attach the checker cpu if selected 1838887Sgeoffrey.blake@arm.com if options.checker: 1848887Sgeoffrey.blake@arm.com switch_cpus[i].addCheckerCpu() 1858887Sgeoffrey.blake@arm.com switch_cpus_1[i].addCheckerCpu() 1868887Sgeoffrey.blake@arm.com 1878211Satgutier@umich.edu testsys.switch_cpus = switch_cpus 1888211Satgutier@umich.edu testsys.switch_cpus_1 = switch_cpus_1 1898211Satgutier@umich.edu switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] 1908211Satgutier@umich.edu switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)] 1913395Shsul@eecs.umich.edu 1925361Srstrong@cs.ucsd.edu # set the checkpoint in the cpu before m5.instantiate is called 1935369Ssaidi@eecs.umich.edu if options.take_checkpoints != None and \ 1945361Srstrong@cs.ucsd.edu (options.simpoint or options.at_instruction): 1955361Srstrong@cs.ucsd.edu offset = int(options.take_checkpoints) 1965361Srstrong@cs.ucsd.edu # Set an instruction break point 1975361Srstrong@cs.ucsd.edu if options.simpoint: 1985361Srstrong@cs.ucsd.edu for i in xrange(np): 1995378Ssaidi@eecs.umich.edu if testsys.cpu[i].workload[0].simpoint == 0: 2006654Snate@binkert.org fatal('no simpoint for testsys.cpu[%d].workload[0]', i) 2015369Ssaidi@eecs.umich.edu checkpoint_inst = int(testsys.cpu[i].workload[0].simpoint) + offset 2025361Srstrong@cs.ucsd.edu testsys.cpu[i].max_insts_any_thread = checkpoint_inst 2035361Srstrong@cs.ucsd.edu # used for output below 2045361Srstrong@cs.ucsd.edu options.take_checkpoints = checkpoint_inst 2055361Srstrong@cs.ucsd.edu else: 2065361Srstrong@cs.ucsd.edu options.take_checkpoints = offset 2075361Srstrong@cs.ucsd.edu # Set all test cpus with the right number of instructions 2085361Srstrong@cs.ucsd.edu # for the upcoming simulation 2095361Srstrong@cs.ucsd.edu for i in xrange(np): 2105361Srstrong@cs.ucsd.edu testsys.cpu[i].max_insts_any_thread = offset 2115361Srstrong@cs.ucsd.edu 2127531Ssteve.reinhardt@amd.com checkpoint_dir = None 2135369Ssaidi@eecs.umich.edu if options.checkpoint_restore != None: 2145361Srstrong@cs.ucsd.edu from os.path import isdir, exists 2153395Shsul@eecs.umich.edu from os import listdir 2163395Shsul@eecs.umich.edu import re 2173395Shsul@eecs.umich.edu 2183395Shsul@eecs.umich.edu if not isdir(cptdir): 2196654Snate@binkert.org fatal("checkpoint dir %s does not exist!", cptdir) 2203395Shsul@eecs.umich.edu 2217530Ssteve.reinhardt@amd.com if options.at_instruction or options.simpoint: 2227530Ssteve.reinhardt@amd.com inst = options.checkpoint_restore 2237530Ssteve.reinhardt@amd.com if options.simpoint: 2247530Ssteve.reinhardt@amd.com # assume workload 0 has the simpoint 2257530Ssteve.reinhardt@amd.com if testsys.cpu[0].workload[0].simpoint == 0: 2267530Ssteve.reinhardt@amd.com fatal('Unable to find simpoint') 2277530Ssteve.reinhardt@amd.com inst += int(testsys.cpu[0].workload[0].simpoint) 2287530Ssteve.reinhardt@amd.com 2297530Ssteve.reinhardt@amd.com checkpoint_dir = joinpath(cptdir, 2307530Ssteve.reinhardt@amd.com "cpt.%s.%s" % (options.bench, inst)) 2315361Srstrong@cs.ucsd.edu if not exists(checkpoint_dir): 2326654Snate@binkert.org fatal("Unable to find checkpoint directory %s", checkpoint_dir) 2335361Srstrong@cs.ucsd.edu else: 2345361Srstrong@cs.ucsd.edu dirs = listdir(cptdir) 2355361Srstrong@cs.ucsd.edu expr = re.compile('cpt\.([0-9]*)') 2365361Srstrong@cs.ucsd.edu cpts = [] 2375361Srstrong@cs.ucsd.edu for dir in dirs: 2385361Srstrong@cs.ucsd.edu match = expr.match(dir) 2395361Srstrong@cs.ucsd.edu if match: 2405361Srstrong@cs.ucsd.edu cpts.append(match.group(1)) 2413999Ssaidi@eecs.umich.edu 2425361Srstrong@cs.ucsd.edu cpts.sort(lambda a,b: cmp(long(a), long(b))) 2435361Srstrong@cs.ucsd.edu 2445361Srstrong@cs.ucsd.edu cpt_num = options.checkpoint_restore 2455361Srstrong@cs.ucsd.edu 2465361Srstrong@cs.ucsd.edu if cpt_num > len(cpts): 2476654Snate@binkert.org fatal('Checkpoint %d not found', cpt_num) 2485361Srstrong@cs.ucsd.edu 2495361Srstrong@cs.ucsd.edu ## Adjust max tick based on our starting tick 2505361Srstrong@cs.ucsd.edu maxtick = maxtick - int(cpts[cpt_num - 1]) 2517531Ssteve.reinhardt@amd.com checkpoint_dir = joinpath(cptdir, "cpt.%s" % cpts[cpt_num - 1]) 2525361Srstrong@cs.ucsd.edu 2537531Ssteve.reinhardt@amd.com m5.instantiate(checkpoint_dir) 2543395Shsul@eecs.umich.edu 2553481Shsul@eecs.umich.edu if options.standard_switch or cpu_class: 2565361Srstrong@cs.ucsd.edu if options.standard_switch: 2575361Srstrong@cs.ucsd.edu print "Switch at instruction count:%s" % \ 2585361Srstrong@cs.ucsd.edu str(testsys.cpu[0].max_insts_any_thread) 2595361Srstrong@cs.ucsd.edu exit_event = m5.simulate() 2605361Srstrong@cs.ucsd.edu elif cpu_class and options.fast_forward: 2615361Srstrong@cs.ucsd.edu print "Switch at instruction count:%s" % \ 2625361Srstrong@cs.ucsd.edu str(testsys.cpu[0].max_insts_any_thread) 2635361Srstrong@cs.ucsd.edu exit_event = m5.simulate() 2645361Srstrong@cs.ucsd.edu else: 2655361Srstrong@cs.ucsd.edu print "Switch at curTick count:%s" % str(10000) 2665361Srstrong@cs.ucsd.edu exit_event = m5.simulate(10000) 2677766Sgblack@eecs.umich.edu print "Switched CPUS @ tick %s" % (m5.curTick()) 2683395Shsul@eecs.umich.edu 2695361Srstrong@cs.ucsd.edu # when you change to Timing (or Atomic), you halt the system 2705361Srstrong@cs.ucsd.edu # given as argument. When you are finished with the system 2715361Srstrong@cs.ucsd.edu # changes (including switchCpus), you must resume the system 2725361Srstrong@cs.ucsd.edu # manually. You DON'T need to resume after just switching 2735361Srstrong@cs.ucsd.edu # CPUs if you haven't changed anything on the system level. 2743395Shsul@eecs.umich.edu 2753395Shsul@eecs.umich.edu m5.changeToTiming(testsys) 2763395Shsul@eecs.umich.edu m5.switchCpus(switch_cpu_list) 2773395Shsul@eecs.umich.edu m5.resume(testsys) 2783395Shsul@eecs.umich.edu 2793481Shsul@eecs.umich.edu if options.standard_switch: 2805361Srstrong@cs.ucsd.edu print "Switch at instruction count:%d" % \ 2815361Srstrong@cs.ucsd.edu (testsys.switch_cpus[0].max_insts_any_thread) 2825361Srstrong@cs.ucsd.edu 2835361Srstrong@cs.ucsd.edu #warmup instruction count may have already been set 2845361Srstrong@cs.ucsd.edu if options.warmup_insts: 2855361Srstrong@cs.ucsd.edu exit_event = m5.simulate() 2865361Srstrong@cs.ucsd.edu else: 2875353Svilas.sridharan@gmail.com exit_event = m5.simulate(options.warmup) 2887766Sgblack@eecs.umich.edu print "Switching CPUS @ tick %s" % (m5.curTick()) 2895361Srstrong@cs.ucsd.edu print "Simulation ends instruction count:%d" % \ 2905361Srstrong@cs.ucsd.edu (testsys.switch_cpus_1[0].max_insts_any_thread) 2915072Ssaidi@eecs.umich.edu m5.drain(testsys) 2923481Shsul@eecs.umich.edu m5.switchCpus(switch_cpu_list1) 2935072Ssaidi@eecs.umich.edu m5.resume(testsys) 2943395Shsul@eecs.umich.edu 2953395Shsul@eecs.umich.edu num_checkpoints = 0 2963395Shsul@eecs.umich.edu exit_cause = '' 2973395Shsul@eecs.umich.edu 2987489Ssteve.reinhardt@amd.com # If we're taking and restoring checkpoints, use checkpoint_dir 2997489Ssteve.reinhardt@amd.com # option only for finding the checkpoints to restore from. This 3007489Ssteve.reinhardt@amd.com # lets us test checkpointing by restoring from one set of 3017489Ssteve.reinhardt@amd.com # checkpoints, generating a second set, and then comparing them. 3027489Ssteve.reinhardt@amd.com if options.take_checkpoints and options.checkpoint_restore: 3037489Ssteve.reinhardt@amd.com if m5.options.outdir: 3047489Ssteve.reinhardt@amd.com cptdir = m5.options.outdir 3057489Ssteve.reinhardt@amd.com else: 3067489Ssteve.reinhardt@amd.com cptdir = getcwd() 3077489Ssteve.reinhardt@amd.com 3085361Srstrong@cs.ucsd.edu # Checkpoints being taken via the command line at <when> and at 3095361Srstrong@cs.ucsd.edu # subsequent periods of <period>. Checkpoint instructions 3105361Srstrong@cs.ucsd.edu # received from the benchmark running are ignored and skipped in 3115361Srstrong@cs.ucsd.edu # favor of command line checkpoint instructions. 3125369Ssaidi@eecs.umich.edu if options.take_checkpoints != None : 3135361Srstrong@cs.ucsd.edu if options.at_instruction or options.simpoint: 3145369Ssaidi@eecs.umich.edu checkpoint_inst = int(options.take_checkpoints) 3153395Shsul@eecs.umich.edu 3165361Srstrong@cs.ucsd.edu # maintain correct offset if we restored from some instruction 3175369Ssaidi@eecs.umich.edu if options.checkpoint_restore != None: 3185361Srstrong@cs.ucsd.edu checkpoint_inst += options.checkpoint_restore 3193395Shsul@eecs.umich.edu 3205361Srstrong@cs.ucsd.edu print "Creating checkpoint at inst:%d" % (checkpoint_inst) 3215361Srstrong@cs.ucsd.edu exit_event = m5.simulate() 3225361Srstrong@cs.ucsd.edu print "exit cause = %s" % (exit_event.getCause()) 3233395Shsul@eecs.umich.edu 3245361Srstrong@cs.ucsd.edu # skip checkpoint instructions should they exist 3255361Srstrong@cs.ucsd.edu while exit_event.getCause() == "checkpoint": 3265361Srstrong@cs.ucsd.edu exit_event = m5.simulate() 3273999Ssaidi@eecs.umich.edu 3285361Srstrong@cs.ucsd.edu if exit_event.getCause() == \ 3295361Srstrong@cs.ucsd.edu "a thread reached the max instruction count": 3307525Ssteve.reinhardt@amd.com m5.checkpoint(joinpath(cptdir, "cpt.%s.%d" % \ 3315361Srstrong@cs.ucsd.edu (options.bench, checkpoint_inst))) 3325361Srstrong@cs.ucsd.edu print "Checkpoint written." 3335361Srstrong@cs.ucsd.edu num_checkpoints += 1 3343999Ssaidi@eecs.umich.edu 3355361Srstrong@cs.ucsd.edu if exit_event.getCause() == "user interrupt received": 3365361Srstrong@cs.ucsd.edu exit_cause = exit_event.getCause(); 3375361Srstrong@cs.ucsd.edu else: 3385369Ssaidi@eecs.umich.edu when, period = options.take_checkpoints.split(",", 1) 3395369Ssaidi@eecs.umich.edu when = int(when) 3405369Ssaidi@eecs.umich.edu period = int(period) 3415369Ssaidi@eecs.umich.edu 3425361Srstrong@cs.ucsd.edu exit_event = m5.simulate(when) 3435361Srstrong@cs.ucsd.edu while exit_event.getCause() == "checkpoint": 3445361Srstrong@cs.ucsd.edu exit_event = m5.simulate(when - m5.curTick()) 3455361Srstrong@cs.ucsd.edu 3465361Srstrong@cs.ucsd.edu if exit_event.getCause() == "simulate() limit reached": 3477525Ssteve.reinhardt@amd.com m5.checkpoint(joinpath(cptdir, "cpt.%d")) 3485361Srstrong@cs.ucsd.edu num_checkpoints += 1 3495361Srstrong@cs.ucsd.edu 3505361Srstrong@cs.ucsd.edu sim_ticks = when 3515361Srstrong@cs.ucsd.edu exit_cause = "maximum %d checkpoints dropped" % max_checkpoints 3525361Srstrong@cs.ucsd.edu while num_checkpoints < max_checkpoints and \ 3535361Srstrong@cs.ucsd.edu exit_event.getCause() == "simulate() limit reached": 3545361Srstrong@cs.ucsd.edu if (sim_ticks + period) > maxtick: 3555361Srstrong@cs.ucsd.edu exit_event = m5.simulate(maxtick - sim_ticks) 3565361Srstrong@cs.ucsd.edu exit_cause = exit_event.getCause() 3575361Srstrong@cs.ucsd.edu break 3585361Srstrong@cs.ucsd.edu else: 3595361Srstrong@cs.ucsd.edu exit_event = m5.simulate(period) 3605361Srstrong@cs.ucsd.edu sim_ticks += period 3615361Srstrong@cs.ucsd.edu while exit_event.getCause() == "checkpoint": 3625361Srstrong@cs.ucsd.edu exit_event = m5.simulate(sim_ticks - m5.curTick()) 3635361Srstrong@cs.ucsd.edu if exit_event.getCause() == "simulate() limit reached": 3647525Ssteve.reinhardt@amd.com m5.checkpoint(joinpath(cptdir, "cpt.%d")) 3655361Srstrong@cs.ucsd.edu num_checkpoints += 1 3665361Srstrong@cs.ucsd.edu 3675361Srstrong@cs.ucsd.edu if exit_event.getCause() != "simulate() limit reached": 3685361Srstrong@cs.ucsd.edu exit_cause = exit_event.getCause(); 3695361Srstrong@cs.ucsd.edu 3705361Srstrong@cs.ucsd.edu else: # no checkpoints being taken via this script 3715361Srstrong@cs.ucsd.edu if options.fast_forward: 3725361Srstrong@cs.ucsd.edu m5.stats.reset() 3735361Srstrong@cs.ucsd.edu print "**** REAL SIMULATION ****" 3743395Shsul@eecs.umich.edu exit_event = m5.simulate(maxtick) 3753395Shsul@eecs.umich.edu 3763395Shsul@eecs.umich.edu while exit_event.getCause() == "checkpoint": 3777525Ssteve.reinhardt@amd.com m5.checkpoint(joinpath(cptdir, "cpt.%d")) 3783395Shsul@eecs.umich.edu num_checkpoints += 1 3793395Shsul@eecs.umich.edu if num_checkpoints == max_checkpoints: 3805361Srstrong@cs.ucsd.edu exit_cause = "maximum %d checkpoints dropped" % max_checkpoints 3813395Shsul@eecs.umich.edu break 3823395Shsul@eecs.umich.edu 3833511Shsul@eecs.umich.edu exit_event = m5.simulate(maxtick - m5.curTick()) 3843395Shsul@eecs.umich.edu exit_cause = exit_event.getCause() 3853395Shsul@eecs.umich.edu 3863395Shsul@eecs.umich.edu if exit_cause == '': 3873395Shsul@eecs.umich.edu exit_cause = exit_event.getCause() 3887766Sgblack@eecs.umich.edu print 'Exiting @ tick %i because %s' % (m5.curTick(), exit_cause) 3893395Shsul@eecs.umich.edu 3906776SBrad.Beckmann@amd.com if options.checkpoint_at_end: 3917525Ssteve.reinhardt@amd.com m5.checkpoint(joinpath(cptdir, "cpt.%d")) 3926776SBrad.Beckmann@amd.com 393