Simulation.py revision 5072
13999Ssaidi@eecs.umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan
23395Shsul@eecs.umich.edu# All rights reserved.
33395Shsul@eecs.umich.edu#
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63395Shsul@eecs.umich.edu# met: redistributions of source code must retain the above copyright
73395Shsul@eecs.umich.edu# notice, this list of conditions and the following disclaimer;
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273395Shsul@eecs.umich.edu# Authors: Lisa Hsu
283395Shsul@eecs.umich.edu
293395Shsul@eecs.umich.edufrom os import getcwd
303509Shsul@eecs.umich.edufrom os.path import join as joinpath
313395Shsul@eecs.umich.eduimport m5
323395Shsul@eecs.umich.edufrom m5.objects import *
333395Shsul@eecs.umich.edum5.AddToPath('../common')
343448Shsul@eecs.umich.edufrom Caches import L1Cache
353395Shsul@eecs.umich.edu
363481Shsul@eecs.umich.edudef setCPUClass(options):
373481Shsul@eecs.umich.edu
383481Shsul@eecs.umich.edu    atomic = False
393481Shsul@eecs.umich.edu    if options.timing:
403481Shsul@eecs.umich.edu        TmpClass = TimingSimpleCPU
413481Shsul@eecs.umich.edu    elif options.detailed:
423681Sktlim@umich.edu        if not options.caches:
433681Sktlim@umich.edu            print "O3 CPU must be used with caches"
443681Sktlim@umich.edu            sys.exit(1)
453481Shsul@eecs.umich.edu        TmpClass = DerivO3CPU
463481Shsul@eecs.umich.edu    else:
473481Shsul@eecs.umich.edu        TmpClass = AtomicSimpleCPU
483481Shsul@eecs.umich.edu        atomic = True
493481Shsul@eecs.umich.edu
503481Shsul@eecs.umich.edu    CPUClass = None
513481Shsul@eecs.umich.edu    test_mem_mode = 'atomic'
523481Shsul@eecs.umich.edu
533481Shsul@eecs.umich.edu    if not atomic:
543481Shsul@eecs.umich.edu        if options.checkpoint_restore:
553481Shsul@eecs.umich.edu            CPUClass = TmpClass
563481Shsul@eecs.umich.edu            TmpClass = AtomicSimpleCPU
573481Shsul@eecs.umich.edu        else:
583481Shsul@eecs.umich.edu            test_mem_mode = 'timing'
593481Shsul@eecs.umich.edu
603481Shsul@eecs.umich.edu    return (TmpClass, test_mem_mode, CPUClass)
613481Shsul@eecs.umich.edu
623481Shsul@eecs.umich.edu
633481Shsul@eecs.umich.edudef run(options, root, testsys, cpu_class):
643395Shsul@eecs.umich.edu    if options.maxtick:
653395Shsul@eecs.umich.edu        maxtick = options.maxtick
663395Shsul@eecs.umich.edu    elif options.maxtime:
674167Sbinkertn@umich.edu        simtime = m5.ticks.seconds(simtime)
683395Shsul@eecs.umich.edu        print "simulating for: ", simtime
693395Shsul@eecs.umich.edu        maxtick = simtime
703395Shsul@eecs.umich.edu    else:
713511Shsul@eecs.umich.edu        maxtick = m5.MaxTick
723395Shsul@eecs.umich.edu
733395Shsul@eecs.umich.edu    if options.checkpoint_dir:
743395Shsul@eecs.umich.edu        cptdir = options.checkpoint_dir
753395Shsul@eecs.umich.edu    else:
763395Shsul@eecs.umich.edu        cptdir = getcwd()
773395Shsul@eecs.umich.edu
783395Shsul@eecs.umich.edu    np = options.num_cpus
793395Shsul@eecs.umich.edu    max_checkpoints = options.max_checkpoints
803481Shsul@eecs.umich.edu    switch_cpus = None
813481Shsul@eecs.umich.edu
823481Shsul@eecs.umich.edu    if cpu_class:
833481Shsul@eecs.umich.edu        switch_cpus = [cpu_class(defer_registration=True, cpu_id=(np+i))
843481Shsul@eecs.umich.edu                       for i in xrange(np)]
853481Shsul@eecs.umich.edu
863481Shsul@eecs.umich.edu        for i in xrange(np):
873481Shsul@eecs.umich.edu            switch_cpus[i].system =  testsys
883481Shsul@eecs.umich.edu            if not m5.build_env['FULL_SYSTEM']:
893481Shsul@eecs.umich.edu                switch_cpus[i].workload = testsys.cpu[i].workload
903481Shsul@eecs.umich.edu            switch_cpus[i].clock = testsys.cpu[0].clock
913481Shsul@eecs.umich.edu
923481Shsul@eecs.umich.edu        root.switch_cpus = switch_cpus
933481Shsul@eecs.umich.edu        switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
943395Shsul@eecs.umich.edu
953395Shsul@eecs.umich.edu    if options.standard_switch:
963395Shsul@eecs.umich.edu        switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(np+i))
973395Shsul@eecs.umich.edu                       for i in xrange(np)]
983478Shsul@eecs.umich.edu        switch_cpus_1 = [DerivO3CPU(defer_registration=True, cpu_id=(2*np+i))
993395Shsul@eecs.umich.edu                        for i in xrange(np)]
1003478Shsul@eecs.umich.edu
1013395Shsul@eecs.umich.edu        for i in xrange(np):
1023395Shsul@eecs.umich.edu            switch_cpus[i].system =  testsys
1033478Shsul@eecs.umich.edu            switch_cpus_1[i].system =  testsys
1043395Shsul@eecs.umich.edu            if not m5.build_env['FULL_SYSTEM']:
1053395Shsul@eecs.umich.edu                switch_cpus[i].workload = testsys.cpu[i].workload
1063478Shsul@eecs.umich.edu                switch_cpus_1[i].workload = testsys.cpu[i].workload
1073395Shsul@eecs.umich.edu            switch_cpus[i].clock = testsys.cpu[0].clock
1083478Shsul@eecs.umich.edu            switch_cpus_1[i].clock = testsys.cpu[0].clock
1093480Shsul@eecs.umich.edu
1103514Sktlim@umich.edu            if not options.caches:
1113481Shsul@eecs.umich.edu                # O3 CPU must have a cache to work.
1123480Shsul@eecs.umich.edu                switch_cpus_1[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
1133480Shsul@eecs.umich.edu                                                         L1Cache(size = '64kB'))
1143480Shsul@eecs.umich.edu                switch_cpus_1[i].connectMemPorts(testsys.membus)
1153395Shsul@eecs.umich.edu
1163478Shsul@eecs.umich.edu
1173514Sktlim@umich.edu            testsys.switch_cpus = switch_cpus
1183514Sktlim@umich.edu            testsys.switch_cpus_1 = switch_cpus_1
1193395Shsul@eecs.umich.edu            switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
1203478Shsul@eecs.umich.edu            switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)]
1213395Shsul@eecs.umich.edu
1223395Shsul@eecs.umich.edu    m5.instantiate(root)
1233395Shsul@eecs.umich.edu
1243395Shsul@eecs.umich.edu    if options.checkpoint_restore:
1253395Shsul@eecs.umich.edu        from os.path import isdir
1263395Shsul@eecs.umich.edu        from os import listdir
1273395Shsul@eecs.umich.edu        import re
1283395Shsul@eecs.umich.edu
1293395Shsul@eecs.umich.edu        if not isdir(cptdir):
1303395Shsul@eecs.umich.edu            m5.panic("checkpoint dir %s does not exist!" % cptdir)
1313395Shsul@eecs.umich.edu
1323395Shsul@eecs.umich.edu        dirs = listdir(cptdir)
1333395Shsul@eecs.umich.edu        expr = re.compile('cpt.([0-9]*)')
1343395Shsul@eecs.umich.edu        cpts = []
1353395Shsul@eecs.umich.edu        for dir in dirs:
1363395Shsul@eecs.umich.edu            match = expr.match(dir)
1373395Shsul@eecs.umich.edu            if match:
1383395Shsul@eecs.umich.edu                cpts.append(match.group(1))
1393395Shsul@eecs.umich.edu
1403395Shsul@eecs.umich.edu        cpts.sort(lambda a,b: cmp(long(a), long(b)))
1413395Shsul@eecs.umich.edu
1423395Shsul@eecs.umich.edu        cpt_num = options.checkpoint_restore
1433395Shsul@eecs.umich.edu
1443395Shsul@eecs.umich.edu        if cpt_num > len(cpts):
1453395Shsul@eecs.umich.edu            m5.panic('Checkpoint %d not found' % cpt_num)
1463395Shsul@eecs.umich.edu
1473999Ssaidi@eecs.umich.edu        ## Adjust max tick based on our starting tick
1483999Ssaidi@eecs.umich.edu        maxtick = maxtick - int(cpts[cpt_num - 1])
1493999Ssaidi@eecs.umich.edu
1503999Ssaidi@eecs.umich.edu        ## Restore the checkpoint
1513395Shsul@eecs.umich.edu        m5.restoreCheckpoint(root,
1523509Shsul@eecs.umich.edu                             joinpath(cptdir, "cpt.%s" % cpts[cpt_num - 1]))
1533395Shsul@eecs.umich.edu
1543481Shsul@eecs.umich.edu    if options.standard_switch or cpu_class:
1553395Shsul@eecs.umich.edu        exit_event = m5.simulate(10000)
1563395Shsul@eecs.umich.edu
1573395Shsul@eecs.umich.edu        ## when you change to Timing (or Atomic), you halt the system given
1583395Shsul@eecs.umich.edu        ## as argument.  When you are finished with the system changes
1593395Shsul@eecs.umich.edu        ## (including switchCpus), you must resume the system manually.
1603395Shsul@eecs.umich.edu        ## You DON'T need to resume after just switching CPUs if you haven't
1613395Shsul@eecs.umich.edu        ## changed anything on the system level.
1623395Shsul@eecs.umich.edu
1633395Shsul@eecs.umich.edu        m5.changeToTiming(testsys)
1643395Shsul@eecs.umich.edu        m5.switchCpus(switch_cpu_list)
1653395Shsul@eecs.umich.edu        m5.resume(testsys)
1663395Shsul@eecs.umich.edu
1673481Shsul@eecs.umich.edu        if options.standard_switch:
1683481Shsul@eecs.umich.edu            exit_event = m5.simulate(options.warmup)
1695072Ssaidi@eecs.umich.edu            m5.drain(testsys)
1703481Shsul@eecs.umich.edu            m5.switchCpus(switch_cpu_list1)
1715072Ssaidi@eecs.umich.edu            m5.resume(testsys)
1723395Shsul@eecs.umich.edu
1733395Shsul@eecs.umich.edu    num_checkpoints = 0
1743395Shsul@eecs.umich.edu    exit_cause = ''
1753395Shsul@eecs.umich.edu
1763410Shsul@eecs.umich.edu    ## Checkpoints being taken via the command line at <when> and at subsequent
1773410Shsul@eecs.umich.edu    ## periods of <period>.  Checkpoint instructions received from the benchmark running
1783410Shsul@eecs.umich.edu    ## are ignored and skipped in favor of command line checkpoint instructions.
1793395Shsul@eecs.umich.edu    if options.take_checkpoints:
1803395Shsul@eecs.umich.edu        [when, period] = options.take_checkpoints.split(",", 1)
1813395Shsul@eecs.umich.edu        when = int(when)
1823395Shsul@eecs.umich.edu        period = int(period)
1833395Shsul@eecs.umich.edu
1843395Shsul@eecs.umich.edu        exit_event = m5.simulate(when)
1853395Shsul@eecs.umich.edu        while exit_event.getCause() == "checkpoint":
1863395Shsul@eecs.umich.edu            exit_event = m5.simulate(when - m5.curTick())
1873395Shsul@eecs.umich.edu
1883395Shsul@eecs.umich.edu        if exit_event.getCause() == "simulate() limit reached":
1893509Shsul@eecs.umich.edu            m5.checkpoint(root, joinpath(cptdir, "cpt.%d"))
1903395Shsul@eecs.umich.edu            num_checkpoints += 1
1913395Shsul@eecs.umich.edu
1923395Shsul@eecs.umich.edu        sim_ticks = when
1933395Shsul@eecs.umich.edu        exit_cause = "maximum %d checkpoints dropped" % max_checkpoints
1943999Ssaidi@eecs.umich.edu        while num_checkpoints < max_checkpoints and \
1953999Ssaidi@eecs.umich.edu                exit_event.getCause() != "user interrupt received":
1963511Shsul@eecs.umich.edu            if (sim_ticks + period) > maxtick:
1973395Shsul@eecs.umich.edu                exit_event = m5.simulate(maxtick - sim_ticks)
1983395Shsul@eecs.umich.edu                exit_cause = exit_event.getCause()
1993395Shsul@eecs.umich.edu                break
2003395Shsul@eecs.umich.edu            else:
2013395Shsul@eecs.umich.edu                exit_event = m5.simulate(period)
2023395Shsul@eecs.umich.edu                sim_ticks += period
2033395Shsul@eecs.umich.edu                while exit_event.getCause() == "checkpoint":
2043395Shsul@eecs.umich.edu                    exit_event = m5.simulate(sim_ticks - m5.curTick())
2053395Shsul@eecs.umich.edu                if exit_event.getCause() == "simulate() limit reached":
2063509Shsul@eecs.umich.edu                    m5.checkpoint(root, joinpath(cptdir, "cpt.%d"))
2073395Shsul@eecs.umich.edu                    num_checkpoints += 1
2083395Shsul@eecs.umich.edu
2093999Ssaidi@eecs.umich.edu        if exit_event.getCause() == "user interrupt received":
2103999Ssaidi@eecs.umich.edu            exit_cause = exit_event.getCause();
2113999Ssaidi@eecs.umich.edu
2123999Ssaidi@eecs.umich.edu
2133395Shsul@eecs.umich.edu    else: #no checkpoints being taken via this script
2143395Shsul@eecs.umich.edu        exit_event = m5.simulate(maxtick)
2153395Shsul@eecs.umich.edu
2163395Shsul@eecs.umich.edu        while exit_event.getCause() == "checkpoint":
2173509Shsul@eecs.umich.edu            m5.checkpoint(root, joinpath(cptdir, "cpt.%d"))
2183395Shsul@eecs.umich.edu            num_checkpoints += 1
2193395Shsul@eecs.umich.edu            if num_checkpoints == max_checkpoints:
2203395Shsul@eecs.umich.edu                exit_cause =  "maximum %d checkpoints dropped" % max_checkpoints
2213395Shsul@eecs.umich.edu                break
2223395Shsul@eecs.umich.edu
2233511Shsul@eecs.umich.edu            exit_event = m5.simulate(maxtick - m5.curTick())
2243395Shsul@eecs.umich.edu            exit_cause = exit_event.getCause()
2253395Shsul@eecs.umich.edu
2263395Shsul@eecs.umich.edu    if exit_cause == '':
2273395Shsul@eecs.umich.edu        exit_cause = exit_event.getCause()
2283514Sktlim@umich.edu    print 'Exiting @ cycle %i because %s' % (m5.curTick(), exit_cause)
2293395Shsul@eecs.umich.edu
230