Simulation.py revision 3480
13395Shsul@eecs.umich.edu# Copyright (c) 2006 The Regents of The University of Michigan
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33395Shsul@eecs.umich.edu#
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63395Shsul@eecs.umich.edu# met: redistributions of source code must retain the above copyright
73395Shsul@eecs.umich.edu# notice, this list of conditions and the following disclaimer;
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273395Shsul@eecs.umich.edu# Authors: Lisa Hsu
283395Shsul@eecs.umich.edu
293395Shsul@eecs.umich.edufrom os import getcwd
303395Shsul@eecs.umich.eduimport m5
313395Shsul@eecs.umich.edufrom m5.objects import *
323395Shsul@eecs.umich.edum5.AddToPath('../common')
333448Shsul@eecs.umich.edufrom Caches import L1Cache
343395Shsul@eecs.umich.edu
353395Shsul@eecs.umich.edudef run(options, root, testsys):
363395Shsul@eecs.umich.edu    if options.maxtick:
373395Shsul@eecs.umich.edu        maxtick = options.maxtick
383395Shsul@eecs.umich.edu    elif options.maxtime:
393395Shsul@eecs.umich.edu        simtime = int(options.maxtime * root.clock.value)
403395Shsul@eecs.umich.edu        print "simulating for: ", simtime
413395Shsul@eecs.umich.edu        maxtick = simtime
423395Shsul@eecs.umich.edu    else:
433395Shsul@eecs.umich.edu        maxtick = -1
443395Shsul@eecs.umich.edu
453395Shsul@eecs.umich.edu    if options.checkpoint_dir:
463395Shsul@eecs.umich.edu        cptdir = options.checkpoint_dir
473395Shsul@eecs.umich.edu    else:
483395Shsul@eecs.umich.edu        cptdir = getcwd()
493395Shsul@eecs.umich.edu
503395Shsul@eecs.umich.edu    np = options.num_cpus
513395Shsul@eecs.umich.edu    max_checkpoints = options.max_checkpoints
523395Shsul@eecs.umich.edu
533395Shsul@eecs.umich.edu    if options.standard_switch:
543395Shsul@eecs.umich.edu        switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(np+i))
553395Shsul@eecs.umich.edu                       for i in xrange(np)]
563478Shsul@eecs.umich.edu        switch_cpus_1 = [DerivO3CPU(defer_registration=True, cpu_id=(2*np+i))
573395Shsul@eecs.umich.edu                        for i in xrange(np)]
583478Shsul@eecs.umich.edu
593395Shsul@eecs.umich.edu        for i in xrange(np):
603395Shsul@eecs.umich.edu            switch_cpus[i].system =  testsys
613478Shsul@eecs.umich.edu            switch_cpus_1[i].system =  testsys
623395Shsul@eecs.umich.edu            if not m5.build_env['FULL_SYSTEM']:
633395Shsul@eecs.umich.edu                switch_cpus[i].workload = testsys.cpu[i].workload
643478Shsul@eecs.umich.edu                switch_cpus_1[i].workload = testsys.cpu[i].workload
653395Shsul@eecs.umich.edu            switch_cpus[i].clock = testsys.cpu[0].clock
663478Shsul@eecs.umich.edu            switch_cpus_1[i].clock = testsys.cpu[0].clock
673480Shsul@eecs.umich.edu
683480Shsul@eecs.umich.edu            ## add caches to the warmup timing CPU (which will be
693480Shsul@eecs.umich.edu            ## xferred to O3 when you switch again)
703395Shsul@eecs.umich.edu            if options.caches:
713395Shsul@eecs.umich.edu                switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
723395Shsul@eecs.umich.edu                                                       L1Cache(size = '64kB'))
733480Shsul@eecs.umich.edu            else: # O3 CPU must have a cache to work.
743480Shsul@eecs.umich.edu                switch_cpus_1[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
753480Shsul@eecs.umich.edu                                                         L1Cache(size = '64kB'))
763480Shsul@eecs.umich.edu                switch_cpus_1[i].connectMemPorts(testsys.membus)
773395Shsul@eecs.umich.edu
783395Shsul@eecs.umich.edu            switch_cpus[i].connectMemPorts(testsys.membus)
793478Shsul@eecs.umich.edu
803395Shsul@eecs.umich.edu            root.switch_cpus = switch_cpus
813478Shsul@eecs.umich.edu            root.switch_cpus_1 = switch_cpus_1
823395Shsul@eecs.umich.edu            switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
833478Shsul@eecs.umich.edu            switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)]
843395Shsul@eecs.umich.edu
853395Shsul@eecs.umich.edu    m5.instantiate(root)
863395Shsul@eecs.umich.edu
873395Shsul@eecs.umich.edu    if options.checkpoint_restore:
883395Shsul@eecs.umich.edu        from os.path import isdir
893395Shsul@eecs.umich.edu        from os import listdir
903395Shsul@eecs.umich.edu        import re
913395Shsul@eecs.umich.edu
923395Shsul@eecs.umich.edu        if not isdir(cptdir):
933395Shsul@eecs.umich.edu            m5.panic("checkpoint dir %s does not exist!" % cptdir)
943395Shsul@eecs.umich.edu
953395Shsul@eecs.umich.edu        dirs = listdir(cptdir)
963395Shsul@eecs.umich.edu        expr = re.compile('cpt.([0-9]*)')
973395Shsul@eecs.umich.edu        cpts = []
983395Shsul@eecs.umich.edu        for dir in dirs:
993395Shsul@eecs.umich.edu            match = expr.match(dir)
1003395Shsul@eecs.umich.edu            if match:
1013395Shsul@eecs.umich.edu                cpts.append(match.group(1))
1023395Shsul@eecs.umich.edu
1033395Shsul@eecs.umich.edu        cpts.sort(lambda a,b: cmp(long(a), long(b)))
1043395Shsul@eecs.umich.edu
1053395Shsul@eecs.umich.edu        cpt_num = options.checkpoint_restore
1063395Shsul@eecs.umich.edu
1073395Shsul@eecs.umich.edu        if cpt_num > len(cpts):
1083395Shsul@eecs.umich.edu            m5.panic('Checkpoint %d not found' % cpt_num)
1093395Shsul@eecs.umich.edu
1103395Shsul@eecs.umich.edu        m5.restoreCheckpoint(root,
1113395Shsul@eecs.umich.edu                             "/".join([cptdir, "cpt.%s" % cpts[cpt_num - 1]]))
1123395Shsul@eecs.umich.edu
1133395Shsul@eecs.umich.edu    if options.standard_switch:
1143395Shsul@eecs.umich.edu        exit_event = m5.simulate(10000)
1153395Shsul@eecs.umich.edu
1163395Shsul@eecs.umich.edu        ## when you change to Timing (or Atomic), you halt the system given
1173395Shsul@eecs.umich.edu        ## as argument.  When you are finished with the system changes
1183395Shsul@eecs.umich.edu        ## (including switchCpus), you must resume the system manually.
1193395Shsul@eecs.umich.edu        ## You DON'T need to resume after just switching CPUs if you haven't
1203395Shsul@eecs.umich.edu        ## changed anything on the system level.
1213395Shsul@eecs.umich.edu
1223395Shsul@eecs.umich.edu        m5.changeToTiming(testsys)
1233395Shsul@eecs.umich.edu        m5.switchCpus(switch_cpu_list)
1243395Shsul@eecs.umich.edu        m5.resume(testsys)
1253395Shsul@eecs.umich.edu
1263445Shsul@eecs.umich.edu        exit_event = m5.simulate(options.warmup)
1273395Shsul@eecs.umich.edu        m5.switchCpus(switch_cpu_list1)
1283395Shsul@eecs.umich.edu
1293395Shsul@eecs.umich.edu    num_checkpoints = 0
1303395Shsul@eecs.umich.edu    exit_cause = ''
1313395Shsul@eecs.umich.edu
1323410Shsul@eecs.umich.edu    ## Checkpoints being taken via the command line at <when> and at subsequent
1333410Shsul@eecs.umich.edu    ## periods of <period>.  Checkpoint instructions received from the benchmark running
1343410Shsul@eecs.umich.edu    ## are ignored and skipped in favor of command line checkpoint instructions.
1353395Shsul@eecs.umich.edu    if options.take_checkpoints:
1363395Shsul@eecs.umich.edu        [when, period] = options.take_checkpoints.split(",", 1)
1373395Shsul@eecs.umich.edu        when = int(when)
1383395Shsul@eecs.umich.edu        period = int(period)
1393395Shsul@eecs.umich.edu
1403395Shsul@eecs.umich.edu        exit_event = m5.simulate(when)
1413395Shsul@eecs.umich.edu        while exit_event.getCause() == "checkpoint":
1423395Shsul@eecs.umich.edu            exit_event = m5.simulate(when - m5.curTick())
1433395Shsul@eecs.umich.edu
1443395Shsul@eecs.umich.edu        if exit_event.getCause() == "simulate() limit reached":
1453447Shsul@eecs.umich.edu            m5.checkpoint(root, "/".join([cptdir,"cpt.%d"]))
1463395Shsul@eecs.umich.edu            num_checkpoints += 1
1473395Shsul@eecs.umich.edu
1483395Shsul@eecs.umich.edu        sim_ticks = when
1493395Shsul@eecs.umich.edu        exit_cause = "maximum %d checkpoints dropped" % max_checkpoints
1503395Shsul@eecs.umich.edu        while num_checkpoints < max_checkpoints:
1513395Shsul@eecs.umich.edu            if (sim_ticks + period) > maxtick and maxtick != -1:
1523395Shsul@eecs.umich.edu                exit_event = m5.simulate(maxtick - sim_ticks)
1533395Shsul@eecs.umich.edu                exit_cause = exit_event.getCause()
1543395Shsul@eecs.umich.edu                break
1553395Shsul@eecs.umich.edu            else:
1563395Shsul@eecs.umich.edu                exit_event = m5.simulate(period)
1573395Shsul@eecs.umich.edu                sim_ticks += period
1583395Shsul@eecs.umich.edu                while exit_event.getCause() == "checkpoint":
1593395Shsul@eecs.umich.edu                    exit_event = m5.simulate(sim_ticks - m5.curTick())
1603395Shsul@eecs.umich.edu                if exit_event.getCause() == "simulate() limit reached":
1613447Shsul@eecs.umich.edu                    m5.checkpoint(root, "/".join([cptdir,"cpt.%d"]))
1623395Shsul@eecs.umich.edu                    num_checkpoints += 1
1633395Shsul@eecs.umich.edu
1643395Shsul@eecs.umich.edu    else: #no checkpoints being taken via this script
1653395Shsul@eecs.umich.edu        exit_event = m5.simulate(maxtick)
1663395Shsul@eecs.umich.edu
1673395Shsul@eecs.umich.edu        while exit_event.getCause() == "checkpoint":
1683447Shsul@eecs.umich.edu            m5.checkpoint(root, "/".join([cptdir,"cpt.%d"]))
1693395Shsul@eecs.umich.edu            num_checkpoints += 1
1703395Shsul@eecs.umich.edu            if num_checkpoints == max_checkpoints:
1713395Shsul@eecs.umich.edu                exit_cause =  "maximum %d checkpoints dropped" % max_checkpoints
1723395Shsul@eecs.umich.edu                break
1733395Shsul@eecs.umich.edu
1743395Shsul@eecs.umich.edu            if maxtick == -1:
1753395Shsul@eecs.umich.edu                exit_event = m5.simulate(maxtick)
1763395Shsul@eecs.umich.edu            else:
1773395Shsul@eecs.umich.edu                exit_event = m5.simulate(maxtick - m5.curTick())
1783395Shsul@eecs.umich.edu
1793395Shsul@eecs.umich.edu            exit_cause = exit_event.getCause()
1803395Shsul@eecs.umich.edu
1813395Shsul@eecs.umich.edu    if exit_cause == '':
1823395Shsul@eecs.umich.edu        exit_cause = exit_event.getCause()
1833395Shsul@eecs.umich.edu    print 'Exiting @ cycle', m5.curTick(), 'because ', exit_cause
1843395Shsul@eecs.umich.edu
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