MemConfig.py revision 9836:4411b4e0c03a 
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35#
36# Authors: Andreas Sandberg
37#          Andreas Hansson
38
39import m5.objects
40import inspect
41import sys
42from textwrap import  TextWrapper
43
44# Dictionary of mapping names of real memory controller models to
45# classes.
46_mem_classes = {}
47
48# Memory aliases. We make sure they exist before we add them to the
49# fina; list. A target may be specified as a tuple, in which case the
50# first available memory controller model in the tuple will be used.
51_mem_aliases_all = [
52    ("simple_mem", "SimpleMemory"),
53    ("ddr3_1600_x64", "DDR3_1600_x64"),
54    ("lpddr2_s4_1066_x32", "LPDDR2_S4_1066_x32"),
55    ("lpddr3_1600_x32", "LPDDR3_1600_x32"),
56    ("wio_200_x128", "WideIO_200_x128"),
57    ]
58
59# Filtered list of aliases. Only aliases for existing memory
60# controllers exist in this list.
61_mem_aliases = {}
62
63
64def is_mem_class(cls):
65    """Determine if a class is a memory controller that can be instantiated"""
66
67    # We can't use the normal inspect.isclass because the ParamFactory
68    # and ProxyFactory classes have a tendency to confuse it.
69    try:
70        return issubclass(cls, m5.objects.AbstractMemory) and \
71            not cls.abstract
72    except TypeError:
73        return False
74
75def get(name):
76    """Get a memory class from a user provided class name or alias."""
77
78    real_name = _mem_aliases.get(name, name)
79
80    try:
81        mem_class = _mem_classes[real_name]
82        return mem_class
83    except KeyError:
84        print "%s is not a valid memory controller." % (name,)
85        sys.exit(1)
86
87def print_mem_list():
88    """Print a list of available memory classes including their aliases."""
89
90    print "Available memory classes:"
91    doc_wrapper = TextWrapper(initial_indent="\t\t", subsequent_indent="\t\t")
92    for name, cls in _mem_classes.items():
93        print "\t%s" % name
94
95        # Try to extract the class documentation from the class help
96        # string.
97        doc = inspect.getdoc(cls)
98        if doc:
99            for line in doc_wrapper.wrap(doc):
100                print line
101
102    if _mem_aliases:
103        print "\nMemory aliases:"
104        for alias, target in _mem_aliases.items():
105            print "\t%s => %s" % (alias, target)
106
107def mem_names():
108    """Return a list of valid memory names."""
109    return _mem_classes.keys() + _mem_aliases.keys()
110
111# Add all memory controllers in the object hierarchy.
112for name, cls in inspect.getmembers(m5.objects, is_mem_class):
113    _mem_classes[name] = cls
114
115for alias, target in _mem_aliases_all:
116    if isinstance(target, tuple):
117        # Some aliases contain a list of memory controller models
118        # sorted in priority order. Use the first target that's
119        # available.
120        for t in target:
121            if t in _mem_classes:
122                _mem_aliases[alias] = t
123                break
124    elif target in _mem_classes:
125        # Normal alias
126        _mem_aliases[alias] = target
127
128def config_mem(options, system):
129    """
130    Create the memory controllers based on the options and attach them.
131
132    If requested, we make a multi-channel configuration of the
133    selected memory controller class by creating multiple instances of
134    the specific class. The individual controllers have their
135    parameters set such that the address range is interleaved between
136    them.
137    """
138
139    nbr_mem_ctrls = options.mem_channels
140    import math
141    from m5.util import fatal
142    intlv_bits = int(math.log(nbr_mem_ctrls, 2))
143    if 2 ** intlv_bits != nbr_mem_ctrls:
144        fatal("Number of memory channels must be a power of 2")
145    cls = get(options.mem_type)
146    mem_ctrls = []
147
148    # The default behaviour is to interleave on cache line granularity
149    cache_line_bit = int(math.log(system.cache_line_size.value, 2)) - 1
150    intlv_low_bit = cache_line_bit
151
152    # For every range (most systems will only have one), create an
153    # array of controllers and set their parameters to match their
154    # address mapping in the case of a DRAM
155    for r in system.mem_ranges:
156        for i in xrange(nbr_mem_ctrls):
157            # Create an instance so we can figure out the address
158            # mapping and row-buffer size
159            ctrl = cls()
160
161            # Only do this for DRAMs
162            if issubclass(cls, m5.objects.SimpleDRAM):
163                # Inform each controller how many channels to account
164                # for
165                ctrl.channels = nbr_mem_ctrls
166
167                # If the channel bits are appearing after the column
168                # bits, we need to add the appropriate number of bits
169                # for the row buffer size
170                if ctrl.addr_mapping.value == 'RaBaChCo':
171                    # This computation only really needs to happen
172                    # once, but as we rely on having an instance we
173                    # end up having to repeat it for each and every
174                    # one
175                    rowbuffer_size = ctrl.device_rowbuffer_size.value * \
176                        ctrl.devices_per_rank.value
177
178                    intlv_low_bit = int(math.log(rowbuffer_size, 2)) - 1
179
180            # We got all we need to configure the appropriate address
181            # range
182            ctrl.range = m5.objects.AddrRange(r.start, size = r.size(),
183                                              intlvHighBit = \
184                                                  intlv_low_bit + intlv_bits,
185                                              intlvBits = intlv_bits,
186                                              intlvMatch = i)
187            mem_ctrls.append(ctrl)
188
189    system.mem_ctrls = mem_ctrls
190
191    # Connect the controllers to the membus
192    for i in xrange(nbr_mem_ctrls):
193        system.mem_ctrls[i].port = system.membus.master
194