MemConfig.py revision 10136:ba1ed063e3af 
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35#
36# Authors: Andreas Sandberg
37#          Andreas Hansson
38
39import m5.objects
40import inspect
41import sys
42from textwrap import  TextWrapper
43
44# Dictionary of mapping names of real memory controller models to
45# classes.
46_mem_classes = {}
47
48# Memory aliases. We make sure they exist before we add them to the
49# fina; list. A target may be specified as a tuple, in which case the
50# first available memory controller model in the tuple will be used.
51_mem_aliases_all = [
52    ("simple_mem", "SimpleMemory"),
53    ("ddr3_1600_x64", "DDR3_1600_x64"),
54    ("lpddr2_s4_1066_x32", "LPDDR2_S4_1066_x32"),
55    ("lpddr3_1600_x32", "LPDDR3_1600_x32"),
56    ("wio_200_x128", "WideIO_200_x128"),
57    ("dramsim2", "DRAMSim2")
58    ]
59
60# Filtered list of aliases. Only aliases for existing memory
61# controllers exist in this list.
62_mem_aliases = {}
63
64
65def is_mem_class(cls):
66    """Determine if a class is a memory controller that can be instantiated"""
67
68    # We can't use the normal inspect.isclass because the ParamFactory
69    # and ProxyFactory classes have a tendency to confuse it.
70    try:
71        return issubclass(cls, m5.objects.AbstractMemory) and \
72            not cls.abstract
73    except TypeError:
74        return False
75
76def get(name):
77    """Get a memory class from a user provided class name or alias."""
78
79    real_name = _mem_aliases.get(name, name)
80
81    try:
82        mem_class = _mem_classes[real_name]
83        return mem_class
84    except KeyError:
85        print "%s is not a valid memory controller." % (name,)
86        sys.exit(1)
87
88def print_mem_list():
89    """Print a list of available memory classes including their aliases."""
90
91    print "Available memory classes:"
92    doc_wrapper = TextWrapper(initial_indent="\t\t", subsequent_indent="\t\t")
93    for name, cls in _mem_classes.items():
94        print "\t%s" % name
95
96        # Try to extract the class documentation from the class help
97        # string.
98        doc = inspect.getdoc(cls)
99        if doc:
100            for line in doc_wrapper.wrap(doc):
101                print line
102
103    if _mem_aliases:
104        print "\nMemory aliases:"
105        for alias, target in _mem_aliases.items():
106            print "\t%s => %s" % (alias, target)
107
108def mem_names():
109    """Return a list of valid memory names."""
110    return _mem_classes.keys() + _mem_aliases.keys()
111
112# Add all memory controllers in the object hierarchy.
113for name, cls in inspect.getmembers(m5.objects, is_mem_class):
114    _mem_classes[name] = cls
115
116for alias, target in _mem_aliases_all:
117    if isinstance(target, tuple):
118        # Some aliases contain a list of memory controller models
119        # sorted in priority order. Use the first target that's
120        # available.
121        for t in target:
122            if t in _mem_classes:
123                _mem_aliases[alias] = t
124                break
125    elif target in _mem_classes:
126        # Normal alias
127        _mem_aliases[alias] = target
128
129def config_mem(options, system):
130    """
131    Create the memory controllers based on the options and attach them.
132
133    If requested, we make a multi-channel configuration of the
134    selected memory controller class by creating multiple instances of
135    the specific class. The individual controllers have their
136    parameters set such that the address range is interleaved between
137    them.
138    """
139
140    nbr_mem_ctrls = options.mem_channels
141    import math
142    from m5.util import fatal
143    intlv_bits = int(math.log(nbr_mem_ctrls, 2))
144    if 2 ** intlv_bits != nbr_mem_ctrls:
145        fatal("Number of memory channels must be a power of 2")
146    cls = get(options.mem_type)
147    mem_ctrls = []
148
149    # The default behaviour is to interleave on cache line granularity
150    cache_line_bit = int(math.log(system.cache_line_size.value, 2)) - 1
151    intlv_low_bit = cache_line_bit
152
153    # For every range (most systems will only have one), create an
154    # array of controllers and set their parameters to match their
155    # address mapping in the case of a DRAM
156    for r in system.mem_ranges:
157        for i in xrange(nbr_mem_ctrls):
158            # Create an instance so we can figure out the address
159            # mapping and row-buffer size
160            ctrl = cls()
161
162            # Only do this for DRAMs
163            if issubclass(cls, m5.objects.SimpleDRAM):
164                # Inform each controller how many channels to account
165                # for
166                ctrl.channels = nbr_mem_ctrls
167
168                # If the channel bits are appearing after the column
169                # bits, we need to add the appropriate number of bits
170                # for the row buffer size
171                if ctrl.addr_mapping.value == 'RoRaBaChCo':
172                    # This computation only really needs to happen
173                    # once, but as we rely on having an instance we
174                    # end up having to repeat it for each and every
175                    # one
176                    rowbuffer_size = ctrl.device_rowbuffer_size.value * \
177                        ctrl.devices_per_rank.value
178
179                    intlv_low_bit = int(math.log(rowbuffer_size, 2)) - 1
180
181            # We got all we need to configure the appropriate address
182            # range
183            ctrl.range = m5.objects.AddrRange(r.start, size = r.size(),
184                                              intlvHighBit = \
185                                                  intlv_low_bit + intlv_bits,
186                                              intlvBits = intlv_bits,
187                                              intlvMatch = i)
188            mem_ctrls.append(ctrl)
189
190    system.mem_ctrls = mem_ctrls
191
192    # Connect the controllers to the membus
193    for i in xrange(len(system.mem_ctrls)):
194        system.mem_ctrls[i].port = system.membus.master
195