GPUTLBConfig.py revision 13731
1# Copyright (c) 2011-2015 Advanced Micro Devices, Inc. 2# All rights reserved. 3# 4# For use for simulation and test purposes only 5# 6# Redistribution and use in source and binary forms, with or without 7# modification, are permitted provided that the following conditions are met: 8# 9# 1. Redistributions of source code must retain the above copyright notice, 10# this list of conditions and the following disclaimer. 11# 12# 2. Redistributions in binary form must reproduce the above copyright notice, 13# this list of conditions and the following disclaimer in the documentation 14# and/or other materials provided with the distribution. 15# 16# 3. Neither the name of the copyright holder nor the names of its 17# contributors may be used to endorse or promote products derived from this 18# software without specific prior written permission. 19# 20# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 24# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30# POSSIBILITY OF SUCH DAMAGE. 31# 32# Authors: Lisa Hsu 33 34from __future__ import print_function 35 36# Configure the TLB hierarchy 37# Places which would probably need to be modified if you 38# want a different hierarchy are specified by a <Modify here .. >' 39# comment 40import m5 41from m5.objects import * 42 43def TLB_constructor(level): 44 45 constructor_call = "X86GPUTLB(size = options.L%(level)dTLBentries, \ 46 assoc = options.L%(level)dTLBassoc, \ 47 hitLatency = options.L%(level)dAccessLatency,\ 48 missLatency2 = options.L%(level)dMissLatency,\ 49 maxOutstandingReqs = options.L%(level)dMaxOutstandingReqs,\ 50 accessDistance = options.L%(level)dAccessDistanceStat,\ 51 clk_domain = SrcClockDomain(\ 52 clock = options.GPUClock,\ 53 voltage_domain = VoltageDomain(\ 54 voltage = options.gpu_voltage)))" % locals() 55 return constructor_call 56 57def Coalescer_constructor(level): 58 59 constructor_call = "TLBCoalescer(probesPerCycle = \ 60 options.L%(level)dProbesPerCycle, \ 61 coalescingWindow = options.L%(level)dCoalescingWindow,\ 62 disableCoalescing = options.L%(level)dDisableCoalescing,\ 63 clk_domain = SrcClockDomain(\ 64 clock = options.GPUClock,\ 65 voltage_domain = VoltageDomain(\ 66 voltage = options.gpu_voltage)))" % locals() 67 return constructor_call 68 69def create_TLB_Coalescer(options, my_level, my_index, TLB_name, Coalescer_name): 70 # arguments: options, TLB level, number of private structures for this Level, 71 # TLB name and Coalescer name 72 for i in range(my_index): 73 TLB_name.append(eval(TLB_constructor(my_level))) 74 Coalescer_name.append(eval(Coalescer_constructor(my_level))) 75 76def config_tlb_hierarchy(options, system, shader_idx): 77 n_cu = options.num_compute_units 78 # Make this configurable now, instead of the hard coded val. The dispatcher 79 # is always the last item in the system.cpu list. 80 dispatcher_idx = len(system.cpu) - 1 81 82 if options.TLB_config == "perLane": 83 num_TLBs = 64 * n_cu 84 elif options.TLB_config == "mono": 85 num_TLBs = 1 86 elif options.TLB_config == "perCU": 87 num_TLBs = n_cu 88 elif options.TLB_config == "2CU": 89 num_TLBs = n_cu >> 1 90 else: 91 print("Bad option for TLB Configuration.") 92 sys.exit(1) 93 94 #---------------------------------------------------------------------------------------- 95 # A visual representation of the TLB hierarchy 96 # for ease of configuration 97 # < Modify here the width and the number of levels if you want a different configuration > 98 # width is the number of TLBs of the given type (i.e., D-TLB, I-TLB etc) for this level 99 L1 = [{'name': 'sqc', 'width': options.num_sqc, 'TLBarray': [], 'CoalescerArray': []}, 100 {'name': 'dispatcher', 'width': 1, 'TLBarray': [], 'CoalescerArray': []}, 101 {'name': 'l1', 'width': num_TLBs, 'TLBarray': [], 'CoalescerArray': []}] 102 103 L2 = [{'name': 'l2', 'width': 1, 'TLBarray': [], 'CoalescerArray': []}] 104 L3 = [{'name': 'l3', 'width': 1, 'TLBarray': [], 'CoalescerArray': []}] 105 106 TLB_hierarchy = [L1, L2, L3] 107 108 #---------------------------------------------------------------------------------------- 109 # Create the hiearchy 110 # Call the appropriate constructors and add objects to the system 111 112 for i in range(len(TLB_hierarchy)): 113 hierarchy_level = TLB_hierarchy[i] 114 level = i+1 115 for TLB_type in hierarchy_level: 116 TLB_index = TLB_type['width'] 117 TLB_array = TLB_type['TLBarray'] 118 Coalescer_array = TLB_type['CoalescerArray'] 119 # If the sim calls for a fixed L1 TLB size across CUs, 120 # override the TLB entries option 121 if options.tot_L1TLB_size: 122 options.L1TLBentries = options.tot_L1TLB_size / num_TLBs 123 if options.L1TLBassoc > options.L1TLBentries: 124 options.L1TLBassoc = options.L1TLBentries 125 # call the constructors for the TLB and the Coalescer 126 create_TLB_Coalescer(options, level, TLB_index,\ 127 TLB_array, Coalescer_array) 128 129 system_TLB_name = TLB_type['name'] + '_tlb' 130 system_Coalescer_name = TLB_type['name'] + '_coalescer' 131 132 # add the different TLB levels to the system 133 # Modify here if you want to make the TLB hierarchy a child of 134 # the shader. 135 exec('system.%s = TLB_array' % system_TLB_name) 136 exec('system.%s = Coalescer_array' % system_Coalescer_name) 137 138 #=========================================================== 139 # Specify the TLB hierarchy (i.e., port connections) 140 # All TLBs but the last level TLB need to have a memSidePort (master) 141 #=========================================================== 142 143 # Each TLB is connected with its Coalescer through a single port. 144 # There is a one-to-one mapping of TLBs to Coalescers at a given level 145 # This won't be modified no matter what the hierarchy looks like. 146 for i in range(len(TLB_hierarchy)): 147 hierarchy_level = TLB_hierarchy[i] 148 level = i+1 149 for TLB_type in hierarchy_level: 150 name = TLB_type['name'] 151 for index in range(TLB_type['width']): 152 exec('system.%s_coalescer[%d].master[0] = \ 153 system.%s_tlb[%d].slave[0]' % \ 154 (name, index, name, index)) 155 156 # Connect the cpuSidePort (slave) of all the coalescers in level 1 157 # < Modify here if you want a different configuration > 158 for TLB_type in L1: 159 name = TLB_type['name'] 160 num_TLBs = TLB_type['width'] 161 if name == 'l1': # L1 D-TLBs 162 tlb_per_cu = num_TLBs // n_cu 163 for cu_idx in range(n_cu): 164 if tlb_per_cu: 165 for tlb in range(tlb_per_cu): 166 exec('system.cpu[%d].CUs[%d].translation_port[%d] = \ 167 system.l1_coalescer[%d].slave[%d]' % \ 168 (shader_idx, cu_idx, tlb, cu_idx*tlb_per_cu+tlb, 0)) 169 else: 170 exec('system.cpu[%d].CUs[%d].translation_port[%d] = \ 171 system.l1_coalescer[%d].slave[%d]' % \ 172 (shader_idx, cu_idx, tlb_per_cu, cu_idx / (n_cu / num_TLBs), cu_idx % (n_cu / num_TLBs))) 173 174 elif name == 'dispatcher': # Dispatcher TLB 175 for index in range(TLB_type['width']): 176 exec('system.cpu[%d].translation_port = \ 177 system.dispatcher_coalescer[%d].slave[0]' % \ 178 (dispatcher_idx, index)) 179 elif name == 'sqc': # I-TLB 180 for index in range(n_cu): 181 sqc_tlb_index = index / options.cu_per_sqc 182 sqc_tlb_port_id = index % options.cu_per_sqc 183 exec('system.cpu[%d].CUs[%d].sqc_tlb_port = \ 184 system.sqc_coalescer[%d].slave[%d]' % \ 185 (shader_idx, index, sqc_tlb_index, sqc_tlb_port_id)) 186 187 188 # Connect the memSidePorts (masters) of all the TLBs with the 189 # cpuSidePorts (slaves) of the Coalescers of the next level 190 # < Modify here if you want a different configuration > 191 # L1 <-> L2 192 l2_coalescer_index = 0 193 for TLB_type in L1: 194 name = TLB_type['name'] 195 for index in range(TLB_type['width']): 196 exec('system.%s_tlb[%d].master[0] = \ 197 system.l2_coalescer[0].slave[%d]' % \ 198 (name, index, l2_coalescer_index)) 199 l2_coalescer_index += 1 200 # L2 <-> L3 201 system.l2_tlb[0].master[0] = system.l3_coalescer[0].slave[0] 202 203 return system 204