FSConfig.py revision 8706:b1838faf3bcc
1# Copyright (c) 2010-2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2010-2011 Advanced Micro Devices, Inc. 14# Copyright (c) 2006-2008 The Regents of The University of Michigan 15# All rights reserved. 16# 17# Redistribution and use in source and binary forms, with or without 18# modification, are permitted provided that the following conditions are 19# met: redistributions of source code must retain the above copyright 20# notice, this list of conditions and the following disclaimer; 21# redistributions in binary form must reproduce the above copyright 22# notice, this list of conditions and the following disclaimer in the 23# documentation and/or other materials provided with the distribution; 24# neither the name of the copyright holders nor the names of its 25# contributors may be used to endorse or promote products derived from 26# this software without specific prior written permission. 27# 28# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39# 40# Authors: Kevin Lim 41 42from m5.objects import * 43from Benchmarks import * 44from m5.util import convert 45 46class CowIdeDisk(IdeDisk): 47 image = CowDiskImage(child=RawDiskImage(read_only=True), 48 read_only=False) 49 50 def childImage(self, ci): 51 self.image.child.image_file = ci 52 53class MemBus(Bus): 54 badaddr_responder = BadAddr() 55 default = Self.badaddr_responder.pio 56 57 58def makeLinuxAlphaSystem(mem_mode, mdesc = None): 59 class BaseTsunami(Tsunami): 60 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 61 ide = IdeController(disks=[Parent.disk0, Parent.disk2], 62 pci_func=0, pci_dev=0, pci_bus=0) 63 64 self = LinuxAlphaSystem() 65 if not mdesc: 66 # generic system 67 mdesc = SysConfig() 68 self.readfile = mdesc.script() 69 self.iobus = Bus(bus_id=0) 70 self.membus = MemBus(bus_id=1) 71 self.bridge = Bridge(delay='50ns', nack_delay='4ns') 72 self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) 73 self.bridge.side_a = self.iobus.port 74 self.bridge.side_b = self.membus.port 75 self.physmem.port = self.membus.port 76 self.disk0 = CowIdeDisk(driveID='master') 77 self.disk2 = CowIdeDisk(driveID='master') 78 self.disk0.childImage(mdesc.disk()) 79 self.disk2.childImage(disk('linux-bigswap2.img')) 80 self.tsunami = BaseTsunami() 81 self.tsunami.attachIO(self.iobus) 82 self.tsunami.ide.pio = self.iobus.port 83 self.tsunami.ethernet.pio = self.iobus.port 84 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 85 read_only = True)) 86 self.intrctrl = IntrControl() 87 self.mem_mode = mem_mode 88 self.terminal = Terminal() 89 self.kernel = binary('vmlinux') 90 self.pal = binary('ts_osfpal') 91 self.console = binary('console') 92 self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 93 94 self.system_port = self.membus.port 95 96 return self 97 98def makeLinuxAlphaRubySystem(mem_mode, mdesc = None): 99 class BaseTsunami(Tsunami): 100 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 101 ide = IdeController(disks=[Parent.disk0, Parent.disk2], 102 pci_func=0, pci_dev=0, pci_bus=0) 103 104 physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) 105 self = LinuxAlphaSystem(physmem = physmem) 106 if not mdesc: 107 # generic system 108 mdesc = SysConfig() 109 self.readfile = mdesc.script() 110 111 # Create pio bus to connect all device pio ports to rubymem's pio port 112 self.piobus = Bus(bus_id=0) 113 114 # 115 # Pio functional accesses from devices need direct access to memory 116 # RubyPort currently does support functional accesses. Therefore provide 117 # the piobus a direct connection to physical memory 118 # 119 self.piobus.port = physmem.port 120 121 self.disk0 = CowIdeDisk(driveID='master') 122 self.disk2 = CowIdeDisk(driveID='master') 123 self.disk0.childImage(mdesc.disk()) 124 self.disk2.childImage(disk('linux-bigswap2.img')) 125 self.tsunami = BaseTsunami() 126 self.tsunami.attachIO(self.piobus) 127 self.tsunami.ide.pio = self.piobus.port 128 self.tsunami.ethernet.pio = self.piobus.port 129 130 # 131 # Store the dma devices for later connection to dma ruby ports. 132 # Append an underscore to dma_devices to avoid the SimObjectVector check. 133 # 134 self._dma_devices = [self.tsunami.ide, self.tsunami.ethernet] 135 136 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 137 read_only = True)) 138 self.intrctrl = IntrControl() 139 self.mem_mode = mem_mode 140 self.terminal = Terminal() 141 self.kernel = binary('vmlinux') 142 self.pal = binary('ts_osfpal') 143 self.console = binary('console') 144 self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 145 146 return self 147 148def makeSparcSystem(mem_mode, mdesc = None): 149 class CowMmDisk(MmDisk): 150 image = CowDiskImage(child=RawDiskImage(read_only=True), 151 read_only=False) 152 153 def childImage(self, ci): 154 self.image.child.image_file = ci 155 156 self = SparcSystem() 157 if not mdesc: 158 # generic system 159 mdesc = SysConfig() 160 self.readfile = mdesc.script() 161 self.iobus = Bus(bus_id=0) 162 self.membus = MemBus(bus_id=1) 163 self.bridge = Bridge(delay='50ns', nack_delay='4ns') 164 self.t1000 = T1000() 165 self.t1000.attachOnChipIO(self.membus) 166 self.t1000.attachIO(self.iobus) 167 self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True) 168 self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True) 169 self.bridge.side_a = self.iobus.port 170 self.bridge.side_b = self.membus.port 171 self.physmem.port = self.membus.port 172 self.physmem2.port = self.membus.port 173 self.rom.port = self.membus.port 174 self.nvram.port = self.membus.port 175 self.hypervisor_desc.port = self.membus.port 176 self.partition_desc.port = self.membus.port 177 self.intrctrl = IntrControl() 178 self.disk0 = CowMmDisk() 179 self.disk0.childImage(disk('disk.s10hw2')) 180 self.disk0.pio = self.iobus.port 181 self.reset_bin = binary('reset_new.bin') 182 self.hypervisor_bin = binary('q_new.bin') 183 self.openboot_bin = binary('openboot_new.bin') 184 self.nvram_bin = binary('nvram1') 185 self.hypervisor_desc_bin = binary('1up-hv.bin') 186 self.partition_desc_bin = binary('1up-md.bin') 187 188 self.system_port = self.membus.port 189 190 return self 191 192def makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False): 193 assert machine_type 194 195 if bare_metal: 196 self = ArmSystem() 197 else: 198 self = LinuxArmSystem() 199 200 if not mdesc: 201 # generic system 202 mdesc = SysConfig() 203 204 self.readfile = mdesc.script() 205 self.iobus = Bus(bus_id=0) 206 self.membus = MemBus(bus_id=1) 207 self.membus.badaddr_responder.warn_access = "warn" 208 self.bridge = Bridge(delay='50ns', nack_delay='4ns') 209 self.bridge.side_a = self.iobus.port 210 self.bridge.side_b = self.membus.port 211 212 self.mem_mode = mem_mode 213 214 if machine_type == "RealView_PBX": 215 self.realview = RealViewPBX() 216 elif machine_type == "RealView_EB": 217 self.realview = RealViewEB() 218 elif machine_type == "VExpress_ELT": 219 self.realview = VExpress_ELT() 220 else: 221 print "Unknown Machine Type" 222 sys.exit(1) 223 224 self.cf0 = CowIdeDisk(driveID='master') 225 self.cf0.childImage(mdesc.disk()) 226 # default to an IDE controller rather than a CF one 227 # assuming we've got one 228 try: 229 self.realview.ide.disks = [self.cf0] 230 except: 231 self.realview.cf_ctrl.disks = [self.cf0] 232 233 if bare_metal: 234 # EOT character on UART will end the simulation 235 self.realview.uart.end_on_eot = True 236 self.physmem = PhysicalMemory(range = AddrRange(Addr(mdesc.mem())), 237 zero = True) 238 else: 239 self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8') 240 self.machine_type = machine_type 241 if convert.toMemorySize(mdesc.mem()) > convert.toMemorySize('256MB'): 242 print "The currently implemented ARM platforms only easily support 256MB of DRAM" 243 print "It might be possible to get some more by using 256MB@0x30000000, but this" 244 print "is untested and may require some heroics" 245 246 boot_flags = 'earlyprintk console=ttyAMA0 lpj=19988480 norandmaps ' + \ 247 'rw loglevel=8 mem=%s root=/dev/sda1' % mdesc.mem() 248 249 self.physmem = PhysicalMemory(range = AddrRange(Addr(mdesc.mem())), 250 zero = True) 251 self.nvmem = PhysicalMemory(range = AddrRange(Addr('2GB'), 252 size = '64MB'), zero = True) 253 self.nvmem.port = self.membus.port 254 self.boot_loader = binary('boot.arm') 255 self.boot_loader_mem = self.nvmem 256 self.gic_cpu_addr = self.realview.gic.cpu_addr 257 self.flags_addr = self.realview.realview_io.pio_addr + 0x30 258 259 if mdesc.disk().lower().count('android'): 260 boot_flags += " init=/init " 261 self.boot_osflags = boot_flags 262 263 self.physmem.port = self.membus.port 264 self.realview.attachOnChipIO(self.membus) 265 self.realview.attachIO(self.iobus) 266 self.intrctrl = IntrControl() 267 self.terminal = Terminal() 268 self.vncserver = VncServer() 269 270 self.system_port = self.membus.port 271 272 return self 273 274 275def makeLinuxMipsSystem(mem_mode, mdesc = None): 276 class BaseMalta(Malta): 277 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 278 ide = IdeController(disks=[Parent.disk0, Parent.disk2], 279 pci_func=0, pci_dev=0, pci_bus=0) 280 281 self = LinuxMipsSystem() 282 if not mdesc: 283 # generic system 284 mdesc = SysConfig() 285 self.readfile = mdesc.script() 286 self.iobus = Bus(bus_id=0) 287 self.membus = MemBus(bus_id=1) 288 self.bridge = Bridge(delay='50ns', nack_delay='4ns') 289 self.physmem = PhysicalMemory(range = AddrRange('1GB')) 290 self.bridge.side_a = self.iobus.port 291 self.bridge.side_b = self.membus.port 292 self.physmem.port = self.membus.port 293 self.disk0 = CowIdeDisk(driveID='master') 294 self.disk2 = CowIdeDisk(driveID='master') 295 self.disk0.childImage(mdesc.disk()) 296 self.disk2.childImage(disk('linux-bigswap2.img')) 297 self.malta = BaseMalta() 298 self.malta.attachIO(self.iobus) 299 self.malta.ide.pio = self.iobus.port 300 self.malta.ethernet.pio = self.iobus.port 301 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 302 read_only = True)) 303 self.intrctrl = IntrControl() 304 self.mem_mode = mem_mode 305 self.terminal = Terminal() 306 self.kernel = binary('mips/vmlinux') 307 self.console = binary('mips/console') 308 self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 309 310 self.system_port = self.membus.port 311 312 return self 313 314def x86IOAddress(port): 315 IO_address_space_base = 0x8000000000000000 316 return IO_address_space_base + port 317 318def connectX86ClassicSystem(x86_sys): 319 x86_sys.membus = MemBus(bus_id=1) 320 x86_sys.physmem.port = x86_sys.membus.port 321 322 # North Bridge 323 x86_sys.iobus = Bus(bus_id=0) 324 x86_sys.bridge = Bridge(delay='50ns', nack_delay='4ns') 325 x86_sys.bridge.side_a = x86_sys.iobus.port 326 x86_sys.bridge.side_b = x86_sys.membus.port 327 328 # connect the io bus 329 x86_sys.pc.attachIO(x86_sys.iobus) 330 331 x86_sys.system_port = x86_sys.membus.port 332 333def connectX86RubySystem(x86_sys): 334 # North Bridge 335 x86_sys.piobus = Bus(bus_id=0) 336 337 # 338 # Pio functional accesses from devices need direct access to memory 339 # RubyPort currently does support functional accesses. Therefore provide 340 # the piobus a direct connection to physical memory 341 # 342 x86_sys.piobus.port = x86_sys.physmem.port 343 344 x86_sys.pc.attachIO(x86_sys.piobus) 345 346 347def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None, Ruby = False): 348 if self == None: 349 self = X86System() 350 351 if not mdesc: 352 # generic system 353 mdesc = SysConfig() 354 self.readfile = mdesc.script() 355 356 self.mem_mode = mem_mode 357 358 # Physical memory 359 self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) 360 361 # Platform 362 self.pc = Pc() 363 364 # Create and connect the busses required by each memory system 365 if Ruby: 366 connectX86RubySystem(self) 367 # add the ide to the list of dma devices that later need to attach to 368 # dma controllers 369 self._dma_devices = [self.pc.south_bridge.ide] 370 else: 371 connectX86ClassicSystem(self) 372 373 self.intrctrl = IntrControl() 374 375 # Disks 376 disk0 = CowIdeDisk(driveID='master') 377 disk2 = CowIdeDisk(driveID='master') 378 disk0.childImage(mdesc.disk()) 379 disk2.childImage(disk('linux-bigswap2.img')) 380 self.pc.south_bridge.ide.disks = [disk0, disk2] 381 382 # Add in a Bios information structure. 383 structures = [X86SMBiosBiosInformation()] 384 self.smbios_table.structures = structures 385 386 # Set up the Intel MP table 387 base_entries = [] 388 ext_entries = [] 389 for i in xrange(numCPUs): 390 bp = X86IntelMPProcessor( 391 local_apic_id = i, 392 local_apic_version = 0x14, 393 enable = True, 394 bootstrap = (i == 0)) 395 base_entries.append(bp) 396 io_apic = X86IntelMPIOAPIC( 397 id = numCPUs, 398 version = 0x11, 399 enable = True, 400 address = 0xfec00000) 401 self.pc.south_bridge.io_apic.apic_id = io_apic.id 402 base_entries.append(io_apic) 403 isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA') 404 base_entries.append(isa_bus) 405 pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI') 406 base_entries.append(pci_bus) 407 connect_busses = X86IntelMPBusHierarchy(bus_id=0, 408 subtractive_decode=True, parent_bus=1) 409 ext_entries.append(connect_busses) 410 pci_dev4_inta = X86IntelMPIOIntAssignment( 411 interrupt_type = 'INT', 412 polarity = 'ConformPolarity', 413 trigger = 'ConformTrigger', 414 source_bus_id = 1, 415 source_bus_irq = 0 + (4 << 2), 416 dest_io_apic_id = io_apic.id, 417 dest_io_apic_intin = 16) 418 base_entries.append(pci_dev4_inta) 419 def assignISAInt(irq, apicPin): 420 assign_8259_to_apic = X86IntelMPIOIntAssignment( 421 interrupt_type = 'ExtInt', 422 polarity = 'ConformPolarity', 423 trigger = 'ConformTrigger', 424 source_bus_id = 0, 425 source_bus_irq = irq, 426 dest_io_apic_id = io_apic.id, 427 dest_io_apic_intin = 0) 428 base_entries.append(assign_8259_to_apic) 429 assign_to_apic = X86IntelMPIOIntAssignment( 430 interrupt_type = 'INT', 431 polarity = 'ConformPolarity', 432 trigger = 'ConformTrigger', 433 source_bus_id = 0, 434 source_bus_irq = irq, 435 dest_io_apic_id = io_apic.id, 436 dest_io_apic_intin = apicPin) 437 base_entries.append(assign_to_apic) 438 assignISAInt(0, 2) 439 assignISAInt(1, 1) 440 for i in range(3, 15): 441 assignISAInt(i, i) 442 self.intel_mp_table.base_entries = base_entries 443 self.intel_mp_table.ext_entries = ext_entries 444 445def setWorkCountOptions(system, options): 446 if options.work_item_id != None: 447 system.work_item_id = options.work_item_id 448 if options.work_begin_cpu_id_exit != None: 449 system.work_begin_cpu_id_exit = options.work_begin_cpu_id_exit 450 if options.work_end_exit_count != None: 451 system.work_end_exit_count = options.work_end_exit_count 452 if options.work_end_checkpoint_count != None: 453 system.work_end_ckpt_count = options.work_end_checkpoint_count 454 if options.work_begin_exit_count != None: 455 system.work_begin_exit_count = options.work_begin_exit_count 456 if options.work_begin_checkpoint_count != None: 457 system.work_begin_ckpt_count = options.work_begin_checkpoint_count 458 if options.work_cpus_checkpoint_count != None: 459 system.work_cpus_ckpt_count = options.work_cpus_checkpoint_count 460 461 462def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None, Ruby = False): 463 self = LinuxX86System() 464 465 # Build up the x86 system and then specialize it for Linux 466 makeX86System(mem_mode, numCPUs, mdesc, self, Ruby) 467 468 # We assume below that there's at least 1MB of memory. We'll require 2 469 # just to avoid corner cases. 470 assert(self.physmem.range.second.getValue() >= 0x200000) 471 472 self.e820_table.entries = \ 473 [ 474 # Mark the first megabyte of memory as reserved 475 X86E820Entry(addr = 0, size = '1MB', range_type = 2), 476 # Mark the rest as available 477 X86E820Entry(addr = 0x100000, 478 size = '%dB' % (self.physmem.range.second - 0x100000 + 1), 479 range_type = 1) 480 ] 481 482 # Command line 483 self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \ 484 'root=/dev/hda1' 485 return self 486 487 488def makeDualRoot(testSystem, driveSystem, dumpfile): 489 self = Root() 490 self.testsys = testSystem 491 self.drivesys = driveSystem 492 self.etherlink = EtherLink() 493 self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 494 self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 495 496 if hasattr(testSystem, 'realview'): 497 self.etherlink.int0 = Parent.testsys.realview.ethernet.interface 498 self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface 499 elif hasattr(testSystem, 'tsunami'): 500 self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 501 self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 502 else: 503 fatal("Don't know how to connect these system together") 504 505 if dumpfile: 506 self.etherdump = EtherDump(file=dumpfile) 507 self.etherlink.dump = Parent.etherdump 508 509 return self 510 511def setMipsOptions(TestCPUClass): 512 #CP0 Configuration 513 TestCPUClass.CoreParams.CP0_PRId_CompanyOptions = 0 514 TestCPUClass.CoreParams.CP0_PRId_CompanyID = 1 515 TestCPUClass.CoreParams.CP0_PRId_ProcessorID = 147 516 TestCPUClass.CoreParams.CP0_PRId_Revision = 0 517 518 #CP0 Interrupt Control 519 TestCPUClass.CoreParams.CP0_IntCtl_IPTI = 7 520 TestCPUClass.CoreParams.CP0_IntCtl_IPPCI = 7 521 522 # Config Register 523 #TestCPUClass.CoreParams.CP0_Config_K23 = 0 # Since TLB 524 #TestCPUClass.CoreParams.CP0_Config_KU = 0 # Since TLB 525 TestCPUClass.CoreParams.CP0_Config_BE = 0 # Little Endian 526 TestCPUClass.CoreParams.CP0_Config_AR = 1 # Architecture Revision 2 527 TestCPUClass.CoreParams.CP0_Config_AT = 0 # MIPS32 528 TestCPUClass.CoreParams.CP0_Config_MT = 1 # TLB MMU 529 #TestCPUClass.CoreParams.CP0_Config_K0 = 2 # Uncached 530 531 #Config 1 Register 532 TestCPUClass.CoreParams.CP0_Config1_M = 1 # Config2 Implemented 533 TestCPUClass.CoreParams.CP0_Config1_MMU = 63 # TLB Size 534 # ***VERY IMPORTANT*** 535 # Remember to modify CP0_Config1 according to cache specs 536 # Examine file ../common/Cache.py 537 TestCPUClass.CoreParams.CP0_Config1_IS = 1 # I-Cache Sets Per Way, 16KB cache, i.e., 1 (128) 538 TestCPUClass.CoreParams.CP0_Config1_IL = 5 # I-Cache Line Size, default in Cache.py is 64, i.e 5 539 TestCPUClass.CoreParams.CP0_Config1_IA = 1 # I-Cache Associativity, default in Cache.py is 2, i.e, a value of 1 540 TestCPUClass.CoreParams.CP0_Config1_DS = 2 # D-Cache Sets Per Way (see below), 32KB cache, i.e., 2 541 TestCPUClass.CoreParams.CP0_Config1_DL = 5 # D-Cache Line Size, default is 64, i.e., 5 542 TestCPUClass.CoreParams.CP0_Config1_DA = 1 # D-Cache Associativity, default is 2, i.e. 1 543 TestCPUClass.CoreParams.CP0_Config1_C2 = 0 # Coprocessor 2 not implemented(?) 544 TestCPUClass.CoreParams.CP0_Config1_MD = 0 # MDMX ASE not implemented in Mips32 545 TestCPUClass.CoreParams.CP0_Config1_PC = 1 # Performance Counters Implemented 546 TestCPUClass.CoreParams.CP0_Config1_WR = 0 # Watch Registers Implemented 547 TestCPUClass.CoreParams.CP0_Config1_CA = 0 # Mips16e NOT implemented 548 TestCPUClass.CoreParams.CP0_Config1_EP = 0 # EJTag Not Implemented 549 TestCPUClass.CoreParams.CP0_Config1_FP = 0 # FPU Implemented 550 551 #Config 2 Register 552 TestCPUClass.CoreParams.CP0_Config2_M = 1 # Config3 Implemented 553 TestCPUClass.CoreParams.CP0_Config2_TU = 0 # Tertiary Cache Control 554 TestCPUClass.CoreParams.CP0_Config2_TS = 0 # Tertiary Cache Sets Per Way 555 TestCPUClass.CoreParams.CP0_Config2_TL = 0 # Tertiary Cache Line Size 556 TestCPUClass.CoreParams.CP0_Config2_TA = 0 # Tertiary Cache Associativity 557 TestCPUClass.CoreParams.CP0_Config2_SU = 0 # Secondary Cache Control 558 TestCPUClass.CoreParams.CP0_Config2_SS = 0 # Secondary Cache Sets Per Way 559 TestCPUClass.CoreParams.CP0_Config2_SL = 0 # Secondary Cache Line Size 560 TestCPUClass.CoreParams.CP0_Config2_SA = 0 # Secondary Cache Associativity 561 562 563 #Config 3 Register 564 TestCPUClass.CoreParams.CP0_Config3_M = 0 # Config4 Not Implemented 565 TestCPUClass.CoreParams.CP0_Config3_DSPP = 1 # DSP ASE Present 566 TestCPUClass.CoreParams.CP0_Config3_LPA = 0 # Large Physical Addresses Not supported in Mips32 567 TestCPUClass.CoreParams.CP0_Config3_VEIC = 0 # EIC Supported 568 TestCPUClass.CoreParams.CP0_Config3_VInt = 0 # Vectored Interrupts Implemented 569 TestCPUClass.CoreParams.CP0_Config3_SP = 0 # Small Pages Supported (PageGrain reg. exists) 570 TestCPUClass.CoreParams.CP0_Config3_MT = 0 # MT Not present 571 TestCPUClass.CoreParams.CP0_Config3_SM = 0 # SmartMIPS ASE Not implemented 572 TestCPUClass.CoreParams.CP0_Config3_TL = 0 # TraceLogic Not implemented 573 574 #SRS Ctl - HSS 575 TestCPUClass.CoreParams.CP0_SrsCtl_HSS = 3 # Four shadow register sets implemented 576 577 578 #TestCPUClass.CoreParams.tlb = TLB() 579 #TestCPUClass.CoreParams.UnifiedTLB = 1 580