FSConfig.py revision 8661 
1# Copyright (c) 2010 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder.  You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2010-2011 Advanced Micro Devices, Inc.
14# Copyright (c) 2006-2008 The Regents of The University of Michigan
15# All rights reserved.
16#
17# Redistribution and use in source and binary forms, with or without
18# modification, are permitted provided that the following conditions are
19# met: redistributions of source code must retain the above copyright
20# notice, this list of conditions and the following disclaimer;
21# redistributions in binary form must reproduce the above copyright
22# notice, this list of conditions and the following disclaimer in the
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24# neither the name of the copyright holders nor the names of its
25# contributors may be used to endorse or promote products derived from
26# this software without specific prior written permission.
27#
28# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39#
40# Authors: Kevin Lim
41
42from m5.objects import *
43from Benchmarks import *
44from m5.util import convert
45
46class CowIdeDisk(IdeDisk):
47    image = CowDiskImage(child=RawDiskImage(read_only=True),
48                         read_only=False)
49
50    def childImage(self, ci):
51        self.image.child.image_file = ci
52
53class MemBus(Bus):
54    badaddr_responder = BadAddr()
55    default = Self.badaddr_responder.pio
56
57
58def makeLinuxAlphaSystem(mem_mode, mdesc = None):
59    class BaseTsunami(Tsunami):
60        ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
61        ide = IdeController(disks=[Parent.disk0, Parent.disk2],
62                            pci_func=0, pci_dev=0, pci_bus=0)
63
64    self = LinuxAlphaSystem()
65    if not mdesc:
66        # generic system
67        mdesc = SysConfig()
68    self.readfile = mdesc.script()
69    self.iobus = Bus(bus_id=0)
70    self.membus = MemBus(bus_id=1)
71    self.bridge = Bridge(delay='50ns', nack_delay='4ns')
72    self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
73    self.bridge.side_a = self.iobus.port
74    self.bridge.side_b = self.membus.port
75    self.physmem.port = self.membus.port
76    self.disk0 = CowIdeDisk(driveID='master')
77    self.disk2 = CowIdeDisk(driveID='master')
78    self.disk0.childImage(mdesc.disk())
79    self.disk2.childImage(disk('linux-bigswap2.img'))
80    self.tsunami = BaseTsunami()
81    self.tsunami.attachIO(self.iobus)
82    self.tsunami.ide.pio = self.iobus.port
83    self.tsunami.ethernet.pio = self.iobus.port
84    self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
85                                               read_only = True))
86    self.intrctrl = IntrControl()
87    self.mem_mode = mem_mode
88    self.terminal = Terminal()
89    self.kernel = binary('vmlinux')
90    self.pal = binary('ts_osfpal')
91    self.console = binary('console')
92    self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
93
94    return self
95
96def makeLinuxAlphaRubySystem(mem_mode, mdesc = None):
97    class BaseTsunami(Tsunami):
98        ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
99        ide = IdeController(disks=[Parent.disk0, Parent.disk2],
100                            pci_func=0, pci_dev=0, pci_bus=0)
101
102    physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
103    self = LinuxAlphaSystem(physmem = physmem)
104    if not mdesc:
105        # generic system
106        mdesc = SysConfig()
107    self.readfile = mdesc.script()
108
109    # Create pio bus to connect all device pio ports to rubymem's pio port
110    self.piobus = Bus(bus_id=0)
111
112    #
113    # Pio functional accesses from devices need direct access to memory
114    # RubyPort currently does support functional accesses.  Therefore provide
115    # the piobus a direct connection to physical memory
116    #
117    self.piobus.port = physmem.port
118
119    self.disk0 = CowIdeDisk(driveID='master')
120    self.disk2 = CowIdeDisk(driveID='master')
121    self.disk0.childImage(mdesc.disk())
122    self.disk2.childImage(disk('linux-bigswap2.img'))
123    self.tsunami = BaseTsunami()
124    self.tsunami.attachIO(self.piobus)
125    self.tsunami.ide.pio = self.piobus.port
126    self.tsunami.ethernet.pio = self.piobus.port
127
128    #
129    # Store the dma devices for later connection to dma ruby ports.
130    # Append an underscore to dma_devices to avoid the SimObjectVector check.
131    #
132    self._dma_devices = [self.tsunami.ide, self.tsunami.ethernet]
133
134    self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
135                                               read_only = True))
136    self.intrctrl = IntrControl()
137    self.mem_mode = mem_mode
138    self.terminal = Terminal()
139    self.kernel = binary('vmlinux')
140    self.pal = binary('ts_osfpal')
141    self.console = binary('console')
142    self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
143
144    return self
145
146def makeSparcSystem(mem_mode, mdesc = None):
147    class CowMmDisk(MmDisk):
148        image = CowDiskImage(child=RawDiskImage(read_only=True),
149                             read_only=False)
150
151        def childImage(self, ci):
152            self.image.child.image_file = ci
153
154    self = SparcSystem()
155    if not mdesc:
156        # generic system
157        mdesc = SysConfig()
158    self.readfile = mdesc.script()
159    self.iobus = Bus(bus_id=0)
160    self.membus = MemBus(bus_id=1)
161    self.bridge = Bridge(delay='50ns', nack_delay='4ns')
162    self.t1000 = T1000()
163    self.t1000.attachOnChipIO(self.membus)
164    self.t1000.attachIO(self.iobus)
165    self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True)
166    self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True)
167    self.bridge.side_a = self.iobus.port
168    self.bridge.side_b = self.membus.port
169    self.physmem.port = self.membus.port
170    self.physmem2.port = self.membus.port
171    self.rom.port = self.membus.port
172    self.nvram.port = self.membus.port
173    self.hypervisor_desc.port = self.membus.port
174    self.partition_desc.port = self.membus.port
175    self.intrctrl = IntrControl()
176    self.disk0 = CowMmDisk()
177    self.disk0.childImage(disk('disk.s10hw2'))
178    self.disk0.pio = self.iobus.port
179    self.reset_bin = binary('reset_new.bin')
180    self.hypervisor_bin = binary('q_new.bin')
181    self.openboot_bin = binary('openboot_new.bin')
182    self.nvram_bin = binary('nvram1')
183    self.hypervisor_desc_bin = binary('1up-hv.bin')
184    self.partition_desc_bin = binary('1up-md.bin')
185
186    return self
187
188def makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False):
189    assert machine_type
190
191    if bare_metal:
192        self = ArmSystem()
193    else:
194        self = LinuxArmSystem()
195
196    if not mdesc:
197        # generic system
198        mdesc = SysConfig()
199
200    self.readfile = mdesc.script()
201    self.iobus = Bus(bus_id=0)
202    self.membus = MemBus(bus_id=1)
203    self.membus.badaddr_responder.warn_access = "warn"
204    self.bridge = Bridge(delay='50ns', nack_delay='4ns')
205    self.bridge.side_a = self.iobus.port
206    self.bridge.side_b = self.membus.port
207
208    self.mem_mode = mem_mode
209
210    if machine_type == "RealView_PBX":
211        self.realview = RealViewPBX()
212    elif machine_type == "RealView_EB":
213        self.realview = RealViewEB()
214    elif machine_type == "VExpress_ELT":
215        self.realview = VExpress_ELT()
216    else:
217        print "Unknown Machine Type"
218        sys.exit(1)
219
220    self.cf0 = CowIdeDisk(driveID='master')
221    self.cf0.childImage(mdesc.disk())
222    # default to an IDE controller rather than a CF one
223    # assuming we've got one
224    try:
225        self.realview.ide.disks = [self.cf0]
226    except:
227        self.realview.cf_ctrl.disks = [self.cf0]
228
229    if bare_metal:
230        # EOT character on UART will end the simulation
231        self.realview.uart.end_on_eot = True
232        self.physmem = PhysicalMemory(range = AddrRange(Addr(mdesc.mem())),
233                                      zero = True)
234    else:
235        self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8')
236        self.machine_type = machine_type
237        if convert.toMemorySize(mdesc.mem()) > convert.toMemorySize('256MB'):
238            print "The currently implemented ARM platforms only easily support 256MB of DRAM"
239            print "It might be possible to get some more by using 256MB@0x30000000, but this"
240            print "is untested and may require some heroics"
241
242        boot_flags = 'earlyprintk console=ttyAMA0 lpj=19988480 norandmaps ' + \
243                     'rw loglevel=8 mem=%s root=/dev/sda1' % mdesc.mem()
244
245        self.physmem = PhysicalMemory(range = AddrRange(Addr(mdesc.mem())),
246                                      zero = True)
247        self.nvmem = PhysicalMemory(range = AddrRange(Addr('2GB'),
248                                    size = '64MB'), zero = True)
249        self.nvmem.port = self.membus.port
250        self.boot_loader = binary('boot.arm')
251        self.boot_loader_mem = self.nvmem
252        self.gic_cpu_addr = self.realview.gic.cpu_addr
253        self.flags_addr = self.realview.realview_io.pio_addr + 0x30
254
255        if mdesc.disk().lower().count('android'):
256            boot_flags += " init=/init "
257        self.boot_osflags = boot_flags
258
259    self.physmem.port = self.membus.port
260    self.realview.attachOnChipIO(self.membus)
261    self.realview.attachIO(self.iobus)
262    self.intrctrl = IntrControl()
263    self.terminal = Terminal()
264    self.vncserver = VncServer()
265
266    return self
267
268
269def makeLinuxMipsSystem(mem_mode, mdesc = None):
270    class BaseMalta(Malta):
271        ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
272        ide = IdeController(disks=[Parent.disk0, Parent.disk2],
273                            pci_func=0, pci_dev=0, pci_bus=0)
274
275    self = LinuxMipsSystem()
276    if not mdesc:
277        # generic system
278        mdesc = SysConfig()
279    self.readfile = mdesc.script()
280    self.iobus = Bus(bus_id=0)
281    self.membus = MemBus(bus_id=1)
282    self.bridge = Bridge(delay='50ns', nack_delay='4ns')
283    self.physmem = PhysicalMemory(range = AddrRange('1GB'))
284    self.bridge.side_a = self.iobus.port
285    self.bridge.side_b = self.membus.port
286    self.physmem.port = self.membus.port
287    self.disk0 = CowIdeDisk(driveID='master')
288    self.disk2 = CowIdeDisk(driveID='master')
289    self.disk0.childImage(mdesc.disk())
290    self.disk2.childImage(disk('linux-bigswap2.img'))
291    self.malta = BaseMalta()
292    self.malta.attachIO(self.iobus)
293    self.malta.ide.pio = self.iobus.port
294    self.malta.ethernet.pio = self.iobus.port
295    self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
296                                               read_only = True))
297    self.intrctrl = IntrControl()
298    self.mem_mode = mem_mode
299    self.terminal = Terminal()
300    self.kernel = binary('mips/vmlinux')
301    self.console = binary('mips/console')
302    self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
303
304    return self
305
306def x86IOAddress(port):
307    IO_address_space_base = 0x8000000000000000
308    return IO_address_space_base + port
309
310def connectX86ClassicSystem(x86_sys):
311    x86_sys.membus = MemBus(bus_id=1)
312    x86_sys.physmem.port = x86_sys.membus.port
313
314    # North Bridge
315    x86_sys.iobus = Bus(bus_id=0)
316    x86_sys.bridge = Bridge(delay='50ns', nack_delay='4ns')
317    x86_sys.bridge.side_a = x86_sys.iobus.port
318    x86_sys.bridge.side_b = x86_sys.membus.port
319
320    # connect the io bus
321    x86_sys.pc.attachIO(x86_sys.iobus)
322
323def connectX86RubySystem(x86_sys):
324    # North Bridge
325    x86_sys.piobus = Bus(bus_id=0)
326
327    #
328    # Pio functional accesses from devices need direct access to memory
329    # RubyPort currently does support functional accesses.  Therefore provide
330    # the piobus a direct connection to physical memory
331    #
332    x86_sys.piobus.port = x86_sys.physmem.port
333
334    x86_sys.pc.attachIO(x86_sys.piobus)
335
336
337def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None, Ruby = False):
338    if self == None:
339        self = X86System()
340
341    if not mdesc:
342        # generic system
343        mdesc = SysConfig()
344    self.readfile = mdesc.script()
345
346    self.mem_mode = mem_mode
347
348    # Physical memory
349    self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
350
351    # Platform
352    self.pc = Pc()
353
354    # Create and connect the busses required by each memory system
355    if Ruby:
356        connectX86RubySystem(self)
357        # add the ide to the list of dma devices that later need to attach to
358        # dma controllers
359        self._dma_devices = [self.pc.south_bridge.ide]
360    else:
361        connectX86ClassicSystem(self)
362
363    self.intrctrl = IntrControl()
364
365    # Disks
366    disk0 = CowIdeDisk(driveID='master')
367    disk2 = CowIdeDisk(driveID='master')
368    disk0.childImage(mdesc.disk())
369    disk2.childImage(disk('linux-bigswap2.img'))
370    self.pc.south_bridge.ide.disks = [disk0, disk2]
371
372    # Add in a Bios information structure.
373    structures = [X86SMBiosBiosInformation()]
374    self.smbios_table.structures = structures
375
376    # Set up the Intel MP table
377    base_entries = []
378    ext_entries = []
379    for i in xrange(numCPUs):
380        bp = X86IntelMPProcessor(
381                local_apic_id = i,
382                local_apic_version = 0x14,
383                enable = True,
384                bootstrap = (i == 0))
385        base_entries.append(bp)
386    io_apic = X86IntelMPIOAPIC(
387            id = numCPUs,
388            version = 0x11,
389            enable = True,
390            address = 0xfec00000)
391    self.pc.south_bridge.io_apic.apic_id = io_apic.id
392    base_entries.append(io_apic)
393    isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA')
394    base_entries.append(isa_bus)
395    pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI')
396    base_entries.append(pci_bus)
397    connect_busses = X86IntelMPBusHierarchy(bus_id=0,
398            subtractive_decode=True, parent_bus=1)
399    ext_entries.append(connect_busses)
400    pci_dev4_inta = X86IntelMPIOIntAssignment(
401            interrupt_type = 'INT',
402            polarity = 'ConformPolarity',
403            trigger = 'ConformTrigger',
404            source_bus_id = 1,
405            source_bus_irq = 0 + (4 << 2),
406            dest_io_apic_id = io_apic.id,
407            dest_io_apic_intin = 16)
408    base_entries.append(pci_dev4_inta)
409    def assignISAInt(irq, apicPin):
410        assign_8259_to_apic = X86IntelMPIOIntAssignment(
411                interrupt_type = 'ExtInt',
412                polarity = 'ConformPolarity',
413                trigger = 'ConformTrigger',
414                source_bus_id = 0,
415                source_bus_irq = irq,
416                dest_io_apic_id = io_apic.id,
417                dest_io_apic_intin = 0)
418        base_entries.append(assign_8259_to_apic)
419        assign_to_apic = X86IntelMPIOIntAssignment(
420                interrupt_type = 'INT',
421                polarity = 'ConformPolarity',
422                trigger = 'ConformTrigger',
423                source_bus_id = 0,
424                source_bus_irq = irq,
425                dest_io_apic_id = io_apic.id,
426                dest_io_apic_intin = apicPin)
427        base_entries.append(assign_to_apic)
428    assignISAInt(0, 2)
429    assignISAInt(1, 1)
430    for i in range(3, 15):
431        assignISAInt(i, i)
432    self.intel_mp_table.base_entries = base_entries
433    self.intel_mp_table.ext_entries = ext_entries
434
435def setWorkCountOptions(system, options):
436    if options.work_item_id != None:
437        system.work_item_id = options.work_item_id
438    if options.work_begin_cpu_id_exit != None:
439        system.work_begin_cpu_id_exit = options.work_begin_cpu_id_exit
440    if options.work_end_exit_count != None:
441        system.work_end_exit_count = options.work_end_exit_count
442    if options.work_end_checkpoint_count != None:
443        system.work_end_ckpt_count = options.work_end_checkpoint_count
444    if options.work_begin_exit_count != None:
445        system.work_begin_exit_count = options.work_begin_exit_count
446    if options.work_begin_checkpoint_count != None:
447        system.work_begin_ckpt_count = options.work_begin_checkpoint_count
448    if options.work_cpus_checkpoint_count != None:
449        system.work_cpus_ckpt_count = options.work_cpus_checkpoint_count
450
451
452def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None, Ruby = False):
453    self = LinuxX86System()
454
455    # Build up the x86 system and then specialize it for Linux
456    makeX86System(mem_mode, numCPUs, mdesc, self, Ruby)
457
458    # We assume below that there's at least 1MB of memory. We'll require 2
459    # just to avoid corner cases.
460    assert(self.physmem.range.second.getValue() >= 0x200000)
461
462    self.e820_table.entries = \
463       [
464        # Mark the first megabyte of memory as reserved
465        X86E820Entry(addr = 0, size = '1MB', range_type = 2),
466        # Mark the rest as available
467        X86E820Entry(addr = 0x100000,
468                size = '%dB' % (self.physmem.range.second - 0x100000 + 1),
469                range_type = 1)
470        ]
471
472    # Command line
473    self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \
474                        'root=/dev/hda1'
475    return self
476
477
478def makeDualRoot(testSystem, driveSystem, dumpfile):
479    self = Root()
480    self.testsys = testSystem
481    self.drivesys = driveSystem
482    self.etherlink = EtherLink()
483    self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
484    self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
485
486    if hasattr(testSystem, 'realview'):
487        self.etherlink.int0 = Parent.testsys.realview.ethernet.interface
488        self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface
489    elif hasattr(testSystem, 'tsunami'):
490        self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
491        self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
492    else:
493        fatal("Don't know how to connect these system together")
494
495    if dumpfile:
496        self.etherdump = EtherDump(file=dumpfile)
497        self.etherlink.dump = Parent.etherdump
498
499    return self
500
501def setMipsOptions(TestCPUClass):
502        #CP0 Configuration
503        TestCPUClass.CoreParams.CP0_PRId_CompanyOptions = 0
504        TestCPUClass.CoreParams.CP0_PRId_CompanyID = 1
505        TestCPUClass.CoreParams.CP0_PRId_ProcessorID = 147
506        TestCPUClass.CoreParams.CP0_PRId_Revision = 0
507
508        #CP0 Interrupt Control
509        TestCPUClass.CoreParams.CP0_IntCtl_IPTI = 7
510        TestCPUClass.CoreParams.CP0_IntCtl_IPPCI = 7
511
512        # Config Register
513        #TestCPUClass.CoreParams.CP0_Config_K23 = 0 # Since TLB
514        #TestCPUClass.CoreParams.CP0_Config_KU = 0 # Since TLB
515        TestCPUClass.CoreParams.CP0_Config_BE = 0 # Little Endian
516        TestCPUClass.CoreParams.CP0_Config_AR = 1 # Architecture Revision 2
517        TestCPUClass.CoreParams.CP0_Config_AT = 0 # MIPS32
518        TestCPUClass.CoreParams.CP0_Config_MT = 1 # TLB MMU
519        #TestCPUClass.CoreParams.CP0_Config_K0 = 2 # Uncached
520
521        #Config 1 Register
522        TestCPUClass.CoreParams.CP0_Config1_M = 1 # Config2 Implemented
523        TestCPUClass.CoreParams.CP0_Config1_MMU = 63 # TLB Size
524        # ***VERY IMPORTANT***
525        # Remember to modify CP0_Config1 according to cache specs
526        # Examine file ../common/Cache.py
527        TestCPUClass.CoreParams.CP0_Config1_IS = 1 # I-Cache Sets Per Way, 16KB cache, i.e., 1 (128)
528        TestCPUClass.CoreParams.CP0_Config1_IL = 5 # I-Cache Line Size, default in Cache.py is 64, i.e 5
529        TestCPUClass.CoreParams.CP0_Config1_IA = 1 # I-Cache Associativity, default in Cache.py is 2, i.e, a value of 1
530        TestCPUClass.CoreParams.CP0_Config1_DS = 2 # D-Cache Sets Per Way (see below), 32KB cache, i.e., 2
531        TestCPUClass.CoreParams.CP0_Config1_DL = 5 # D-Cache Line Size, default is 64, i.e., 5
532        TestCPUClass.CoreParams.CP0_Config1_DA = 1 # D-Cache Associativity, default is 2, i.e. 1
533        TestCPUClass.CoreParams.CP0_Config1_C2 = 0 # Coprocessor 2 not implemented(?)
534        TestCPUClass.CoreParams.CP0_Config1_MD = 0 # MDMX ASE not implemented in Mips32
535        TestCPUClass.CoreParams.CP0_Config1_PC = 1 # Performance Counters Implemented
536        TestCPUClass.CoreParams.CP0_Config1_WR = 0 # Watch Registers Implemented
537        TestCPUClass.CoreParams.CP0_Config1_CA = 0 # Mips16e NOT implemented
538        TestCPUClass.CoreParams.CP0_Config1_EP = 0 # EJTag Not Implemented
539        TestCPUClass.CoreParams.CP0_Config1_FP = 0 # FPU Implemented
540
541        #Config 2 Register
542        TestCPUClass.CoreParams.CP0_Config2_M = 1 # Config3 Implemented
543        TestCPUClass.CoreParams.CP0_Config2_TU = 0 # Tertiary Cache Control
544        TestCPUClass.CoreParams.CP0_Config2_TS = 0 # Tertiary Cache Sets Per Way
545        TestCPUClass.CoreParams.CP0_Config2_TL = 0 # Tertiary Cache Line Size
546        TestCPUClass.CoreParams.CP0_Config2_TA = 0 # Tertiary Cache Associativity
547        TestCPUClass.CoreParams.CP0_Config2_SU = 0 # Secondary Cache Control
548        TestCPUClass.CoreParams.CP0_Config2_SS = 0 # Secondary Cache Sets Per Way
549        TestCPUClass.CoreParams.CP0_Config2_SL = 0 # Secondary Cache Line Size
550        TestCPUClass.CoreParams.CP0_Config2_SA = 0 # Secondary Cache Associativity
551
552
553        #Config 3 Register
554        TestCPUClass.CoreParams.CP0_Config3_M = 0 # Config4 Not Implemented
555        TestCPUClass.CoreParams.CP0_Config3_DSPP = 1 # DSP ASE Present
556        TestCPUClass.CoreParams.CP0_Config3_LPA = 0 # Large Physical Addresses Not supported in Mips32
557        TestCPUClass.CoreParams.CP0_Config3_VEIC = 0 # EIC Supported
558        TestCPUClass.CoreParams.CP0_Config3_VInt = 0 # Vectored Interrupts Implemented
559        TestCPUClass.CoreParams.CP0_Config3_SP = 0 # Small Pages Supported (PageGrain reg. exists)
560        TestCPUClass.CoreParams.CP0_Config3_MT = 0 # MT Not present
561        TestCPUClass.CoreParams.CP0_Config3_SM = 0 # SmartMIPS ASE Not implemented
562        TestCPUClass.CoreParams.CP0_Config3_TL = 0 # TraceLogic Not implemented
563
564        #SRS Ctl - HSS
565        TestCPUClass.CoreParams.CP0_SrsCtl_HSS = 3 # Four shadow register sets implemented
566
567
568        #TestCPUClass.CoreParams.tlb = TLB()
569        #TestCPUClass.CoreParams.UnifiedTLB = 1
570