FSConfig.py revision 7750:0731d632db76
1# Copyright (c) 2010 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2006-2008 The Regents of The University of Michigan 14# All rights reserved. 15# 16# Redistribution and use in source and binary forms, with or without 17# modification, are permitted provided that the following conditions are 18# met: redistributions of source code must retain the above copyright 19# notice, this list of conditions and the following disclaimer; 20# redistributions in binary form must reproduce the above copyright 21# notice, this list of conditions and the following disclaimer in the 22# documentation and/or other materials provided with the distribution; 23# neither the name of the copyright holders nor the names of its 24# contributors may be used to endorse or promote products derived from 25# this software without specific prior written permission. 26# 27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38# 39# Authors: Kevin Lim 40 41from m5.objects import * 42from Benchmarks import * 43 44class CowIdeDisk(IdeDisk): 45 image = CowDiskImage(child=RawDiskImage(read_only=True), 46 read_only=False) 47 48 def childImage(self, ci): 49 self.image.child.image_file = ci 50 51class MemBus(Bus): 52 badaddr_responder = BadAddr() 53 default = Self.badaddr_responder.pio 54 55 56def makeLinuxAlphaSystem(mem_mode, mdesc = None): 57 class BaseTsunami(Tsunami): 58 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 59 ide = IdeController(disks=[Parent.disk0, Parent.disk2], 60 pci_func=0, pci_dev=0, pci_bus=0) 61 62 self = LinuxAlphaSystem() 63 if not mdesc: 64 # generic system 65 mdesc = SysConfig() 66 self.readfile = mdesc.script() 67 self.iobus = Bus(bus_id=0) 68 self.membus = MemBus(bus_id=1) 69 self.bridge = Bridge(delay='50ns', nack_delay='4ns') 70 self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) 71 self.bridge.side_a = self.iobus.port 72 self.bridge.side_b = self.membus.port 73 self.physmem.port = self.membus.port 74 self.disk0 = CowIdeDisk(driveID='master') 75 self.disk2 = CowIdeDisk(driveID='master') 76 self.disk0.childImage(mdesc.disk()) 77 self.disk2.childImage(disk('linux-bigswap2.img')) 78 self.tsunami = BaseTsunami() 79 self.tsunami.attachIO(self.iobus) 80 self.tsunami.ide.pio = self.iobus.port 81 self.tsunami.ethernet.pio = self.iobus.port 82 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 83 read_only = True)) 84 self.intrctrl = IntrControl() 85 self.mem_mode = mem_mode 86 self.terminal = Terminal() 87 self.kernel = binary('vmlinux') 88 self.pal = binary('ts_osfpal') 89 self.console = binary('console') 90 self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 91 92 return self 93 94def makeLinuxAlphaRubySystem(mem_mode, mdesc = None): 95 class BaseTsunami(Tsunami): 96 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 97 ide = IdeController(disks=[Parent.disk0, Parent.disk2], 98 pci_func=0, pci_dev=0, pci_bus=0) 99 100 physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) 101 self = LinuxAlphaSystem(physmem = physmem) 102 if not mdesc: 103 # generic system 104 mdesc = SysConfig() 105 self.readfile = mdesc.script() 106 107 # Create pio bus to connect all device pio ports to rubymem's pio port 108 self.piobus = Bus(bus_id=0) 109 110 # 111 # Pio functional accesses from devices need direct access to memory 112 # RubyPort currently does support functional accesses. Therefore provide 113 # the piobus a direct connection to physical memory 114 # 115 self.piobus.port = physmem.port 116 117 self.disk0 = CowIdeDisk(driveID='master') 118 self.disk2 = CowIdeDisk(driveID='master') 119 self.disk0.childImage(mdesc.disk()) 120 self.disk2.childImage(disk('linux-bigswap2.img')) 121 self.tsunami = BaseTsunami() 122 self.tsunami.attachIO(self.piobus) 123 self.tsunami.ide.pio = self.piobus.port 124 self.tsunami.ethernet.pio = self.piobus.port 125 126 # 127 # Store the dma devices for later connection to dma ruby ports. 128 # Append an underscore to dma_devices to avoid the SimObjectVector check. 129 # 130 self._dma_devices = [self.tsunami.ide, self.tsunami.ethernet] 131 132 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 133 read_only = True)) 134 self.intrctrl = IntrControl() 135 self.mem_mode = mem_mode 136 self.terminal = Terminal() 137 self.kernel = binary('vmlinux') 138 self.pal = binary('ts_osfpal') 139 self.console = binary('console') 140 self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 141 142 return self 143 144def makeSparcSystem(mem_mode, mdesc = None): 145 class CowMmDisk(MmDisk): 146 image = CowDiskImage(child=RawDiskImage(read_only=True), 147 read_only=False) 148 149 def childImage(self, ci): 150 self.image.child.image_file = ci 151 152 self = SparcSystem() 153 if not mdesc: 154 # generic system 155 mdesc = SysConfig() 156 self.readfile = mdesc.script() 157 self.iobus = Bus(bus_id=0) 158 self.membus = MemBus(bus_id=1) 159 self.bridge = Bridge(delay='50ns', nack_delay='4ns') 160 self.t1000 = T1000() 161 self.t1000.attachOnChipIO(self.membus) 162 self.t1000.attachIO(self.iobus) 163 self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True) 164 self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True) 165 self.bridge.side_a = self.iobus.port 166 self.bridge.side_b = self.membus.port 167 self.physmem.port = self.membus.port 168 self.physmem2.port = self.membus.port 169 self.rom.port = self.membus.port 170 self.nvram.port = self.membus.port 171 self.hypervisor_desc.port = self.membus.port 172 self.partition_desc.port = self.membus.port 173 self.intrctrl = IntrControl() 174 self.disk0 = CowMmDisk() 175 self.disk0.childImage(disk('disk.s10hw2')) 176 self.disk0.pio = self.iobus.port 177 self.reset_bin = binary('reset_new.bin') 178 self.hypervisor_bin = binary('q_new.bin') 179 self.openboot_bin = binary('openboot_new.bin') 180 self.nvram_bin = binary('nvram1') 181 self.hypervisor_desc_bin = binary('1up-hv.bin') 182 self.partition_desc_bin = binary('1up-md.bin') 183 184 return self 185 186def makeLinuxArmSystem(mem_mode, mdesc = None, bare_metal=False, 187 machine_type = None): 188 if bare_metal: 189 self = ArmSystem() 190 else: 191 self = LinuxArmSystem() 192 193 if not mdesc: 194 # generic system 195 mdesc = SysConfig() 196 197 self.readfile = mdesc.script() 198 self.iobus = Bus(bus_id=0) 199 self.membus = MemBus(bus_id=1) 200 self.membus.badaddr_responder.warn_access = "warn" 201 self.bridge = Bridge(delay='50ns', nack_delay='4ns') 202 self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()), zero = True) 203 self.diskmem = PhysicalMemory(range = AddrRange(Addr('128MB'), size = '128MB'), 204 file = disk('ael-arm.ext2')) 205 self.bridge.side_a = self.iobus.port 206 self.bridge.side_b = self.membus.port 207 self.physmem.port = self.membus.port 208 self.diskmem.port = self.membus.port 209 210 self.mem_mode = mem_mode 211 212 #self.cf0 = CowIdeDisk(driveID='master') 213 #self.cf0.childImage(mdesc.disk()) 214 #self.cf_ctrl = IdeController(disks=[self.cf0], 215 # pci_func = 0, pci_dev = 0, pci_bus = 0, 216 # io_shift = 1, ctrl_offset = 2, Command = 0x1, 217 # BAR0 = 0x18000000, BAR0Size = '16B', 218 # BAR1 = 0x18000100, BAR1Size = '1B', 219 # BAR0LegacyIO = True, BAR1LegacyIO = True,) 220 #self.cf_ctrl.pio = self.iobus.port 221 222 if machine_type == "RealView_PBX": 223 self.realview = RealViewPBX() 224 elif machine_type == "RealView_EB": 225 self.realview = RealViewEB() 226 else: 227 print "Unknown Machine Type" 228 sys.exit(1) 229 230 if not bare_metal and machine_type: 231 self.machine_type = machine_type 232 elif bare_metal: 233 self.realview.uart.end_on_eot = True 234 235 self.realview.attachOnChipIO(self.membus) 236 self.realview.attachIO(self.iobus) 237 238 self.intrctrl = IntrControl() 239 self.terminal = Terminal() 240 self.kernel = binary('vmlinux.arm') 241 self.boot_osflags = 'earlyprintk mem=128MB console=ttyAMA0 lpj=19988480' + \ 242 ' norandmaps slram=slram0,0x8000000,+0x8000000' + \ 243 ' mtdparts=slram0:- rw loglevel=8 root=/dev/mtdblock0' 244 245 return self 246 247 248def makeLinuxMipsSystem(mem_mode, mdesc = None): 249 class BaseMalta(Malta): 250 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 251 ide = IdeController(disks=[Parent.disk0, Parent.disk2], 252 pci_func=0, pci_dev=0, pci_bus=0) 253 254 self = LinuxMipsSystem() 255 if not mdesc: 256 # generic system 257 mdesc = SysConfig() 258 self.readfile = mdesc.script() 259 self.iobus = Bus(bus_id=0) 260 self.membus = MemBus(bus_id=1) 261 self.bridge = Bridge(delay='50ns', nack_delay='4ns') 262 self.physmem = PhysicalMemory(range = AddrRange('1GB')) 263 self.bridge.side_a = self.iobus.port 264 self.bridge.side_b = self.membus.port 265 self.physmem.port = self.membus.port 266 self.disk0 = CowIdeDisk(driveID='master') 267 self.disk2 = CowIdeDisk(driveID='master') 268 self.disk0.childImage(mdesc.disk()) 269 self.disk2.childImage(disk('linux-bigswap2.img')) 270 self.malta = BaseMalta() 271 self.malta.attachIO(self.iobus) 272 self.malta.ide.pio = self.iobus.port 273 self.malta.ethernet.pio = self.iobus.port 274 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 275 read_only = True)) 276 self.intrctrl = IntrControl() 277 self.mem_mode = mem_mode 278 self.terminal = Terminal() 279 self.kernel = binary('mips/vmlinux') 280 self.console = binary('mips/console') 281 self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 282 283 return self 284 285def x86IOAddress(port): 286 IO_address_space_base = 0x8000000000000000 287 return IO_address_space_base + port; 288 289def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None): 290 if self == None: 291 self = X86System() 292 293 if not mdesc: 294 # generic system 295 mdesc = SysConfig() 296 mdesc.diskname = 'x86root.img' 297 self.readfile = mdesc.script() 298 299 self.mem_mode = mem_mode 300 301 # Physical memory 302 self.membus = MemBus(bus_id=1) 303 self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) 304 self.physmem.port = self.membus.port 305 306 # North Bridge 307 self.iobus = Bus(bus_id=0) 308 self.bridge = Bridge(delay='50ns', nack_delay='4ns') 309 self.bridge.side_a = self.iobus.port 310 self.bridge.side_b = self.membus.port 311 312 # Platform 313 self.pc = Pc() 314 self.pc.attachIO(self.iobus) 315 316 self.intrctrl = IntrControl() 317 318 # Disks 319 disk0 = CowIdeDisk(driveID='master') 320 disk2 = CowIdeDisk(driveID='master') 321 disk0.childImage(mdesc.disk()) 322 disk2.childImage(disk('linux-bigswap2.img')) 323 self.pc.south_bridge.ide.disks = [disk0, disk2] 324 325 # Add in a Bios information structure. 326 structures = [X86SMBiosBiosInformation()] 327 self.smbios_table.structures = structures 328 329 # Set up the Intel MP table 330 for i in xrange(numCPUs): 331 bp = X86IntelMPProcessor( 332 local_apic_id = i, 333 local_apic_version = 0x14, 334 enable = True, 335 bootstrap = (i == 0)) 336 self.intel_mp_table.add_entry(bp) 337 io_apic = X86IntelMPIOAPIC( 338 id = numCPUs, 339 version = 0x11, 340 enable = True, 341 address = 0xfec00000) 342 self.pc.south_bridge.io_apic.apic_id = io_apic.id 343 self.intel_mp_table.add_entry(io_apic) 344 isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA') 345 self.intel_mp_table.add_entry(isa_bus) 346 pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI') 347 self.intel_mp_table.add_entry(pci_bus) 348 connect_busses = X86IntelMPBusHierarchy(bus_id=0, 349 subtractive_decode=True, parent_bus=1) 350 self.intel_mp_table.add_entry(connect_busses) 351 pci_dev4_inta = X86IntelMPIOIntAssignment( 352 interrupt_type = 'INT', 353 polarity = 'ConformPolarity', 354 trigger = 'ConformTrigger', 355 source_bus_id = 1, 356 source_bus_irq = 0 + (4 << 2), 357 dest_io_apic_id = io_apic.id, 358 dest_io_apic_intin = 16) 359 self.intel_mp_table.add_entry(pci_dev4_inta); 360 def assignISAInt(irq, apicPin): 361 assign_8259_to_apic = X86IntelMPIOIntAssignment( 362 interrupt_type = 'ExtInt', 363 polarity = 'ConformPolarity', 364 trigger = 'ConformTrigger', 365 source_bus_id = 0, 366 source_bus_irq = irq, 367 dest_io_apic_id = io_apic.id, 368 dest_io_apic_intin = 0) 369 self.intel_mp_table.add_entry(assign_8259_to_apic) 370 assign_to_apic = X86IntelMPIOIntAssignment( 371 interrupt_type = 'INT', 372 polarity = 'ConformPolarity', 373 trigger = 'ConformTrigger', 374 source_bus_id = 0, 375 source_bus_irq = irq, 376 dest_io_apic_id = io_apic.id, 377 dest_io_apic_intin = apicPin) 378 self.intel_mp_table.add_entry(assign_to_apic) 379 assignISAInt(0, 2) 380 assignISAInt(1, 1) 381 for i in range(3, 15): 382 assignISAInt(i, i) 383 384 385def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None): 386 self = LinuxX86System() 387 388 # Build up a generic x86 system and then specialize it for Linux 389 makeX86System(mem_mode, numCPUs, mdesc, self) 390 391 # We assume below that there's at least 1MB of memory. We'll require 2 392 # just to avoid corner cases. 393 assert(self.physmem.range.second.getValue() >= 0x200000) 394 395 # Mark the first megabyte of memory as reserved 396 self.e820_table.entries.append(X86E820Entry( 397 addr = 0, 398 size = '1MB', 399 range_type = 2)) 400 401 # Mark the rest as available 402 self.e820_table.entries.append(X86E820Entry( 403 addr = 0x100000, 404 size = '%dB' % (self.physmem.range.second - 0x100000 + 1), 405 range_type = 1)) 406 407 # Command line 408 self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \ 409 'root=/dev/hda1' 410 return self 411 412 413def makeDualRoot(testSystem, driveSystem, dumpfile): 414 self = Root() 415 self.testsys = testSystem 416 self.drivesys = driveSystem 417 self.etherlink = EtherLink() 418 self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 419 self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 420 421 if dumpfile: 422 self.etherdump = EtherDump(file=dumpfile) 423 self.etherlink.dump = Parent.etherdump 424 425 return self 426 427def setMipsOptions(TestCPUClass): 428 #CP0 Configuration 429 TestCPUClass.CoreParams.CP0_PRId_CompanyOptions = 0 430 TestCPUClass.CoreParams.CP0_PRId_CompanyID = 1 431 TestCPUClass.CoreParams.CP0_PRId_ProcessorID = 147 432 TestCPUClass.CoreParams.CP0_PRId_Revision = 0 433 434 #CP0 Interrupt Control 435 TestCPUClass.CoreParams.CP0_IntCtl_IPTI = 7 436 TestCPUClass.CoreParams.CP0_IntCtl_IPPCI = 7 437 438 # Config Register 439 #TestCPUClass.CoreParams.CP0_Config_K23 = 0 # Since TLB 440 #TestCPUClass.CoreParams.CP0_Config_KU = 0 # Since TLB 441 TestCPUClass.CoreParams.CP0_Config_BE = 0 # Little Endian 442 TestCPUClass.CoreParams.CP0_Config_AR = 1 # Architecture Revision 2 443 TestCPUClass.CoreParams.CP0_Config_AT = 0 # MIPS32 444 TestCPUClass.CoreParams.CP0_Config_MT = 1 # TLB MMU 445 #TestCPUClass.CoreParams.CP0_Config_K0 = 2 # Uncached 446 447 #Config 1 Register 448 TestCPUClass.CoreParams.CP0_Config1_M = 1 # Config2 Implemented 449 TestCPUClass.CoreParams.CP0_Config1_MMU = 63 # TLB Size 450 # ***VERY IMPORTANT*** 451 # Remember to modify CP0_Config1 according to cache specs 452 # Examine file ../common/Cache.py 453 TestCPUClass.CoreParams.CP0_Config1_IS = 1 # I-Cache Sets Per Way, 16KB cache, i.e., 1 (128) 454 TestCPUClass.CoreParams.CP0_Config1_IL = 5 # I-Cache Line Size, default in Cache.py is 64, i.e 5 455 TestCPUClass.CoreParams.CP0_Config1_IA = 1 # I-Cache Associativity, default in Cache.py is 2, i.e, a value of 1 456 TestCPUClass.CoreParams.CP0_Config1_DS = 2 # D-Cache Sets Per Way (see below), 32KB cache, i.e., 2 457 TestCPUClass.CoreParams.CP0_Config1_DL = 5 # D-Cache Line Size, default is 64, i.e., 5 458 TestCPUClass.CoreParams.CP0_Config1_DA = 1 # D-Cache Associativity, default is 2, i.e. 1 459 TestCPUClass.CoreParams.CP0_Config1_C2 = 0 # Coprocessor 2 not implemented(?) 460 TestCPUClass.CoreParams.CP0_Config1_MD = 0 # MDMX ASE not implemented in Mips32 461 TestCPUClass.CoreParams.CP0_Config1_PC = 1 # Performance Counters Implemented 462 TestCPUClass.CoreParams.CP0_Config1_WR = 0 # Watch Registers Implemented 463 TestCPUClass.CoreParams.CP0_Config1_CA = 0 # Mips16e NOT implemented 464 TestCPUClass.CoreParams.CP0_Config1_EP = 0 # EJTag Not Implemented 465 TestCPUClass.CoreParams.CP0_Config1_FP = 0 # FPU Implemented 466 467 #Config 2 Register 468 TestCPUClass.CoreParams.CP0_Config2_M = 1 # Config3 Implemented 469 TestCPUClass.CoreParams.CP0_Config2_TU = 0 # Tertiary Cache Control 470 TestCPUClass.CoreParams.CP0_Config2_TS = 0 # Tertiary Cache Sets Per Way 471 TestCPUClass.CoreParams.CP0_Config2_TL = 0 # Tertiary Cache Line Size 472 TestCPUClass.CoreParams.CP0_Config2_TA = 0 # Tertiary Cache Associativity 473 TestCPUClass.CoreParams.CP0_Config2_SU = 0 # Secondary Cache Control 474 TestCPUClass.CoreParams.CP0_Config2_SS = 0 # Secondary Cache Sets Per Way 475 TestCPUClass.CoreParams.CP0_Config2_SL = 0 # Secondary Cache Line Size 476 TestCPUClass.CoreParams.CP0_Config2_SA = 0 # Secondary Cache Associativity 477 478 479 #Config 3 Register 480 TestCPUClass.CoreParams.CP0_Config3_M = 0 # Config4 Not Implemented 481 TestCPUClass.CoreParams.CP0_Config3_DSPP = 1 # DSP ASE Present 482 TestCPUClass.CoreParams.CP0_Config3_LPA = 0 # Large Physical Addresses Not supported in Mips32 483 TestCPUClass.CoreParams.CP0_Config3_VEIC = 0 # EIC Supported 484 TestCPUClass.CoreParams.CP0_Config3_VInt = 0 # Vectored Interrupts Implemented 485 TestCPUClass.CoreParams.CP0_Config3_SP = 0 # Small Pages Supported (PageGrain reg. exists) 486 TestCPUClass.CoreParams.CP0_Config3_MT = 0 # MT Not present 487 TestCPUClass.CoreParams.CP0_Config3_SM = 0 # SmartMIPS ASE Not implemented 488 TestCPUClass.CoreParams.CP0_Config3_TL = 0 # TraceLogic Not implemented 489 490 #SRS Ctl - HSS 491 TestCPUClass.CoreParams.CP0_SrsCtl_HSS = 3 # Four shadow register sets implemented 492 493 494 #TestCPUClass.CoreParams.tlb = TLB() 495 #TestCPUClass.CoreParams.UnifiedTLB = 1 496