FSConfig.py revision 7633:d8112aa18a1b 
1# Copyright (c) 2010 ARM Limited
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3#
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13# Copyright (c) 2006-2008 The Regents of The University of Michigan
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33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Kevin Lim
40
41from m5.objects import *
42from Benchmarks import *
43
44class CowIdeDisk(IdeDisk):
45    image = CowDiskImage(child=RawDiskImage(read_only=True),
46                         read_only=False)
47
48    def childImage(self, ci):
49        self.image.child.image_file = ci
50
51class MemBus(Bus):
52    badaddr_responder = BadAddr()
53    default = Self.badaddr_responder.pio
54
55
56def makeLinuxAlphaSystem(mem_mode, mdesc = None):
57    class BaseTsunami(Tsunami):
58        ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
59        ide = IdeController(disks=[Parent.disk0, Parent.disk2],
60                            pci_func=0, pci_dev=0, pci_bus=0)
61
62    self = LinuxAlphaSystem()
63    if not mdesc:
64        # generic system
65        mdesc = SysConfig()
66    self.readfile = mdesc.script()
67    self.iobus = Bus(bus_id=0)
68    self.membus = MemBus(bus_id=1)
69    self.bridge = Bridge(delay='50ns', nack_delay='4ns')
70    self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
71    self.bridge.side_a = self.iobus.port
72    self.bridge.side_b = self.membus.port
73    self.physmem.port = self.membus.port
74    self.disk0 = CowIdeDisk(driveID='master')
75    self.disk2 = CowIdeDisk(driveID='master')
76    self.disk0.childImage(mdesc.disk())
77    self.disk2.childImage(disk('linux-bigswap2.img'))
78    self.tsunami = BaseTsunami()
79    self.tsunami.attachIO(self.iobus)
80    self.tsunami.ide.pio = self.iobus.port
81    self.tsunami.ethernet.pio = self.iobus.port
82    self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
83                                               read_only = True))
84    self.intrctrl = IntrControl()
85    self.mem_mode = mem_mode
86    self.terminal = Terminal()
87    self.kernel = binary('vmlinux')
88    self.pal = binary('ts_osfpal')
89    self.console = binary('console')
90    self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
91
92    return self
93
94def makeLinuxAlphaRubySystem(mem_mode, mdesc = None):
95    class BaseTsunami(Tsunami):
96        ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
97        ide = IdeController(disks=[Parent.disk0, Parent.disk2],
98                            pci_func=0, pci_dev=0, pci_bus=0)
99
100    physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
101    self = LinuxAlphaSystem(physmem = physmem)
102    if not mdesc:
103        # generic system
104        mdesc = SysConfig()
105    self.readfile = mdesc.script()
106
107    # Create pio bus to connect all device pio ports to rubymem's pio port
108    self.piobus = Bus(bus_id=0)
109
110    #
111    # Pio functional accesses from devices need direct access to memory
112    # RubyPort currently does support functional accesses.  Therefore provide
113    # the piobus a direct connection to physical memory
114    #
115    self.piobus.port = physmem.port
116
117    self.disk0 = CowIdeDisk(driveID='master')
118    self.disk2 = CowIdeDisk(driveID='master')
119    self.disk0.childImage(mdesc.disk())
120    self.disk2.childImage(disk('linux-bigswap2.img'))
121    self.tsunami = BaseTsunami()
122    self.tsunami.attachIO(self.piobus)
123    self.tsunami.ide.pio = self.piobus.port
124    self.tsunami.ethernet.pio = self.piobus.port
125
126    #
127    # Store the dma devices for later connection to dma ruby ports.
128    # Append an underscore to dma_devices to avoid the SimObjectVector check.
129    #
130    self._dma_devices = [self.tsunami.ide, self.tsunami.ethernet]
131
132    self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
133                                               read_only = True))
134    self.intrctrl = IntrControl()
135    self.mem_mode = mem_mode
136    self.terminal = Terminal()
137    self.kernel = binary('vmlinux')
138    self.pal = binary('ts_osfpal')
139    self.console = binary('console')
140    self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
141
142    return self
143
144def makeSparcSystem(mem_mode, mdesc = None):
145    class CowMmDisk(MmDisk):
146        image = CowDiskImage(child=RawDiskImage(read_only=True),
147                             read_only=False)
148
149        def childImage(self, ci):
150            self.image.child.image_file = ci
151
152    self = SparcSystem()
153    if not mdesc:
154        # generic system
155        mdesc = SysConfig()
156    self.readfile = mdesc.script()
157    self.iobus = Bus(bus_id=0)
158    self.membus = MemBus(bus_id=1)
159    self.bridge = Bridge(delay='50ns', nack_delay='4ns')
160    self.t1000 = T1000()
161    self.t1000.attachOnChipIO(self.membus)
162    self.t1000.attachIO(self.iobus)
163    self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True)
164    self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True)
165    self.bridge.side_a = self.iobus.port
166    self.bridge.side_b = self.membus.port
167    self.physmem.port = self.membus.port
168    self.physmem2.port = self.membus.port
169    self.rom.port = self.membus.port
170    self.nvram.port = self.membus.port
171    self.hypervisor_desc.port = self.membus.port
172    self.partition_desc.port = self.membus.port
173    self.intrctrl = IntrControl()
174    self.disk0 = CowMmDisk()
175    self.disk0.childImage(disk('disk.s10hw2'))
176    self.disk0.pio = self.iobus.port
177    self.reset_bin = binary('reset_new.bin')
178    self.hypervisor_bin = binary('q_new.bin')
179    self.openboot_bin = binary('openboot_new.bin')
180    self.nvram_bin = binary('nvram1')
181    self.hypervisor_desc_bin = binary('1up-hv.bin')
182    self.partition_desc_bin = binary('1up-md.bin')
183
184    return self
185
186def makeLinuxArmSystem(mem_mode, mdesc = None, bare_metal=False,
187        machine_type = None):
188    if bare_metal:
189        self = ArmSystem()
190    else:
191        self = LinuxArmSystem()
192
193    if not mdesc:
194        # generic system
195        mdesc = SysConfig()
196
197    self.readfile = mdesc.script()
198    self.iobus = Bus(bus_id=0)
199    self.membus = MemBus(bus_id=1)
200    self.membus.badaddr_responder.warn_access = "warn"
201    self.bridge = Bridge(delay='50ns', nack_delay='4ns')
202    self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()), zero = True)
203    self.bridge.side_a = self.iobus.port
204    self.bridge.side_b = self.membus.port
205    self.physmem.port = self.membus.port
206
207    self.mem_mode = mem_mode
208
209    if machine_type == "RealView_PBX":
210        self.realview = RealViewPBX()
211    elif machine_type == "RealView_EB":
212        self.realview = RealViewEB()
213    else:
214        print "Unknown Machine Type"
215        sys.exit(1)
216
217    if not bare_metal and machine_type:
218        self.machine_type = machine_type
219    elif bare_metal:
220        self.realview.uart.end_on_eot = True
221
222    self.realview.attachOnChipIO(self.membus)
223    self.realview.attachIO(self.iobus)
224
225    self.intrctrl = IntrControl()
226    self.terminal = Terminal()
227    self.boot_osflags = 'earlyprintk mem=128MB console=ttyAMA0 lpj=19988480 norandmaps'
228
229    return self
230
231
232def makeLinuxMipsSystem(mem_mode, mdesc = None):
233    class BaseMalta(Malta):
234        ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
235        ide = IdeController(disks=[Parent.disk0, Parent.disk2],
236                            pci_func=0, pci_dev=0, pci_bus=0)
237
238    self = LinuxMipsSystem()
239    if not mdesc:
240        # generic system
241        mdesc = SysConfig()
242    self.readfile = mdesc.script()
243    self.iobus = Bus(bus_id=0)
244    self.membus = MemBus(bus_id=1)
245    self.bridge = Bridge(delay='50ns', nack_delay='4ns')
246    self.physmem = PhysicalMemory(range = AddrRange('1GB'))
247    self.bridge.side_a = self.iobus.port
248    self.bridge.side_b = self.membus.port
249    self.physmem.port = self.membus.port
250    self.disk0 = CowIdeDisk(driveID='master')
251    self.disk2 = CowIdeDisk(driveID='master')
252    self.disk0.childImage(mdesc.disk())
253    self.disk2.childImage(disk('linux-bigswap2.img'))
254    self.malta = BaseMalta()
255    self.malta.attachIO(self.iobus)
256    self.malta.ide.pio = self.iobus.port
257    self.malta.ethernet.pio = self.iobus.port
258    self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
259                                               read_only = True))
260    self.intrctrl = IntrControl()
261    self.mem_mode = mem_mode
262    self.terminal = Terminal()
263    self.kernel = binary('mips/vmlinux')
264    self.console = binary('mips/console')
265    self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
266
267    return self
268
269def x86IOAddress(port):
270    IO_address_space_base = 0x8000000000000000
271    return IO_address_space_base + port;
272
273def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None):
274    if self == None:
275        self = X86System()
276
277    if not mdesc:
278        # generic system
279        mdesc = SysConfig()
280    mdesc.diskname = 'x86root.img'
281    self.readfile = mdesc.script()
282
283    self.mem_mode = mem_mode
284
285    # Physical memory
286    self.membus = MemBus(bus_id=1)
287    self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
288    self.physmem.port = self.membus.port
289
290    # North Bridge
291    self.iobus = Bus(bus_id=0)
292    self.bridge = Bridge(delay='50ns', nack_delay='4ns')
293    self.bridge.side_a = self.iobus.port
294    self.bridge.side_b = self.membus.port
295
296    # Platform
297    self.pc = Pc()
298    self.pc.attachIO(self.iobus)
299
300    self.intrctrl = IntrControl()
301
302    # Disks
303    disk0 = CowIdeDisk(driveID='master')
304    disk2 = CowIdeDisk(driveID='master')
305    disk0.childImage(mdesc.disk())
306    disk2.childImage(disk('linux-bigswap2.img'))
307    self.pc.south_bridge.ide.disks = [disk0, disk2]
308
309    # Add in a Bios information structure.
310    structures = [X86SMBiosBiosInformation()]
311    self.smbios_table.structures = structures
312
313    # Set up the Intel MP table
314    for i in xrange(numCPUs):
315        bp = X86IntelMPProcessor(
316                local_apic_id = i,
317                local_apic_version = 0x14,
318                enable = True,
319                bootstrap = (i == 0))
320        self.intel_mp_table.add_entry(bp)
321    io_apic = X86IntelMPIOAPIC(
322            id = numCPUs,
323            version = 0x11,
324            enable = True,
325            address = 0xfec00000)
326    self.pc.south_bridge.io_apic.apic_id = io_apic.id
327    self.intel_mp_table.add_entry(io_apic)
328    isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA')
329    self.intel_mp_table.add_entry(isa_bus)
330    pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI')
331    self.intel_mp_table.add_entry(pci_bus)
332    connect_busses = X86IntelMPBusHierarchy(bus_id=0,
333            subtractive_decode=True, parent_bus=1)
334    self.intel_mp_table.add_entry(connect_busses)
335    pci_dev4_inta = X86IntelMPIOIntAssignment(
336            interrupt_type = 'INT',
337            polarity = 'ConformPolarity',
338            trigger = 'ConformTrigger',
339            source_bus_id = 1,
340            source_bus_irq = 0 + (4 << 2),
341            dest_io_apic_id = io_apic.id,
342            dest_io_apic_intin = 16)
343    self.intel_mp_table.add_entry(pci_dev4_inta);
344    def assignISAInt(irq, apicPin):
345        assign_8259_to_apic = X86IntelMPIOIntAssignment(
346                interrupt_type = 'ExtInt',
347                polarity = 'ConformPolarity',
348                trigger = 'ConformTrigger',
349                source_bus_id = 0,
350                source_bus_irq = irq,
351                dest_io_apic_id = io_apic.id,
352                dest_io_apic_intin = 0)
353        self.intel_mp_table.add_entry(assign_8259_to_apic)
354        assign_to_apic = X86IntelMPIOIntAssignment(
355                interrupt_type = 'INT',
356                polarity = 'ConformPolarity',
357                trigger = 'ConformTrigger',
358                source_bus_id = 0,
359                source_bus_irq = irq,
360                dest_io_apic_id = io_apic.id,
361                dest_io_apic_intin = apicPin)
362        self.intel_mp_table.add_entry(assign_to_apic)
363    assignISAInt(0, 2)
364    assignISAInt(1, 1)
365    for i in range(3, 15):
366        assignISAInt(i, i)
367
368
369def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None):
370    self = LinuxX86System()
371
372    # Build up a generic x86 system and then specialize it for Linux
373    makeX86System(mem_mode, numCPUs, mdesc, self)
374
375    # We assume below that there's at least 1MB of memory. We'll require 2
376    # just to avoid corner cases.
377    assert(self.physmem.range.second.getValue() >= 0x200000)
378
379    # Mark the first megabyte of memory as reserved
380    self.e820_table.entries.append(X86E820Entry(
381                addr = 0,
382                size = '1MB',
383                range_type = 2))
384
385    # Mark the rest as available
386    self.e820_table.entries.append(X86E820Entry(
387                addr = 0x100000,
388                size = '%dB' % (self.physmem.range.second - 0x100000 + 1),
389                range_type = 1))
390
391    # Command line
392    self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \
393                        'root=/dev/hda1'
394    return self
395
396
397def makeDualRoot(testSystem, driveSystem, dumpfile):
398    self = Root()
399    self.testsys = testSystem
400    self.drivesys = driveSystem
401    self.etherlink = EtherLink()
402    self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
403    self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
404
405    if dumpfile:
406        self.etherdump = EtherDump(file=dumpfile)
407        self.etherlink.dump = Parent.etherdump
408
409    return self
410
411def setMipsOptions(TestCPUClass):
412        #CP0 Configuration
413        TestCPUClass.CoreParams.CP0_PRId_CompanyOptions = 0
414        TestCPUClass.CoreParams.CP0_PRId_CompanyID = 1
415        TestCPUClass.CoreParams.CP0_PRId_ProcessorID = 147
416        TestCPUClass.CoreParams.CP0_PRId_Revision = 0
417
418        #CP0 Interrupt Control
419        TestCPUClass.CoreParams.CP0_IntCtl_IPTI = 7
420        TestCPUClass.CoreParams.CP0_IntCtl_IPPCI = 7
421
422        # Config Register
423        #TestCPUClass.CoreParams.CP0_Config_K23 = 0 # Since TLB
424        #TestCPUClass.CoreParams.CP0_Config_KU = 0 # Since TLB
425        TestCPUClass.CoreParams.CP0_Config_BE = 0 # Little Endian
426        TestCPUClass.CoreParams.CP0_Config_AR = 1 # Architecture Revision 2
427        TestCPUClass.CoreParams.CP0_Config_AT = 0 # MIPS32
428        TestCPUClass.CoreParams.CP0_Config_MT = 1 # TLB MMU
429        #TestCPUClass.CoreParams.CP0_Config_K0 = 2 # Uncached
430
431        #Config 1 Register
432        TestCPUClass.CoreParams.CP0_Config1_M = 1 # Config2 Implemented
433        TestCPUClass.CoreParams.CP0_Config1_MMU = 63 # TLB Size
434        # ***VERY IMPORTANT***
435        # Remember to modify CP0_Config1 according to cache specs
436        # Examine file ../common/Cache.py
437        TestCPUClass.CoreParams.CP0_Config1_IS = 1 # I-Cache Sets Per Way, 16KB cache, i.e., 1 (128)
438        TestCPUClass.CoreParams.CP0_Config1_IL = 5 # I-Cache Line Size, default in Cache.py is 64, i.e 5
439        TestCPUClass.CoreParams.CP0_Config1_IA = 1 # I-Cache Associativity, default in Cache.py is 2, i.e, a value of 1
440        TestCPUClass.CoreParams.CP0_Config1_DS = 2 # D-Cache Sets Per Way (see below), 32KB cache, i.e., 2
441        TestCPUClass.CoreParams.CP0_Config1_DL = 5 # D-Cache Line Size, default is 64, i.e., 5
442        TestCPUClass.CoreParams.CP0_Config1_DA = 1 # D-Cache Associativity, default is 2, i.e. 1
443        TestCPUClass.CoreParams.CP0_Config1_C2 = 0 # Coprocessor 2 not implemented(?)
444        TestCPUClass.CoreParams.CP0_Config1_MD = 0 # MDMX ASE not implemented in Mips32
445        TestCPUClass.CoreParams.CP0_Config1_PC = 1 # Performance Counters Implemented
446        TestCPUClass.CoreParams.CP0_Config1_WR = 0 # Watch Registers Implemented
447        TestCPUClass.CoreParams.CP0_Config1_CA = 0 # Mips16e NOT implemented
448        TestCPUClass.CoreParams.CP0_Config1_EP = 0 # EJTag Not Implemented
449        TestCPUClass.CoreParams.CP0_Config1_FP = 0 # FPU Implemented
450
451        #Config 2 Register
452        TestCPUClass.CoreParams.CP0_Config2_M = 1 # Config3 Implemented
453        TestCPUClass.CoreParams.CP0_Config2_TU = 0 # Tertiary Cache Control
454        TestCPUClass.CoreParams.CP0_Config2_TS = 0 # Tertiary Cache Sets Per Way
455        TestCPUClass.CoreParams.CP0_Config2_TL = 0 # Tertiary Cache Line Size
456        TestCPUClass.CoreParams.CP0_Config2_TA = 0 # Tertiary Cache Associativity
457        TestCPUClass.CoreParams.CP0_Config2_SU = 0 # Secondary Cache Control
458        TestCPUClass.CoreParams.CP0_Config2_SS = 0 # Secondary Cache Sets Per Way
459        TestCPUClass.CoreParams.CP0_Config2_SL = 0 # Secondary Cache Line Size
460        TestCPUClass.CoreParams.CP0_Config2_SA = 0 # Secondary Cache Associativity
461
462
463        #Config 3 Register
464        TestCPUClass.CoreParams.CP0_Config3_M = 0 # Config4 Not Implemented
465        TestCPUClass.CoreParams.CP0_Config3_DSPP = 1 # DSP ASE Present
466        TestCPUClass.CoreParams.CP0_Config3_LPA = 0 # Large Physical Addresses Not supported in Mips32
467        TestCPUClass.CoreParams.CP0_Config3_VEIC = 0 # EIC Supported
468        TestCPUClass.CoreParams.CP0_Config3_VInt = 0 # Vectored Interrupts Implemented
469        TestCPUClass.CoreParams.CP0_Config3_SP = 0 # Small Pages Supported (PageGrain reg. exists)
470        TestCPUClass.CoreParams.CP0_Config3_MT = 0 # MT Not present
471        TestCPUClass.CoreParams.CP0_Config3_SM = 0 # SmartMIPS ASE Not implemented
472        TestCPUClass.CoreParams.CP0_Config3_TL = 0 # TraceLogic Not implemented
473
474        #SRS Ctl - HSS
475        TestCPUClass.CoreParams.CP0_SrsCtl_HSS = 3 # Four shadow register sets implemented
476
477
478        #TestCPUClass.CoreParams.tlb = TLB()
479        #TestCPUClass.CoreParams.UnifiedTLB = 1
480