FSConfig.py revision 5641:51b7b8cf8083
12929Sktlim@umich.edu# Copyright (c) 2006-2008 The Regents of The University of Michigan 22929Sktlim@umich.edu# All rights reserved. 32932Sktlim@umich.edu# 42929Sktlim@umich.edu# Redistribution and use in source and binary forms, with or without 52929Sktlim@umich.edu# modification, are permitted provided that the following conditions are 62929Sktlim@umich.edu# met: redistributions of source code must retain the above copyright 72929Sktlim@umich.edu# notice, this list of conditions and the following disclaimer; 82929Sktlim@umich.edu# redistributions in binary form must reproduce the above copyright 92929Sktlim@umich.edu# notice, this list of conditions and the following disclaimer in the 102929Sktlim@umich.edu# documentation and/or other materials provided with the distribution; 112929Sktlim@umich.edu# neither the name of the copyright holders nor the names of its 122929Sktlim@umich.edu# contributors may be used to endorse or promote products derived from 132929Sktlim@umich.edu# this software without specific prior written permission. 142929Sktlim@umich.edu# 152929Sktlim@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 162929Sktlim@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 172929Sktlim@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 182929Sktlim@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 192929Sktlim@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 202929Sktlim@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 212929Sktlim@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 222929Sktlim@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 232929Sktlim@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 242929Sktlim@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 252929Sktlim@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 262929Sktlim@umich.edu# 272929Sktlim@umich.edu# Authors: Kevin Lim 282932Sktlim@umich.edu 292932Sktlim@umich.eduimport m5 302932Sktlim@umich.edufrom m5 import makeList 312929Sktlim@umich.edufrom m5.objects import * 326007Ssteve.reinhardt@amd.comfrom Benchmarks import * 332929Sktlim@umich.edu 342929Sktlim@umich.educlass CowIdeDisk(IdeDisk): 352929Sktlim@umich.edu image = CowDiskImage(child=RawDiskImage(read_only=True), 362929Sktlim@umich.edu read_only=False) 372929Sktlim@umich.edu 382929Sktlim@umich.edu def childImage(self, ci): 392929Sktlim@umich.edu self.image.child.image_file = ci 402929Sktlim@umich.edu 412929Sktlim@umich.edudef makeLinuxAlphaSystem(mem_mode, mdesc = None): 422929Sktlim@umich.edu class BaseTsunami(Tsunami): 432929Sktlim@umich.edu ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 442929Sktlim@umich.edu ide = IdeController(disks=[Parent.disk0, Parent.disk2], 452929Sktlim@umich.edu pci_func=0, pci_dev=0, pci_bus=0) 462929Sktlim@umich.edu 476007Ssteve.reinhardt@amd.com self = LinuxAlphaSystem() 486007Ssteve.reinhardt@amd.com if not mdesc: 496007Ssteve.reinhardt@amd.com # generic system 506007Ssteve.reinhardt@amd.com mdesc = SysConfig() 516007Ssteve.reinhardt@amd.com self.readfile = mdesc.script() 526007Ssteve.reinhardt@amd.com self.iobus = Bus(bus_id=0) 536007Ssteve.reinhardt@amd.com self.membus = Bus(bus_id=1) 546007Ssteve.reinhardt@amd.com self.bridge = Bridge(delay='50ns', nack_delay='4ns') 556007Ssteve.reinhardt@amd.com self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) 566007Ssteve.reinhardt@amd.com self.bridge.side_a = self.iobus.port 576007Ssteve.reinhardt@amd.com self.bridge.side_b = self.membus.port 586007Ssteve.reinhardt@amd.com self.physmem.port = self.membus.port 596007Ssteve.reinhardt@amd.com self.disk0 = CowIdeDisk(driveID='master') 606007Ssteve.reinhardt@amd.com self.disk2 = CowIdeDisk(driveID='master') 616007Ssteve.reinhardt@amd.com self.disk0.childImage(mdesc.disk()) 626007Ssteve.reinhardt@amd.com self.disk2.childImage(disk('linux-bigswap2.img')) 636007Ssteve.reinhardt@amd.com self.tsunami = BaseTsunami() 646007Ssteve.reinhardt@amd.com self.tsunami.attachIO(self.iobus) 656007Ssteve.reinhardt@amd.com self.tsunami.ide.pio = self.iobus.port 666007Ssteve.reinhardt@amd.com self.tsunami.ethernet.pio = self.iobus.port 676007Ssteve.reinhardt@amd.com self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 686007Ssteve.reinhardt@amd.com read_only = True)) 696007Ssteve.reinhardt@amd.com self.intrctrl = IntrControl() 706007Ssteve.reinhardt@amd.com self.mem_mode = mem_mode 716007Ssteve.reinhardt@amd.com self.terminal = Terminal() 726007Ssteve.reinhardt@amd.com self.kernel = binary('vmlinux') 736007Ssteve.reinhardt@amd.com self.pal = binary('ts_osfpal') 746007Ssteve.reinhardt@amd.com self.console = binary('console') 756007Ssteve.reinhardt@amd.com self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 762929Sktlim@umich.edu 772929Sktlim@umich.edu return self 782929Sktlim@umich.edu 796007Ssteve.reinhardt@amd.comdef makeSparcSystem(mem_mode, mdesc = None): 806007Ssteve.reinhardt@amd.com class CowMmDisk(MmDisk): 816007Ssteve.reinhardt@amd.com image = CowDiskImage(child=RawDiskImage(read_only=True), 826007Ssteve.reinhardt@amd.com read_only=False) 836007Ssteve.reinhardt@amd.com 846007Ssteve.reinhardt@amd.com def childImage(self, ci): 852929Sktlim@umich.edu self.image.child.image_file = ci 862929Sktlim@umich.edu 872929Sktlim@umich.edu self = SparcSystem() 882929Sktlim@umich.edu if not mdesc: 892929Sktlim@umich.edu # generic system 906011Ssteve.reinhardt@amd.com mdesc = SysConfig() 916007Ssteve.reinhardt@amd.com self.readfile = mdesc.script() 926007Ssteve.reinhardt@amd.com self.iobus = Bus(bus_id=0) 936007Ssteve.reinhardt@amd.com self.membus = Bus(bus_id=1) 946007Ssteve.reinhardt@amd.com self.bridge = Bridge(delay='50ns', nack_delay='4ns') 956007Ssteve.reinhardt@amd.com self.t1000 = T1000() 966007Ssteve.reinhardt@amd.com self.t1000.attachOnChipIO(self.membus) 976007Ssteve.reinhardt@amd.com self.t1000.attachIO(self.iobus) 986007Ssteve.reinhardt@amd.com self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True) 996007Ssteve.reinhardt@amd.com self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True) 1006007Ssteve.reinhardt@amd.com self.bridge.side_a = self.iobus.port 1016007Ssteve.reinhardt@amd.com self.bridge.side_b = self.membus.port 1026007Ssteve.reinhardt@amd.com self.physmem.port = self.membus.port 1036007Ssteve.reinhardt@amd.com self.physmem2.port = self.membus.port 1046007Ssteve.reinhardt@amd.com self.rom.port = self.membus.port 1056011Ssteve.reinhardt@amd.com self.nvram.port = self.membus.port 1066007Ssteve.reinhardt@amd.com self.hypervisor_desc.port = self.membus.port 1076007Ssteve.reinhardt@amd.com self.partition_desc.port = self.membus.port 1086007Ssteve.reinhardt@amd.com self.intrctrl = IntrControl() 1096007Ssteve.reinhardt@amd.com self.disk0 = CowMmDisk() 1106007Ssteve.reinhardt@amd.com self.disk0.childImage(disk('disk.s10hw2')) 1116007Ssteve.reinhardt@amd.com self.disk0.pio = self.iobus.port 1126007Ssteve.reinhardt@amd.com self.reset_bin = binary('reset_new.bin') 1136011Ssteve.reinhardt@amd.com self.hypervisor_bin = binary('q_new.bin') 1146007Ssteve.reinhardt@amd.com self.openboot_bin = binary('openboot_new.bin') 1156007Ssteve.reinhardt@amd.com self.nvram_bin = binary('nvram1') 1166007Ssteve.reinhardt@amd.com self.hypervisor_desc_bin = binary('1up-hv.bin') 1176007Ssteve.reinhardt@amd.com self.partition_desc_bin = binary('1up-md.bin') 1186007Ssteve.reinhardt@amd.com 1196007Ssteve.reinhardt@amd.com return self 1206007Ssteve.reinhardt@amd.com 1216011Ssteve.reinhardt@amd.comdef makeLinuxMipsSystem(mem_mode, mdesc = None): 1226007Ssteve.reinhardt@amd.com class BaseMalta(Malta): 1236007Ssteve.reinhardt@amd.com ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 1246007Ssteve.reinhardt@amd.com ide = IdeController(disks=[Parent.disk0, Parent.disk2], 1256007Ssteve.reinhardt@amd.com pci_func=0, pci_dev=0, pci_bus=0) 1266007Ssteve.reinhardt@amd.com 1276008Ssteve.reinhardt@amd.com self = LinuxMipsSystem() 1286007Ssteve.reinhardt@amd.com if not mdesc: 1296008Ssteve.reinhardt@amd.com # generic system 1306008Ssteve.reinhardt@amd.com mdesc = SysConfig() 1316008Ssteve.reinhardt@amd.com self.readfile = mdesc.script() 1326008Ssteve.reinhardt@amd.com self.iobus = Bus(bus_id=0) 1336008Ssteve.reinhardt@amd.com self.membus = Bus(bus_id=1) 1346008Ssteve.reinhardt@amd.com self.bridge = Bridge(delay='50ns', nack_delay='4ns') 1356008Ssteve.reinhardt@amd.com self.physmem = PhysicalMemory(range = AddrRange('1GB')) 1366007Ssteve.reinhardt@amd.com self.bridge.side_a = self.iobus.port 1376007Ssteve.reinhardt@amd.com self.bridge.side_b = self.membus.port 1386007Ssteve.reinhardt@amd.com self.physmem.port = self.membus.port 1396007Ssteve.reinhardt@amd.com self.disk0 = CowIdeDisk(driveID='master') 1406007Ssteve.reinhardt@amd.com self.disk2 = CowIdeDisk(driveID='master') 1412929Sktlim@umich.edu self.disk0.childImage(mdesc.disk()) 1422929Sktlim@umich.edu self.disk2.childImage(disk('linux-bigswap2.img')) 1432929Sktlim@umich.edu self.malta = BaseMalta() 1442929Sktlim@umich.edu self.malta.attachIO(self.iobus) 1456007Ssteve.reinhardt@amd.com self.malta.ide.pio = self.iobus.port 1466007Ssteve.reinhardt@amd.com self.malta.ethernet.pio = self.iobus.port 1472929Sktlim@umich.edu self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 1482929Sktlim@umich.edu read_only = True)) 1492929Sktlim@umich.edu self.intrctrl = IntrControl() 1502929Sktlim@umich.edu self.mem_mode = mem_mode 1516007Ssteve.reinhardt@amd.com self.terminal = Terminal() 1526007Ssteve.reinhardt@amd.com self.kernel = binary('mips/vmlinux') 1532929Sktlim@umich.edu self.console = binary('mips/console') 1542929Sktlim@umich.edu self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 1556007Ssteve.reinhardt@amd.com 1562929Sktlim@umich.edu return self 1572929Sktlim@umich.edu 1582929Sktlim@umich.edudef x86IOAddress(port): 1592929Sktlim@umich.edu IO_address_space_base = 0x8000000000000000 1602929Sktlim@umich.edu return IO_address_space_base + port; 1612929Sktlim@umich.edu 1622929Sktlim@umich.edudef makeX86System(mem_mode, mdesc = None, self = None): 1634937Sstever@gmail.com if self == None: 1644937Sstever@gmail.com self = X86System() 1654937Sstever@gmail.com 1664937Sstever@gmail.com if not mdesc: 1674937Sstever@gmail.com # generic system 1684937Sstever@gmail.com mdesc = SysConfig() 1694937Sstever@gmail.com self.readfile = mdesc.script() 1704937Sstever@gmail.com 1714937Sstever@gmail.com # Physical memory 1725773Snate@binkert.org self.membus = Bus(bus_id=1) 1734937Sstever@gmail.com self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) 1744937Sstever@gmail.com self.physmem.port = self.membus.port 1754937Sstever@gmail.com 1762929Sktlim@umich.edu # North Bridge 1772929Sktlim@umich.edu self.iobus = Bus(bus_id=0) 1782929Sktlim@umich.edu self.bridge = Bridge(delay='50ns', nack_delay='4ns') 1795773Snate@binkert.org self.bridge.side_a = self.iobus.port 1802929Sktlim@umich.edu self.bridge.side_b = self.membus.port 1812929Sktlim@umich.edu 1822929Sktlim@umich.edu # Platform 1832929Sktlim@umich.edu self.pc = Pc() 1842929Sktlim@umich.edu self.pc.attachIO(self.iobus) 1852929Sktlim@umich.edu 1864937Sstever@gmail.com self.intrctrl = IntrControl() 1874937Sstever@gmail.com 1884937Sstever@gmail.com # Add in a Bios information structure. 1894937Sstever@gmail.com structures = [X86SMBiosBiosInformation()] 1904937Sstever@gmail.com self.smbios_table.structures = structures 1914937Sstever@gmail.com 1924937Sstever@gmail.com # Set up the Intel MP table 1934937Sstever@gmail.com bp = X86IntelMPProcessor( 1944937Sstever@gmail.com local_apic_id = 0, 1954937Sstever@gmail.com local_apic_version = 0x14, 1964937Sstever@gmail.com enable = True, 1974937Sstever@gmail.com bootstrap = True) 1984937Sstever@gmail.com self.intel_mp_table.add_entry(bp) 1994937Sstever@gmail.com 2004937Sstever@gmail.com 2012929Sktlim@umich.edudef makeLinuxX86System(mem_mode, mdesc = None): 2022929Sktlim@umich.edu self = LinuxX86System() 2032929Sktlim@umich.edu 2042929Sktlim@umich.edu # Build up a generic x86 system and then specialize it for Linux 2052929Sktlim@umich.edu makeX86System(mem_mode, mdesc, self) 2062929Sktlim@umich.edu 2072929Sktlim@umich.edu # We assume below that there's at least 1MB of memory. We'll require 2 2086011Ssteve.reinhardt@amd.com # just to avoid corner cases. 2092929Sktlim@umich.edu assert(self.physmem.range.second >= 0x200000) 2102929Sktlim@umich.edu 2112929Sktlim@umich.edu # Mark the first megabyte of memory as reserved 2122929Sktlim@umich.edu self.e820_table.entries.append(X86E820Entry( 2132929Sktlim@umich.edu addr = 0, 2142929Sktlim@umich.edu size = '1MB', 2152929Sktlim@umich.edu range_type = 2)) 2162929Sktlim@umich.edu 2172997Sstever@eecs.umich.edu # Mark the rest as available 2182997Sstever@eecs.umich.edu self.e820_table.entries.append(X86E820Entry( 2192929Sktlim@umich.edu addr = 0x100000, 2202997Sstever@eecs.umich.edu size = '%dB' % (self.physmem.range.second - 0x100000 - 1), 2212997Sstever@eecs.umich.edu range_type = 1)) 2222929Sktlim@umich.edu 2232997Sstever@eecs.umich.edu # Command line 2242997Sstever@eecs.umich.edu self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=9608015' 2252997Sstever@eecs.umich.edu 2262929Sktlim@umich.edu return self 2272997Sstever@eecs.umich.edu 2282997Sstever@eecs.umich.edu 2292997Sstever@eecs.umich.edudef makeDualRoot(testSystem, driveSystem, dumpfile): 2302997Sstever@eecs.umich.edu self = Root() 2315773Snate@binkert.org self.testsys = testSystem 2325773Snate@binkert.org self.drivesys = driveSystem 2332997Sstever@eecs.umich.edu self.etherlink = EtherLink() 2342997Sstever@eecs.umich.edu self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 2356007Ssteve.reinhardt@amd.com self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 2366007Ssteve.reinhardt@amd.com 2372997Sstever@eecs.umich.edu if dumpfile: 2382929Sktlim@umich.edu self.etherdump = EtherDump(file=dumpfile) 2392997Sstever@eecs.umich.edu self.etherlink.dump = Parent.etherdump 2402997Sstever@eecs.umich.edu 2412997Sstever@eecs.umich.edu return self 2422997Sstever@eecs.umich.edu 2432997Sstever@eecs.umich.edudef setMipsOptions(TestCPUClass): 2442997Sstever@eecs.umich.edu #CP0 Configuration 2452997Sstever@eecs.umich.edu TestCPUClass.CoreParams.CP0_PRId_CompanyOptions = 0 2462929Sktlim@umich.edu TestCPUClass.CoreParams.CP0_PRId_CompanyID = 1 2472997Sstever@eecs.umich.edu TestCPUClass.CoreParams.CP0_PRId_ProcessorID = 147 2482929Sktlim@umich.edu TestCPUClass.CoreParams.CP0_PRId_Revision = 0 2492929Sktlim@umich.edu 2503005Sstever@eecs.umich.edu #CP0 Interrupt Control 2513005Sstever@eecs.umich.edu TestCPUClass.CoreParams.CP0_IntCtl_IPTI = 7 2523005Sstever@eecs.umich.edu TestCPUClass.CoreParams.CP0_IntCtl_IPPCI = 7 2533005Sstever@eecs.umich.edu 2546025Snate@binkert.org # Config Register 2556025Snate@binkert.org #TestCPUClass.CoreParams.CP0_Config_K23 = 0 # Since TLB 2566025Snate@binkert.org #TestCPUClass.CoreParams.CP0_Config_KU = 0 # Since TLB 2576025Snate@binkert.org TestCPUClass.CoreParams.CP0_Config_BE = 0 # Little Endian 2586025Snate@binkert.org TestCPUClass.CoreParams.CP0_Config_AR = 1 # Architecture Revision 2 2596025Snate@binkert.org TestCPUClass.CoreParams.CP0_Config_AT = 0 # MIPS32 2604130Ssaidi@eecs.umich.edu TestCPUClass.CoreParams.CP0_Config_MT = 1 # TLB MMU 2614130Ssaidi@eecs.umich.edu #TestCPUClass.CoreParams.CP0_Config_K0 = 2 # Uncached 2624130Ssaidi@eecs.umich.edu 2633691Shsul@eecs.umich.edu #Config 1 Register 2643005Sstever@eecs.umich.edu TestCPUClass.CoreParams.CP0_Config1_M = 1 # Config2 Implemented 2655721Shsul@eecs.umich.edu TestCPUClass.CoreParams.CP0_Config1_MMU = 63 # TLB Size 2666112Ssteve.reinhardt@amd.com # ***VERY IMPORTANT*** 2673005Sstever@eecs.umich.edu # Remember to modify CP0_Config1 according to cache specs 2686166Ssteve.reinhardt@amd.com # Examine file ../common/Cache.py 2696166Ssteve.reinhardt@amd.com TestCPUClass.CoreParams.CP0_Config1_IS = 1 # I-Cache Sets Per Way, 16KB cache, i.e., 1 (128) 2706166Ssteve.reinhardt@amd.com TestCPUClass.CoreParams.CP0_Config1_IL = 5 # I-Cache Line Size, default in Cache.py is 64, i.e 5 2712929Sktlim@umich.edu TestCPUClass.CoreParams.CP0_Config1_IA = 1 # I-Cache Associativity, default in Cache.py is 2, i.e, a value of 1 2722929Sktlim@umich.edu TestCPUClass.CoreParams.CP0_Config1_DS = 2 # D-Cache Sets Per Way (see below), 32KB cache, i.e., 2 2733005Sstever@eecs.umich.edu TestCPUClass.CoreParams.CP0_Config1_DL = 5 # D-Cache Line Size, default is 64, i.e., 5 2742997Sstever@eecs.umich.edu TestCPUClass.CoreParams.CP0_Config1_DA = 1 # D-Cache Associativity, default is 2, i.e. 1 2752997Sstever@eecs.umich.edu TestCPUClass.CoreParams.CP0_Config1_C2 = 0 # Coprocessor 2 not implemented(?) 2762997Sstever@eecs.umich.edu TestCPUClass.CoreParams.CP0_Config1_MD = 0 # MDMX ASE not implemented in Mips32 2772929Sktlim@umich.edu TestCPUClass.CoreParams.CP0_Config1_PC = 1 # Performance Counters Implemented 278 TestCPUClass.CoreParams.CP0_Config1_WR = 0 # Watch Registers Implemented 279 TestCPUClass.CoreParams.CP0_Config1_CA = 0 # Mips16e NOT implemented 280 TestCPUClass.CoreParams.CP0_Config1_EP = 0 # EJTag Not Implemented 281 TestCPUClass.CoreParams.CP0_Config1_FP = 0 # FPU Implemented 282 283 #Config 2 Register 284 TestCPUClass.CoreParams.CP0_Config2_M = 1 # Config3 Implemented 285 TestCPUClass.CoreParams.CP0_Config2_TU = 0 # Tertiary Cache Control 286 TestCPUClass.CoreParams.CP0_Config2_TS = 0 # Tertiary Cache Sets Per Way 287 TestCPUClass.CoreParams.CP0_Config2_TL = 0 # Tertiary Cache Line Size 288 TestCPUClass.CoreParams.CP0_Config2_TA = 0 # Tertiary Cache Associativity 289 TestCPUClass.CoreParams.CP0_Config2_SU = 0 # Secondary Cache Control 290 TestCPUClass.CoreParams.CP0_Config2_SS = 0 # Secondary Cache Sets Per Way 291 TestCPUClass.CoreParams.CP0_Config2_SL = 0 # Secondary Cache Line Size 292 TestCPUClass.CoreParams.CP0_Config2_SA = 0 # Secondary Cache Associativity 293 294 295 #Config 3 Register 296 TestCPUClass.CoreParams.CP0_Config3_M = 0 # Config4 Not Implemented 297 TestCPUClass.CoreParams.CP0_Config3_DSPP = 1 # DSP ASE Present 298 TestCPUClass.CoreParams.CP0_Config3_LPA = 0 # Large Physical Addresses Not supported in Mips32 299 TestCPUClass.CoreParams.CP0_Config3_VEIC = 0 # EIC Supported 300 TestCPUClass.CoreParams.CP0_Config3_VInt = 0 # Vectored Interrupts Implemented 301 TestCPUClass.CoreParams.CP0_Config3_SP = 0 # Small Pages Supported (PageGrain reg. exists) 302 TestCPUClass.CoreParams.CP0_Config3_MT = 0 # MT Not present 303 TestCPUClass.CoreParams.CP0_Config3_SM = 0 # SmartMIPS ASE Not implemented 304 TestCPUClass.CoreParams.CP0_Config3_TL = 0 # TraceLogic Not implemented 305 306 #SRS Ctl - HSS 307 TestCPUClass.CoreParams.CP0_SrsCtl_HSS = 3 # Four shadow register sets implemented 308 309 310 #TestCPUClass.CoreParams.tlb = TLB() 311 #TestCPUClass.CoreParams.UnifiedTLB = 1 312