FSConfig.py revision 5330:a1db38b0d8e8
19243SN/A# Copyright (c) 2006-2008 The Regents of The University of Michigan 210206Sandreas.hansson@arm.com# All rights reserved. 39243SN/A# 49243SN/A# Redistribution and use in source and binary forms, with or without 59243SN/A# modification, are permitted provided that the following conditions are 69243SN/A# met: redistributions of source code must retain the above copyright 79243SN/A# notice, this list of conditions and the following disclaimer; 89243SN/A# redistributions in binary form must reproduce the above copyright 99243SN/A# notice, this list of conditions and the following disclaimer in the 109243SN/A# documentation and/or other materials provided with the distribution; 119243SN/A# neither the name of the copyright holders nor the names of its 129243SN/A# contributors may be used to endorse or promote products derived from 139243SN/A# this software without specific prior written permission. 149831SN/A# 159831SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 169831SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 179243SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 189243SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 199243SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 209243SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 219243SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 229243SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 239243SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 249243SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 259243SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 269243SN/A# 279243SN/A# Authors: Kevin Lim 289243SN/A 299243SN/Aimport m5 309243SN/Afrom m5 import makeList 319243SN/Afrom m5.objects import * 329243SN/Afrom Benchmarks import * 339243SN/A 349243SN/Aclass CowIdeDisk(IdeDisk): 359243SN/A image = CowDiskImage(child=RawDiskImage(read_only=True), 369243SN/A read_only=False) 379243SN/A 389243SN/A def childImage(self, ci): 399243SN/A self.image.child.image_file = ci 409243SN/A 419243SN/Adef makeLinuxAlphaSystem(mem_mode, mdesc = None): 429967SN/A class BaseTsunami(Tsunami): 439243SN/A ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 449243SN/A ide = IdeController(disks=[Parent.disk0, Parent.disk2], 4510146Sandreas.hansson@arm.com pci_func=0, pci_dev=0, pci_bus=0) 469356SN/A 4710146Sandreas.hansson@arm.com self = LinuxAlphaSystem() 4810208Sandreas.hansson@arm.com if not mdesc: 499352SN/A # generic system 5010146Sandreas.hansson@arm.com mdesc = SysConfig() 519814SN/A self.readfile = mdesc.script() 529243SN/A self.iobus = Bus(bus_id=0) 539243SN/A self.membus = Bus(bus_id=1) 549243SN/A self.bridge = Bridge(delay='50ns', nack_delay='4ns') 5510146Sandreas.hansson@arm.com self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) 569243SN/A self.bridge.side_a = self.iobus.port 579243SN/A self.bridge.side_b = self.membus.port 589243SN/A self.physmem.port = self.membus.port 5910211Sandreas.hansson@arm.com self.disk0 = CowIdeDisk(driveID='master') 6010208Sandreas.hansson@arm.com self.disk2 = CowIdeDisk(driveID='master') 6110208Sandreas.hansson@arm.com self.disk0.childImage(mdesc.disk()) 6210208Sandreas.hansson@arm.com self.disk2.childImage(disk('linux-bigswap2.img')) 639831SN/A self.tsunami = BaseTsunami() 649831SN/A self.tsunami.attachIO(self.iobus) 659831SN/A self.tsunami.ide.pio = self.iobus.port 669831SN/A self.tsunami.ethernet.pio = self.iobus.port 679831SN/A self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 6810140SN/A read_only = True)) 699243SN/A self.intrctrl = IntrControl() 709566SN/A self.mem_mode = mem_mode 719243SN/A self.sim_console = SimConsole() 729243SN/A self.kernel = binary('vmlinux') 7310140SN/A self.pal = binary('ts_osfpal') 7410140SN/A self.console = binary('console') 7510147Sandreas.hansson@arm.com self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 7610147Sandreas.hansson@arm.com 7710216Sandreas.hansson@arm.com return self 7810210Sandreas.hansson@arm.com 7910212Sandreas.hansson@arm.comdef makeSparcSystem(mem_mode, mdesc = None): 809488SN/A class CowMmDisk(MmDisk): 819243SN/A image = CowDiskImage(child=RawDiskImage(read_only=True), 829243SN/A read_only=False) 8310141SN/A 849726SN/A def childImage(self, ci): 859726SN/A self.image.child.image_file = ci 8610208Sandreas.hansson@arm.com 8710208Sandreas.hansson@arm.com self = SparcSystem() 8810208Sandreas.hansson@arm.com if not mdesc: 899243SN/A # generic system 909243SN/A mdesc = SysConfig() 919243SN/A self.readfile = mdesc.script() 929243SN/A self.iobus = Bus(bus_id=0) 939969SN/A self.membus = Bus(bus_id=1) 949243SN/A self.bridge = Bridge(delay='50ns', nack_delay='4ns') 959243SN/A self.t1000 = T1000() 969969SN/A self.t1000.attachOnChipIO(self.membus) 979243SN/A self.t1000.attachIO(self.iobus) 989243SN/A self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True) 9910140SN/A self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True) 10010140SN/A self.bridge.side_a = self.iobus.port 10110140SN/A self.bridge.side_b = self.membus.port 10210140SN/A self.physmem.port = self.membus.port 10310140SN/A self.physmem2.port = self.membus.port 1049243SN/A self.rom.port = self.membus.port 1059243SN/A self.nvram.port = self.membus.port 1069567SN/A self.hypervisor_desc.port = self.membus.port 1079243SN/A self.partition_desc.port = self.membus.port 1089243SN/A self.intrctrl = IntrControl() 1099243SN/A self.disk0 = CowMmDisk() 1109831SN/A self.disk0.childImage(disk('disk.s10hw2')) 1119831SN/A self.disk0.pio = self.iobus.port 1129831SN/A self.reset_bin = binary('reset_new.bin') 1139831SN/A self.hypervisor_bin = binary('q_new.bin') 1149831SN/A self.openboot_bin = binary('openboot_new.bin') 1159243SN/A self.nvram_bin = binary('nvram1') 1169566SN/A self.hypervisor_desc_bin = binary('1up-hv.bin') 1179566SN/A self.partition_desc_bin = binary('1up-md.bin') 11810143SN/A 1199566SN/A return self 1209566SN/A 12110136SN/Adef makeLinuxMipsSystem(mem_mode, mdesc = None): 1229831SN/A class BaseMalta(Malta): 12310143SN/A ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 12410136SN/A ide = IdeController(disks=[Parent.disk0, Parent.disk2], 1259566SN/A pci_func=0, pci_dev=0, pci_bus=0) 12610136SN/A 12710136SN/A self = LinuxMipsSystem() 12810143SN/A if not mdesc: 12910136SN/A # generic system 1309669SN/A mdesc = SysConfig() 13110136SN/A self.readfile = mdesc.script() 13210136SN/A self.iobus = Bus(bus_id=0) 13310143SN/A self.membus = Bus(bus_id=1) 13410136SN/A self.bridge = Bridge(delay='50ns', nack_delay='4ns') 1359566SN/A self.physmem = PhysicalMemory(range = AddrRange('1GB')) 1369566SN/A self.bridge.side_a = self.iobus.port 13710207Sandreas.hansson@arm.com self.bridge.side_b = self.membus.port 13810207Sandreas.hansson@arm.com self.physmem.port = self.membus.port 13910207Sandreas.hansson@arm.com self.disk0 = CowIdeDisk(driveID='master') 14010207Sandreas.hansson@arm.com self.disk2 = CowIdeDisk(driveID='master') 14110207Sandreas.hansson@arm.com self.disk0.childImage(mdesc.disk()) 14210207Sandreas.hansson@arm.com self.disk2.childImage(disk('linux-bigswap2.img')) 1439243SN/A self.malta = BaseMalta() 1449243SN/A self.malta.attachIO(self.iobus) 1459243SN/A self.malta.ide.pio = self.iobus.port 14610146Sandreas.hansson@arm.com self.malta.ethernet.pio = self.iobus.port 14710140SN/A self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 14810140SN/A read_only = True)) 14910146Sandreas.hansson@arm.com self.intrctrl = IntrControl() 15010140SN/A self.mem_mode = mem_mode 15110140SN/A self.sim_console = SimConsole() 15210140SN/A self.kernel = binary('mips/vmlinux') 15310140SN/A self.console = binary('mips/console') 15410140SN/A self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 15510140SN/A 15610146Sandreas.hansson@arm.com return self 1579243SN/A 15810143SN/Adef x86IOAddress(port): 15910143SN/A IO_address_space_base = 0x1000000000000000 16010208Sandreas.hansson@arm.com return IO_address_space_base + port; 16110143SN/A 16210206Sandreas.hansson@arm.comdef makeLinuxX86System(mem_mode, mdesc = None): 16310206Sandreas.hansson@arm.com self = LinuxX86System() 16410206Sandreas.hansson@arm.com if not mdesc: 16510206Sandreas.hansson@arm.com # generic system 16610206Sandreas.hansson@arm.com mdesc = SysConfig() 16710206Sandreas.hansson@arm.com self.readfile = mdesc.script() 16810207Sandreas.hansson@arm.com 16910207Sandreas.hansson@arm.com # Physical memory 17010207Sandreas.hansson@arm.com self.membus = Bus(bus_id=1) 1719243SN/A self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) 1729243SN/A self.physmem.port = self.membus.port 1739243SN/A 17410146Sandreas.hansson@arm.com # North Bridge 1759243SN/A self.iobus = Bus(bus_id=0) 1769243SN/A self.bridge = Bridge(delay='50ns', nack_delay='4ns') 1779243SN/A self.bridge.side_a = self.iobus.port 1789243SN/A self.bridge.side_b = self.membus.port 1799243SN/A 1809243SN/A # Serial port and console 1819243SN/A self.console = SimConsole() 1829243SN/A self.com_1 = Uart8250() 1839243SN/A self.com_1.pio_addr = x86IOAddress(0x3f8) 1849243SN/A self.com_1.pio = self.iobus.port 1859243SN/A self.com_1.sim_console = self.console 1869243SN/A 1879243SN/A # Command line 1889243SN/A self.boot_osflags = 'earlyprintk=ttyS0' 1899243SN/A 1909243SN/A # Platform 19110146Sandreas.hansson@arm.com self.opteron = Opteron() 1929243SN/A 1939831SN/A self.intrctrl = IntrControl() 1949831SN/A 1959831SN/A return self 1969243SN/A 1979831SN/A 1989831SN/Adef makeDualRoot(testSystem, driveSystem, dumpfile): 1999243SN/A self = Root() 2009243SN/A self.testsys = testSystem 2019243SN/A self.drivesys = driveSystem 20210146Sandreas.hansson@arm.com self.etherlink = EtherLink() 2039243SN/A self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 2049831SN/A self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 2059831SN/A 2069831SN/A if dumpfile: 2079243SN/A self.etherdump = EtherDump(file=dumpfile) 2089243SN/A self.etherlink.dump = Parent.etherdump 20910146Sandreas.hansson@arm.com 21010146Sandreas.hansson@arm.com return self 21110143SN/A 2129243SN/Adef setMipsOptions(TestCPUClass): 2139669SN/A #CP0 Configuration 21410136SN/A TestCPUClass.CoreParams.CP0_PRId_CompanyOptions = 0 21510136SN/A TestCPUClass.CoreParams.CP0_PRId_CompanyID = 1 2169243SN/A TestCPUClass.CoreParams.CP0_PRId_ProcessorID = 147 2179967SN/A TestCPUClass.CoreParams.CP0_PRId_Revision = 0 21810245Sandreas.hansson@arm.com 21910245Sandreas.hansson@arm.com #CP0 Interrupt Control 22010245Sandreas.hansson@arm.com TestCPUClass.CoreParams.CP0_IntCtl_IPTI = 7 2219243SN/A TestCPUClass.CoreParams.CP0_IntCtl_IPPCI = 7 2229243SN/A 2239831SN/A # Config Register 2249243SN/A #TestCPUClass.CoreParams.CP0_Config_K23 = 0 # Since TLB 2259491SN/A #TestCPUClass.CoreParams.CP0_Config_KU = 0 # Since TLB 2269831SN/A TestCPUClass.CoreParams.CP0_Config_BE = 0 # Little Endian 22710136SN/A TestCPUClass.CoreParams.CP0_Config_AR = 1 # Architecture Revision 2 2289491SN/A TestCPUClass.CoreParams.CP0_Config_AT = 0 # MIPS32 2299491SN/A TestCPUClass.CoreParams.CP0_Config_MT = 1 # TLB MMU 2309831SN/A #TestCPUClass.CoreParams.CP0_Config_K0 = 2 # Uncached 2319243SN/A 2329669SN/A #Config 1 Register 2339566SN/A TestCPUClass.CoreParams.CP0_Config1_M = 1 # Config2 Implemented 2349566SN/A TestCPUClass.CoreParams.CP0_Config1_MMU = 63 # TLB Size 2359669SN/A # ***VERY IMPORTANT*** 2369669SN/A # Remember to modify CP0_Config1 according to cache specs 2379669SN/A # Examine file ../common/Cache.py 2389669SN/A TestCPUClass.CoreParams.CP0_Config1_IS = 1 # I-Cache Sets Per Way, 16KB cache, i.e., 1 (128) 2399669SN/A TestCPUClass.CoreParams.CP0_Config1_IL = 5 # I-Cache Line Size, default in Cache.py is 64, i.e 5 2409669SN/A TestCPUClass.CoreParams.CP0_Config1_IA = 1 # I-Cache Associativity, default in Cache.py is 2, i.e, a value of 1 2419669SN/A TestCPUClass.CoreParams.CP0_Config1_DS = 2 # D-Cache Sets Per Way (see below), 32KB cache, i.e., 2 2429669SN/A TestCPUClass.CoreParams.CP0_Config1_DL = 5 # D-Cache Line Size, default is 64, i.e., 5 2439669SN/A TestCPUClass.CoreParams.CP0_Config1_DA = 1 # D-Cache Associativity, default is 2, i.e. 1 2449669SN/A TestCPUClass.CoreParams.CP0_Config1_C2 = 0 # Coprocessor 2 not implemented(?) 2459669SN/A TestCPUClass.CoreParams.CP0_Config1_MD = 0 # MDMX ASE not implemented in Mips32 2469669SN/A TestCPUClass.CoreParams.CP0_Config1_PC = 1 # Performance Counters Implemented 2479669SN/A TestCPUClass.CoreParams.CP0_Config1_WR = 0 # Watch Registers Implemented 24810136SN/A TestCPUClass.CoreParams.CP0_Config1_CA = 0 # Mips16e NOT implemented 2499669SN/A TestCPUClass.CoreParams.CP0_Config1_EP = 0 # EJTag Not Implemented 2509669SN/A TestCPUClass.CoreParams.CP0_Config1_FP = 0 # FPU Implemented 2519669SN/A 2529669SN/A #Config 2 Register 2539831SN/A TestCPUClass.CoreParams.CP0_Config2_M = 1 # Config3 Implemented 2549669SN/A TestCPUClass.CoreParams.CP0_Config2_TU = 0 # Tertiary Cache Control 2559669SN/A TestCPUClass.CoreParams.CP0_Config2_TS = 0 # Tertiary Cache Sets Per Way 2569491SN/A TestCPUClass.CoreParams.CP0_Config2_TL = 0 # Tertiary Cache Line Size 2579243SN/A TestCPUClass.CoreParams.CP0_Config2_TA = 0 # Tertiary Cache Associativity 2589243SN/A TestCPUClass.CoreParams.CP0_Config2_SU = 0 # Secondary Cache Control 2599243SN/A TestCPUClass.CoreParams.CP0_Config2_SS = 0 # Secondary Cache Sets Per Way 2609491SN/A TestCPUClass.CoreParams.CP0_Config2_SL = 0 # Secondary Cache Line Size 2619491SN/A TestCPUClass.CoreParams.CP0_Config2_SA = 0 # Secondary Cache Associativity 2629243SN/A 2639243SN/A 2649243SN/A #Config 3 Register 2659491SN/A TestCPUClass.CoreParams.CP0_Config3_M = 0 # Config4 Not Implemented 2669243SN/A TestCPUClass.CoreParams.CP0_Config3_DSPP = 1 # DSP ASE Present 2679243SN/A TestCPUClass.CoreParams.CP0_Config3_LPA = 0 # Large Physical Addresses Not supported in Mips32 26810136SN/A TestCPUClass.CoreParams.CP0_Config3_VEIC = 0 # EIC Supported 2699491SN/A TestCPUClass.CoreParams.CP0_Config3_VInt = 0 # Vectored Interrupts Implemented 2709491SN/A TestCPUClass.CoreParams.CP0_Config3_SP = 0 # Small Pages Supported (PageGrain reg. exists) 2719491SN/A TestCPUClass.CoreParams.CP0_Config3_MT = 0 # MT Not present 2729566SN/A TestCPUClass.CoreParams.CP0_Config3_SM = 0 # SmartMIPS ASE Not implemented 2739566SN/A TestCPUClass.CoreParams.CP0_Config3_TL = 0 # TraceLogic Not implemented 2749566SN/A 2759566SN/A #SRS Ctl - HSS 2769566SN/A TestCPUClass.CoreParams.CP0_SrsCtl_HSS = 3 # Four shadow register sets implemented 2779491SN/A 2789491SN/A 2799243SN/A #TestCPUClass.CoreParams.tlb = TLB() 2809243SN/A #TestCPUClass.CoreParams.UnifiedTLB = 1 2819243SN/A