FSConfig.py revision 5323
16313Sgblack@eecs.umich.edu# Copyright (c) 2006-2008 The Regents of The University of Michigan 26313Sgblack@eecs.umich.edu# All rights reserved. 36313Sgblack@eecs.umich.edu# 46313Sgblack@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 56313Sgblack@eecs.umich.edu# modification, are permitted provided that the following conditions are 66313Sgblack@eecs.umich.edu# met: redistributions of source code must retain the above copyright 76313Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 86313Sgblack@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 96313Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 106313Sgblack@eecs.umich.edu# documentation and/or other materials provided with the distribution; 116313Sgblack@eecs.umich.edu# neither the name of the copyright holders nor the names of its 126313Sgblack@eecs.umich.edu# contributors may be used to endorse or promote products derived from 136313Sgblack@eecs.umich.edu# this software without specific prior written permission. 146313Sgblack@eecs.umich.edu# 156313Sgblack@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 166313Sgblack@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 176313Sgblack@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 186313Sgblack@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 196313Sgblack@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 206313Sgblack@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 216313Sgblack@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 226313Sgblack@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 236313Sgblack@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 246313Sgblack@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 256313Sgblack@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 266313Sgblack@eecs.umich.edu# 276313Sgblack@eecs.umich.edu# Authors: Kevin Lim 286313Sgblack@eecs.umich.edu 296313Sgblack@eecs.umich.eduimport m5 306313Sgblack@eecs.umich.edufrom m5 import makeList 316313Sgblack@eecs.umich.edufrom m5.objects import * 328229Snate@binkert.orgfrom Benchmarks import * 336334Sgblack@eecs.umich.edu 346334Sgblack@eecs.umich.educlass CowIdeDisk(IdeDisk): 356334Sgblack@eecs.umich.edu image = CowDiskImage(child=RawDiskImage(read_only=True), 366334Sgblack@eecs.umich.edu read_only=False) 376313Sgblack@eecs.umich.edu 388232Snate@binkert.org def childImage(self, ci): 396313Sgblack@eecs.umich.edu self.image.child.image_file = ci 406313Sgblack@eecs.umich.edu 416313Sgblack@eecs.umich.edudef makeLinuxAlphaSystem(mem_mode, mdesc = None): 426313Sgblack@eecs.umich.edu class BaseTsunami(Tsunami): 436334Sgblack@eecs.umich.edu ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 446334Sgblack@eecs.umich.edu ide = IdeController(disks=[Parent.disk0, Parent.disk2], 456334Sgblack@eecs.umich.edu pci_func=0, pci_dev=0, pci_bus=0) 466334Sgblack@eecs.umich.edu 476334Sgblack@eecs.umich.edu self = LinuxAlphaSystem() 486334Sgblack@eecs.umich.edu if not mdesc: 496334Sgblack@eecs.umich.edu # generic system 506334Sgblack@eecs.umich.edu mdesc = SysConfig() 516334Sgblack@eecs.umich.edu self.readfile = mdesc.script() 526334Sgblack@eecs.umich.edu self.iobus = Bus(bus_id=0) 536334Sgblack@eecs.umich.edu self.membus = Bus(bus_id=1) 546334Sgblack@eecs.umich.edu self.bridge = Bridge(delay='50ns', nack_delay='4ns') 556334Sgblack@eecs.umich.edu self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) 566334Sgblack@eecs.umich.edu self.bridge.side_a = self.iobus.port 576334Sgblack@eecs.umich.edu self.bridge.side_b = self.membus.port 586334Sgblack@eecs.umich.edu self.physmem.port = self.membus.port 596334Sgblack@eecs.umich.edu self.disk0 = CowIdeDisk(driveID='master') 606334Sgblack@eecs.umich.edu self.disk2 = CowIdeDisk(driveID='master') 616334Sgblack@eecs.umich.edu self.disk0.childImage(mdesc.disk()) 626334Sgblack@eecs.umich.edu self.disk2.childImage(disk('linux-bigswap2.img')) 636334Sgblack@eecs.umich.edu self.tsunami = BaseTsunami() 646334Sgblack@eecs.umich.edu self.tsunami.attachIO(self.iobus) 656334Sgblack@eecs.umich.edu self.tsunami.ide.pio = self.iobus.port 666334Sgblack@eecs.umich.edu self.tsunami.ethernet.pio = self.iobus.port 676334Sgblack@eecs.umich.edu self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 686334Sgblack@eecs.umich.edu read_only = True)) 696334Sgblack@eecs.umich.edu self.intrctrl = IntrControl() 706334Sgblack@eecs.umich.edu self.mem_mode = mem_mode 716334Sgblack@eecs.umich.edu self.sim_console = SimConsole() 726334Sgblack@eecs.umich.edu self.kernel = binary('vmlinux') 736334Sgblack@eecs.umich.edu self.pal = binary('ts_osfpal') 746334Sgblack@eecs.umich.edu self.console = binary('console') 756334Sgblack@eecs.umich.edu self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 766334Sgblack@eecs.umich.edu 776334Sgblack@eecs.umich.edu return self 786334Sgblack@eecs.umich.edu 796334Sgblack@eecs.umich.edudef makeSparcSystem(mem_mode, mdesc = None): 806334Sgblack@eecs.umich.edu class CowMmDisk(MmDisk): 816334Sgblack@eecs.umich.edu image = CowDiskImage(child=RawDiskImage(read_only=True), 826334Sgblack@eecs.umich.edu read_only=False) 836334Sgblack@eecs.umich.edu 846334Sgblack@eecs.umich.edu def childImage(self, ci): 856334Sgblack@eecs.umich.edu self.image.child.image_file = ci 866334Sgblack@eecs.umich.edu 876334Sgblack@eecs.umich.edu self = SparcSystem() 886334Sgblack@eecs.umich.edu if not mdesc: 896334Sgblack@eecs.umich.edu # generic system 908181Sksewell@umich.edu mdesc = SysConfig() 916334Sgblack@eecs.umich.edu self.readfile = mdesc.script() 928181Sksewell@umich.edu self.iobus = Bus(bus_id=0) 938181Sksewell@umich.edu self.membus = Bus(bus_id=1) 946334Sgblack@eecs.umich.edu self.bridge = Bridge(delay='50ns', nack_delay='4ns') 956334Sgblack@eecs.umich.edu self.t1000 = T1000() 966334Sgblack@eecs.umich.edu self.t1000.attachOnChipIO(self.membus) 976334Sgblack@eecs.umich.edu self.t1000.attachIO(self.iobus) 986334Sgblack@eecs.umich.edu self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True) 996334Sgblack@eecs.umich.edu self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True) 1006334Sgblack@eecs.umich.edu self.bridge.side_a = self.iobus.port 1016334Sgblack@eecs.umich.edu self.bridge.side_b = self.membus.port 1026334Sgblack@eecs.umich.edu self.physmem.port = self.membus.port 1036334Sgblack@eecs.umich.edu self.physmem2.port = self.membus.port 1046334Sgblack@eecs.umich.edu self.rom.port = self.membus.port 1056376Sgblack@eecs.umich.edu self.nvram.port = self.membus.port 1066376Sgblack@eecs.umich.edu self.hypervisor_desc.port = self.membus.port 1076334Sgblack@eecs.umich.edu self.partition_desc.port = self.membus.port 1086334Sgblack@eecs.umich.edu self.intrctrl = IntrControl() 1096334Sgblack@eecs.umich.edu self.disk0 = CowMmDisk() 1106383Sgblack@eecs.umich.edu self.disk0.childImage(disk('disk.s10hw2')) 1116383Sgblack@eecs.umich.edu self.disk0.pio = self.iobus.port 1126383Sgblack@eecs.umich.edu self.reset_bin = binary('reset_new.bin') 1136383Sgblack@eecs.umich.edu self.hypervisor_bin = binary('q_new.bin') 1146383Sgblack@eecs.umich.edu self.openboot_bin = binary('openboot_new.bin') 1156383Sgblack@eecs.umich.edu self.nvram_bin = binary('nvram1') 1166383Sgblack@eecs.umich.edu self.hypervisor_desc_bin = binary('1up-hv.bin') 1176383Sgblack@eecs.umich.edu self.partition_desc_bin = binary('1up-md.bin') 1186334Sgblack@eecs.umich.edu 1196334Sgblack@eecs.umich.edu return self 1206334Sgblack@eecs.umich.edu 1218181Sksewell@umich.edudef makeLinuxMipsSystem(mem_mode, mdesc = None): 1228181Sksewell@umich.edu class BaseMalta(Malta): 1236334Sgblack@eecs.umich.edu ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 1246334Sgblack@eecs.umich.edu ide = IdeController(disks=[Parent.disk0, Parent.disk2], 1256334Sgblack@eecs.umich.edu pci_func=0, pci_dev=0, pci_bus=0) 1266334Sgblack@eecs.umich.edu 1276334Sgblack@eecs.umich.edu self = LinuxMipsSystem() 1286383Sgblack@eecs.umich.edu if not mdesc: 1296383Sgblack@eecs.umich.edu # generic system 1306383Sgblack@eecs.umich.edu mdesc = SysConfig() 1316383Sgblack@eecs.umich.edu self.readfile = mdesc.script() 1326383Sgblack@eecs.umich.edu self.iobus = Bus(bus_id=0) 1336383Sgblack@eecs.umich.edu self.membus = Bus(bus_id=1) 1346334Sgblack@eecs.umich.edu self.bridge = Bridge(delay='50ns', nack_delay='4ns') 1356334Sgblack@eecs.umich.edu self.physmem = PhysicalMemory(range = AddrRange('1GB')) 1366334Sgblack@eecs.umich.edu self.bridge.side_a = self.iobus.port 1376334Sgblack@eecs.umich.edu self.bridge.side_b = self.membus.port 1388181Sksewell@umich.edu self.physmem.port = self.membus.port 1396334Sgblack@eecs.umich.edu self.disk0 = CowIdeDisk(driveID='master') 1406334Sgblack@eecs.umich.edu self.disk2 = CowIdeDisk(driveID='master') 1416334Sgblack@eecs.umich.edu self.disk0.childImage(mdesc.disk()) 1428181Sksewell@umich.edu self.disk2.childImage(disk('linux-bigswap2.img')) 1436334Sgblack@eecs.umich.edu self.malta = BaseMalta() 1446334Sgblack@eecs.umich.edu self.malta.attachIO(self.iobus) 1456334Sgblack@eecs.umich.edu self.malta.ide.pio = self.iobus.port 1468181Sksewell@umich.edu self.malta.ethernet.pio = self.iobus.port 1478181Sksewell@umich.edu self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 1488181Sksewell@umich.edu read_only = True)) 1498181Sksewell@umich.edu self.intrctrl = IntrControl() 1508181Sksewell@umich.edu self.mem_mode = mem_mode 1518181Sksewell@umich.edu self.sim_console = SimConsole() 1528181Sksewell@umich.edu self.kernel = binary('mips/vmlinux') 1538181Sksewell@umich.edu self.console = binary('mips/console') 1548181Sksewell@umich.edu self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 1558181Sksewell@umich.edu 1568181Sksewell@umich.edu return self 1578181Sksewell@umich.edu 1588181Sksewell@umich.edudef x86IOAddress(port): 1598181Sksewell@umich.edu IO_address_space_base = 0x1000000000000000 1606334Sgblack@eecs.umich.edu return IO_address_space_base + port; 1616334Sgblack@eecs.umich.edu 1628181Sksewell@umich.edudef makeLinuxX86System(mem_mode, mdesc = None): 1636334Sgblack@eecs.umich.edu self = LinuxX86System() 1648181Sksewell@umich.edu if not mdesc: 1658181Sksewell@umich.edu # generic system 1666334Sgblack@eecs.umich.edu mdesc = SysConfig() 1676334Sgblack@eecs.umich.edu self.readfile = mdesc.script() 1686334Sgblack@eecs.umich.edu 1696334Sgblack@eecs.umich.edu # Physical memory 1706334Sgblack@eecs.umich.edu self.membus = Bus(bus_id=1) 1716334Sgblack@eecs.umich.edu self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) 1726334Sgblack@eecs.umich.edu self.physmem.port = self.membus.port 1736334Sgblack@eecs.umich.edu 1746383Sgblack@eecs.umich.edu # North Bridge 1756376Sgblack@eecs.umich.edu self.iobus = Bus(bus_id=0) 1766376Sgblack@eecs.umich.edu self.bridge = Bridge(delay='50ns', nack_delay='4ns') 1776376Sgblack@eecs.umich.edu self.bridge.side_a = self.iobus.port 1786376Sgblack@eecs.umich.edu self.bridge.side_b = self.membus.port 1796383Sgblack@eecs.umich.edu 1806376Sgblack@eecs.umich.edu # Serial port and console 1816334Sgblack@eecs.umich.edu self.console = SimConsole() 1826383Sgblack@eecs.umich.edu self.com_1 = Uart8250() 1836383Sgblack@eecs.umich.edu self.com_1.pio_addr = x86IOAddress(0x3f8) 1846383Sgblack@eecs.umich.edu self.com_1.pio = self.iobus.port 1856334Sgblack@eecs.umich.edu self.com_1.sim_console = self.console 1866334Sgblack@eecs.umich.edu 1876383Sgblack@eecs.umich.edu # Platform 1886376Sgblack@eecs.umich.edu self.opteron = Opteron() 1896376Sgblack@eecs.umich.edu 1906376Sgblack@eecs.umich.edu self.intrctrl = IntrControl() 1916376Sgblack@eecs.umich.edu 1926376Sgblack@eecs.umich.edu return self 1936376Sgblack@eecs.umich.edu 1946383Sgblack@eecs.umich.edu 1956334Sgblack@eecs.umich.edudef makeDualRoot(testSystem, driveSystem, dumpfile): 1966334Sgblack@eecs.umich.edu self = Root() 1976376Sgblack@eecs.umich.edu self.testsys = testSystem 1986383Sgblack@eecs.umich.edu self.drivesys = driveSystem 1996334Sgblack@eecs.umich.edu self.etherlink = EtherLink() 2006334Sgblack@eecs.umich.edu self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 2016383Sgblack@eecs.umich.edu self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 2026376Sgblack@eecs.umich.edu 2036376Sgblack@eecs.umich.edu if dumpfile: 2046376Sgblack@eecs.umich.edu self.etherdump = EtherDump(file=dumpfile) 2056376Sgblack@eecs.umich.edu self.etherlink.dump = Parent.etherdump 2066376Sgblack@eecs.umich.edu 2076376Sgblack@eecs.umich.edu return self 2086376Sgblack@eecs.umich.edu 2096376Sgblack@eecs.umich.edudef setMipsOptions(TestCPUClass): 2106376Sgblack@eecs.umich.edu #CP0 Configuration 2116376Sgblack@eecs.umich.edu TestCPUClass.CoreParams.CP0_PRId_CompanyOptions = 0 2126376Sgblack@eecs.umich.edu TestCPUClass.CoreParams.CP0_PRId_CompanyID = 1 2136376Sgblack@eecs.umich.edu TestCPUClass.CoreParams.CP0_PRId_ProcessorID = 147 2146376Sgblack@eecs.umich.edu TestCPUClass.CoreParams.CP0_PRId_Revision = 0 2156376Sgblack@eecs.umich.edu 2166383Sgblack@eecs.umich.edu #CP0 Interrupt Control 2176334Sgblack@eecs.umich.edu TestCPUClass.CoreParams.CP0_IntCtl_IPTI = 7 2186334Sgblack@eecs.umich.edu TestCPUClass.CoreParams.CP0_IntCtl_IPPCI = 7 2196376Sgblack@eecs.umich.edu 2206383Sgblack@eecs.umich.edu # Config Register 2216334Sgblack@eecs.umich.edu #TestCPUClass.CoreParams.CP0_Config_K23 = 0 # Since TLB 2226334Sgblack@eecs.umich.edu #TestCPUClass.CoreParams.CP0_Config_KU = 0 # Since TLB 2236383Sgblack@eecs.umich.edu TestCPUClass.CoreParams.CP0_Config_BE = 0 # Little Endian 2246376Sgblack@eecs.umich.edu TestCPUClass.CoreParams.CP0_Config_AR = 1 # Architecture Revision 2 2256376Sgblack@eecs.umich.edu TestCPUClass.CoreParams.CP0_Config_AT = 0 # MIPS32 2266376Sgblack@eecs.umich.edu TestCPUClass.CoreParams.CP0_Config_MT = 1 # TLB MMU 2276376Sgblack@eecs.umich.edu #TestCPUClass.CoreParams.CP0_Config_K0 = 2 # Uncached 2286376Sgblack@eecs.umich.edu 2296376Sgblack@eecs.umich.edu #Config 1 Register 2306376Sgblack@eecs.umich.edu TestCPUClass.CoreParams.CP0_Config1_M = 1 # Config2 Implemented 2316376Sgblack@eecs.umich.edu TestCPUClass.CoreParams.CP0_Config1_MMU = 63 # TLB Size 2326376Sgblack@eecs.umich.edu # ***VERY IMPORTANT*** 2336383Sgblack@eecs.umich.edu # Remember to modify CP0_Config1 according to cache specs 2346334Sgblack@eecs.umich.edu # Examine file ../common/Cache.py 2356334Sgblack@eecs.umich.edu TestCPUClass.CoreParams.CP0_Config1_IS = 1 # I-Cache Sets Per Way, 16KB cache, i.e., 1 (128) 2366376Sgblack@eecs.umich.edu TestCPUClass.CoreParams.CP0_Config1_IL = 5 # I-Cache Line Size, default in Cache.py is 64, i.e 5 2376383Sgblack@eecs.umich.edu TestCPUClass.CoreParams.CP0_Config1_IA = 1 # I-Cache Associativity, default in Cache.py is 2, i.e, a value of 1 2386334Sgblack@eecs.umich.edu TestCPUClass.CoreParams.CP0_Config1_DS = 2 # D-Cache Sets Per Way (see below), 32KB cache, i.e., 2 2396334Sgblack@eecs.umich.edu TestCPUClass.CoreParams.CP0_Config1_DL = 5 # D-Cache Line Size, default is 64, i.e., 5 2406383Sgblack@eecs.umich.edu TestCPUClass.CoreParams.CP0_Config1_DA = 1 # D-Cache Associativity, default is 2, i.e. 1 2416376Sgblack@eecs.umich.edu TestCPUClass.CoreParams.CP0_Config1_C2 = 0 # Coprocessor 2 not implemented(?) 2426376Sgblack@eecs.umich.edu TestCPUClass.CoreParams.CP0_Config1_MD = 0 # MDMX ASE not implemented in Mips32 2436376Sgblack@eecs.umich.edu TestCPUClass.CoreParams.CP0_Config1_PC = 1 # Performance Counters Implemented 2446376Sgblack@eecs.umich.edu TestCPUClass.CoreParams.CP0_Config1_WR = 0 # Watch Registers Implemented 2456376Sgblack@eecs.umich.edu TestCPUClass.CoreParams.CP0_Config1_CA = 0 # Mips16e NOT implemented 2466376Sgblack@eecs.umich.edu TestCPUClass.CoreParams.CP0_Config1_EP = 0 # EJTag Not Implemented 2476376Sgblack@eecs.umich.edu TestCPUClass.CoreParams.CP0_Config1_FP = 0 # FPU Implemented 2486376Sgblack@eecs.umich.edu 2496383Sgblack@eecs.umich.edu #Config 2 Register 2506334Sgblack@eecs.umich.edu TestCPUClass.CoreParams.CP0_Config2_M = 1 # Config3 Implemented 2516334Sgblack@eecs.umich.edu TestCPUClass.CoreParams.CP0_Config2_TU = 0 # Tertiary Cache Control 2526376Sgblack@eecs.umich.edu TestCPUClass.CoreParams.CP0_Config2_TS = 0 # Tertiary Cache Sets Per Way 2536383Sgblack@eecs.umich.edu TestCPUClass.CoreParams.CP0_Config2_TL = 0 # Tertiary Cache Line Size 2546334Sgblack@eecs.umich.edu TestCPUClass.CoreParams.CP0_Config2_TA = 0 # Tertiary Cache Associativity 2556334Sgblack@eecs.umich.edu TestCPUClass.CoreParams.CP0_Config2_SU = 0 # Secondary Cache Control 2566383Sgblack@eecs.umich.edu TestCPUClass.CoreParams.CP0_Config2_SS = 0 # Secondary Cache Sets Per Way 2576376Sgblack@eecs.umich.edu TestCPUClass.CoreParams.CP0_Config2_SL = 0 # Secondary Cache Line Size 2586376Sgblack@eecs.umich.edu TestCPUClass.CoreParams.CP0_Config2_SA = 0 # Secondary Cache Associativity 2596383Sgblack@eecs.umich.edu 2606334Sgblack@eecs.umich.edu 2616334Sgblack@eecs.umich.edu #Config 3 Register 2626334Sgblack@eecs.umich.edu TestCPUClass.CoreParams.CP0_Config3_M = 0 # Config4 Not Implemented 2636376Sgblack@eecs.umich.edu TestCPUClass.CoreParams.CP0_Config3_DSPP = 1 # DSP ASE Present 2646383Sgblack@eecs.umich.edu TestCPUClass.CoreParams.CP0_Config3_LPA = 0 # Large Physical Addresses Not supported in Mips32 2656334Sgblack@eecs.umich.edu TestCPUClass.CoreParams.CP0_Config3_VEIC = 0 # EIC Supported 2666334Sgblack@eecs.umich.edu TestCPUClass.CoreParams.CP0_Config3_VInt = 0 # Vectored Interrupts Implemented 2676383Sgblack@eecs.umich.edu TestCPUClass.CoreParams.CP0_Config3_SP = 0 # Small Pages Supported (PageGrain reg. exists) 2686376Sgblack@eecs.umich.edu TestCPUClass.CoreParams.CP0_Config3_MT = 0 # MT Not present 2696383Sgblack@eecs.umich.edu TestCPUClass.CoreParams.CP0_Config3_SM = 0 # SmartMIPS ASE Not implemented 2706334Sgblack@eecs.umich.edu TestCPUClass.CoreParams.CP0_Config3_TL = 0 # TraceLogic Not implemented 2716334Sgblack@eecs.umich.edu 2726376Sgblack@eecs.umich.edu #SRS Ctl - HSS 2736383Sgblack@eecs.umich.edu TestCPUClass.CoreParams.CP0_SrsCtl_HSS = 3 # Four shadow register sets implemented 2746334Sgblack@eecs.umich.edu 2756334Sgblack@eecs.umich.edu 2766383Sgblack@eecs.umich.edu #TestCPUClass.CoreParams.tlb = TLB() 2776376Sgblack@eecs.umich.edu #TestCPUClass.CoreParams.UnifiedTLB = 1 2786376Sgblack@eecs.umich.edu