FSConfig.py revision 5133:a88763dd4a84
16019Shines@cs.fsu.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan 26019Shines@cs.fsu.edu# All rights reserved. 313168Smatt.horsnell@arm.com# 47100Sgblack@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 57100Sgblack@eecs.umich.edu# modification, are permitted provided that the following conditions are 67100Sgblack@eecs.umich.edu# met: redistributions of source code must retain the above copyright 77100Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 87100Sgblack@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 97100Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 107100Sgblack@eecs.umich.edu# documentation and/or other materials provided with the distribution; 117100Sgblack@eecs.umich.edu# neither the name of the copyright holders nor the names of its 127100Sgblack@eecs.umich.edu# contributors may be used to endorse or promote products derived from 137100Sgblack@eecs.umich.edu# this software without specific prior written permission. 147100Sgblack@eecs.umich.edu# 156019Shines@cs.fsu.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 166019Shines@cs.fsu.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 176019Shines@cs.fsu.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 186019Shines@cs.fsu.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 196019Shines@cs.fsu.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 206019Shines@cs.fsu.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 216019Shines@cs.fsu.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 226019Shines@cs.fsu.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 236019Shines@cs.fsu.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 246019Shines@cs.fsu.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 256019Shines@cs.fsu.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 266019Shines@cs.fsu.edu# 276019Shines@cs.fsu.edu# Authors: Kevin Lim 286019Shines@cs.fsu.edu 296019Shines@cs.fsu.eduimport m5 306019Shines@cs.fsu.edufrom m5 import makeList 316019Shines@cs.fsu.edufrom m5.objects import * 326019Shines@cs.fsu.edufrom Benchmarks import * 336019Shines@cs.fsu.edu 346019Shines@cs.fsu.educlass CowIdeDisk(IdeDisk): 356019Shines@cs.fsu.edu image = CowDiskImage(child=RawDiskImage(read_only=True), 366019Shines@cs.fsu.edu read_only=False) 376019Shines@cs.fsu.edu 386019Shines@cs.fsu.edu def childImage(self, ci): 396019Shines@cs.fsu.edu self.image.child.image_file = ci 406019Shines@cs.fsu.edu 416019Shines@cs.fsu.edudef makeLinuxAlphaSystem(mem_mode, mdesc = None): 426757SAli.Saidi@ARM.com class BaseTsunami(Tsunami): 436019Shines@cs.fsu.edu ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 446019Shines@cs.fsu.edu ide = IdeController(disks=[Parent.disk0, Parent.disk2], 456019Shines@cs.fsu.edu pci_func=0, pci_dev=0, pci_bus=0) 466019Shines@cs.fsu.edu 476019Shines@cs.fsu.edu self = LinuxAlphaSystem() 4811320Ssteve.reinhardt@amd.com if not mdesc: 496019Shines@cs.fsu.edu # generic system 509022Sgblack@eecs.umich.edu mdesc = SysConfig() 516019Shines@cs.fsu.edu self.readfile = mdesc.script() 5212640Sgiacomo.travaglini@arm.com self.iobus = Bus(bus_id=0) 5310037SARM gem5 Developers self.membus = Bus(bus_id=1) 5410037SARM gem5 Developers self.bridge = Bridge(delay='50ns', nack_delay='4ns') 557170Sgblack@eecs.umich.edu self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) 566253Sgblack@eecs.umich.edu self.bridge.side_a = self.iobus.port 5710037SARM gem5 Developers self.bridge.side_b = self.membus.port 587202Sgblack@eecs.umich.edu self.physmem.port = self.membus.port 5910037SARM gem5 Developers self.disk0 = CowIdeDisk(driveID='master') 606253Sgblack@eecs.umich.edu self.disk2 = CowIdeDisk(driveID='master') 6110611SAndreas.Sandberg@ARM.com self.disk0.childImage(mdesc.disk()) 626253Sgblack@eecs.umich.edu self.disk2.childImage(disk('linux-bigswap2.img')) 637396Sgblack@eecs.umich.edu self.tsunami = BaseTsunami() 6410037SARM gem5 Developers self.tsunami.attachIO(self.iobus) 6513168Smatt.horsnell@arm.com self.tsunami.ide.pio = self.iobus.port 668745Sgblack@eecs.umich.edu self.tsunami.ethernet.pio = self.iobus.port 677405SAli.Saidi@ARM.com self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 6810461SAndreas.Sandberg@ARM.com read_only = True)) 698782Sgblack@eecs.umich.edu self.intrctrl = IntrControl() 708782Sgblack@eecs.umich.edu self.mem_mode = mem_mode 718782Sgblack@eecs.umich.edu self.sim_console = SimConsole() 7210810Sbr@bsdpad.com self.kernel = binary('vmlinux') 7310810Sbr@bsdpad.com self.pal = binary('ts_osfpal') 7410810Sbr@bsdpad.com self.console = binary('console') 757259Sgblack@eecs.umich.edu self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 768757Sgblack@eecs.umich.edu 7710461SAndreas.Sandberg@ARM.com return self 788782Sgblack@eecs.umich.edu 798757Sgblack@eecs.umich.edudef makeSparcSystem(mem_mode, mdesc = None): 8012531Sandreas.sandberg@arm.com class CowMmDisk(MmDisk): 818777Sgblack@eecs.umich.edu image = CowDiskImage(child=RawDiskImage(read_only=True), 828782Sgblack@eecs.umich.edu read_only=False) 838756Sgblack@eecs.umich.edu 8410037SARM gem5 Developers def childImage(self, ci): 8510037SARM gem5 Developers self.image.child.image_file = ci 866019Shines@cs.fsu.edu 8712605Sgiacomo.travaglini@arm.com self = SparcSystem() 886757SAli.Saidi@ARM.com if not mdesc: 898757Sgblack@eecs.umich.edu # generic system 906019Shines@cs.fsu.edu mdesc = SysConfig() 918745Sgblack@eecs.umich.edu self.readfile = mdesc.script() 929384SAndreas.Sandberg@arm.com self.iobus = Bus(bus_id=0) 936397Sgblack@eecs.umich.edu self.membus = Bus(bus_id=1) 9412531Sandreas.sandberg@arm.com self.bridge = Bridge(delay='50ns', nack_delay='4ns') 958782Sgblack@eecs.umich.edu self.t1000 = T1000() 966019Shines@cs.fsu.edu self.t1000.attachOnChipIO(self.membus) 9710461SAndreas.Sandberg@ARM.com self.t1000.attachIO(self.iobus) 986397Sgblack@eecs.umich.edu self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True) 998335Snate@binkert.org self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True) 10012531Sandreas.sandberg@arm.com self.bridge.side_a = self.iobus.port 1019023Sgblack@eecs.umich.edu self.bridge.side_b = self.membus.port 1029023Sgblack@eecs.umich.edu self.physmem.port = self.membus.port 10310461SAndreas.Sandberg@ARM.com self.physmem2.port = self.membus.port 1048335Snate@binkert.org self.rom.port = self.membus.port 1056019Shines@cs.fsu.edu self.nvram.port = self.membus.port 10610196SCurtis.Dunham@arm.com self.hypervisor_desc.port = self.membus.port 10712222Sgabeblack@google.com self.partition_desc.port = self.membus.port 108 self.intrctrl = IntrControl() 109 self.disk0 = CowMmDisk() 110 self.disk0.childImage(disk('disk.s10hw2')) 111 self.disk0.pio = self.iobus.port 112 self.reset_bin = binary('reset_new.bin') 113 self.hypervisor_bin = binary('q_new.bin') 114 self.openboot_bin = binary('openboot_new.bin') 115 self.nvram_bin = binary('nvram1') 116 self.hypervisor_desc_bin = binary('1up-hv.bin') 117 self.partition_desc_bin = binary('1up-md.bin') 118 119 return self 120 121def makeX86System(mem_mode, mdesc = None): 122 self = X86System() 123 if not mdesc: 124 # generic system 125 mdesc = SysConfig() 126 self.readfile = mdesc.script() 127 128 # Physical memory 129 self.membus = Bus(bus_id=0) 130 self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) 131 self.physmem.port = self.membus.port 132 133 # Platform 134 self.opteron = Opteron() 135 136 self.intrctrl = IntrControl() 137 138 return self 139 140 141def makeDualRoot(testSystem, driveSystem, dumpfile): 142 self = Root() 143 self.testsys = testSystem 144 self.drivesys = driveSystem 145 self.etherlink = EtherLink() 146 self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 147 self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 148 149 if dumpfile: 150 self.etherdump = EtherDump(file=dumpfile) 151 self.etherlink.dump = Parent.etherdump 152 153 return self 154