FSConfig.py revision 13532:b1cacf73cd4e
1# Copyright (c) 2010-2012, 2015-2018 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2010-2011 Advanced Micro Devices, Inc. 14# Copyright (c) 2006-2008 The Regents of The University of Michigan 15# All rights reserved. 16# 17# Redistribution and use in source and binary forms, with or without 18# modification, are permitted provided that the following conditions are 19# met: redistributions of source code must retain the above copyright 20# notice, this list of conditions and the following disclaimer; 21# redistributions in binary form must reproduce the above copyright 22# notice, this list of conditions and the following disclaimer in the 23# documentation and/or other materials provided with the distribution; 24# neither the name of the copyright holders nor the names of its 25# contributors may be used to endorse or promote products derived from 26# this software without specific prior written permission. 27# 28# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39# 40# Authors: Kevin Lim 41 42from __future__ import print_function 43 44from m5.objects import * 45from Benchmarks import * 46from m5.util import * 47from common import PlatformConfig 48 49# Populate to reflect supported os types per target ISA 50os_types = { 'alpha' : [ 'linux' ], 51 'mips' : [ 'linux' ], 52 'sparc' : [ 'linux' ], 53 'x86' : [ 'linux' ], 54 'arm' : [ 'linux', 55 'android-gingerbread', 56 'android-ics', 57 'android-jellybean', 58 'android-kitkat', 59 'android-nougat', ], 60 } 61 62class CowIdeDisk(IdeDisk): 63 image = CowDiskImage(child=RawDiskImage(read_only=True), 64 read_only=False) 65 66 def childImage(self, ci): 67 self.image.child.image_file = ci 68 69class MemBus(SystemXBar): 70 badaddr_responder = BadAddr() 71 default = Self.badaddr_responder.pio 72 73def fillInCmdline(mdesc, template, **kwargs): 74 kwargs.setdefault('disk', mdesc.disk()) 75 kwargs.setdefault('rootdev', mdesc.rootdev()) 76 kwargs.setdefault('mem', mdesc.mem()) 77 kwargs.setdefault('script', mdesc.script()) 78 return template % kwargs 79 80def makeLinuxAlphaSystem(mem_mode, mdesc=None, ruby=False, cmdline=None): 81 82 class BaseTsunami(Tsunami): 83 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 84 ide = IdeController(disks=[Parent.disk0, Parent.disk2], 85 pci_func=0, pci_dev=0, pci_bus=0) 86 87 self = LinuxAlphaSystem() 88 if not mdesc: 89 # generic system 90 mdesc = SysConfig() 91 self.readfile = mdesc.script() 92 93 self.tsunami = BaseTsunami() 94 95 # Create the io bus to connect all device ports 96 self.iobus = IOXBar() 97 self.tsunami.attachIO(self.iobus) 98 99 self.tsunami.ide.pio = self.iobus.master 100 101 self.tsunami.ethernet.pio = self.iobus.master 102 103 if ruby: 104 # Store the dma devices for later connection to dma ruby ports. 105 # Append an underscore to dma_ports to avoid the SimObjectVector check. 106 self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma] 107 else: 108 self.membus = MemBus() 109 110 # By default the bridge responds to all addresses above the I/O 111 # base address (including the PCI config space) 112 IO_address_space_base = 0x80000000000 113 self.bridge = Bridge(delay='50ns', 114 ranges = [AddrRange(IO_address_space_base, Addr.max)]) 115 self.bridge.master = self.iobus.slave 116 self.bridge.slave = self.membus.master 117 118 self.tsunami.ide.dma = self.iobus.slave 119 self.tsunami.ethernet.dma = self.iobus.slave 120 121 self.system_port = self.membus.slave 122 123 self.mem_ranges = [AddrRange(mdesc.mem())] 124 self.disk0 = CowIdeDisk(driveID='master') 125 self.disk2 = CowIdeDisk(driveID='master') 126 self.disk0.childImage(mdesc.disk()) 127 self.disk2.childImage(disk('linux-bigswap2.img')) 128 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 129 read_only = True)) 130 self.intrctrl = IntrControl() 131 self.mem_mode = mem_mode 132 self.terminal = Terminal() 133 self.kernel = binary('vmlinux') 134 self.pal = binary('ts_osfpal') 135 self.console = binary('console') 136 if not cmdline: 137 cmdline = 'root=/dev/hda1 console=ttyS0' 138 self.boot_osflags = fillInCmdline(mdesc, cmdline) 139 140 return self 141 142def makeSparcSystem(mem_mode, mdesc=None, cmdline=None): 143 # Constants from iob.cc and uart8250.cc 144 iob_man_addr = 0x9800000000 145 uart_pio_size = 8 146 147 class CowMmDisk(MmDisk): 148 image = CowDiskImage(child=RawDiskImage(read_only=True), 149 read_only=False) 150 151 def childImage(self, ci): 152 self.image.child.image_file = ci 153 154 self = SparcSystem() 155 if not mdesc: 156 # generic system 157 mdesc = SysConfig() 158 self.readfile = mdesc.script() 159 self.iobus = IOXBar() 160 self.membus = MemBus() 161 self.bridge = Bridge(delay='50ns') 162 self.t1000 = T1000() 163 self.t1000.attachOnChipIO(self.membus) 164 self.t1000.attachIO(self.iobus) 165 self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'), 166 AddrRange(Addr('2GB'), size ='256MB')] 167 self.bridge.master = self.iobus.slave 168 self.bridge.slave = self.membus.master 169 self.rom.port = self.membus.master 170 self.nvram.port = self.membus.master 171 self.hypervisor_desc.port = self.membus.master 172 self.partition_desc.port = self.membus.master 173 self.intrctrl = IntrControl() 174 self.disk0 = CowMmDisk() 175 self.disk0.childImage(mdesc.disk()) 176 self.disk0.pio = self.iobus.master 177 178 # The puart0 and hvuart are placed on the IO bus, so create ranges 179 # for them. The remaining IO range is rather fragmented, so poke 180 # holes for the iob and partition descriptors etc. 181 self.bridge.ranges = \ 182 [ 183 AddrRange(self.t1000.puart0.pio_addr, 184 self.t1000.puart0.pio_addr + uart_pio_size - 1), 185 AddrRange(self.disk0.pio_addr, 186 self.t1000.fake_jbi.pio_addr + 187 self.t1000.fake_jbi.pio_size - 1), 188 AddrRange(self.t1000.fake_clk.pio_addr, 189 iob_man_addr - 1), 190 AddrRange(self.t1000.fake_l2_1.pio_addr, 191 self.t1000.fake_ssi.pio_addr + 192 self.t1000.fake_ssi.pio_size - 1), 193 AddrRange(self.t1000.hvuart.pio_addr, 194 self.t1000.hvuart.pio_addr + uart_pio_size - 1) 195 ] 196 self.reset_bin = binary('reset_new.bin') 197 self.hypervisor_bin = binary('q_new.bin') 198 self.openboot_bin = binary('openboot_new.bin') 199 self.nvram_bin = binary('nvram1') 200 self.hypervisor_desc_bin = binary('1up-hv.bin') 201 self.partition_desc_bin = binary('1up-md.bin') 202 203 self.system_port = self.membus.slave 204 205 return self 206 207def makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None, 208 dtb_filename=None, bare_metal=False, cmdline=None, 209 external_memory="", ruby=False, security=False, 210 ignore_dtb=False): 211 assert machine_type 212 213 default_dtbs = { 214 "RealViewPBX": None, 215 "VExpress_EMM": "vexpress.aarch32.ll_20131205.0-gem5.%dcpu.dtb" % num_cpus, 216 "VExpress_EMM64": "vexpress.aarch64.20140821.dtb", 217 } 218 219 default_kernels = { 220 "RealViewPBX": "vmlinux.arm.smp.fb.2.6.38.8", 221 "VExpress_EMM": "vmlinux.aarch32.ll_20131205.0-gem5", 222 "VExpress_EMM64": "vmlinux.aarch64.20140821", 223 } 224 225 pci_devices = [] 226 227 if bare_metal: 228 self = ArmSystem() 229 else: 230 self = LinuxArmSystem() 231 232 if not mdesc: 233 # generic system 234 mdesc = SysConfig() 235 236 self.readfile = mdesc.script() 237 self.iobus = IOXBar() 238 if not ruby: 239 self.bridge = Bridge(delay='50ns') 240 self.bridge.master = self.iobus.slave 241 self.membus = MemBus() 242 self.membus.badaddr_responder.warn_access = "warn" 243 self.bridge.slave = self.membus.master 244 245 self.mem_mode = mem_mode 246 247 platform_class = PlatformConfig.get(machine_type) 248 # Resolve the real platform name, the original machine_type 249 # variable might have been an alias. 250 machine_type = platform_class.__name__ 251 self.realview = platform_class() 252 253 if not dtb_filename and not (bare_metal or ignore_dtb): 254 try: 255 dtb_filename = default_dtbs[machine_type] 256 except KeyError: 257 fatal("No DTB specified and no default DTB known for '%s'" % \ 258 machine_type) 259 260 if isinstance(self.realview, VExpress_EMM64): 261 if os.path.split(mdesc.disk())[-1] == 'linux-aarch32-ael.img': 262 print("Selected 64-bit ARM architecture, updating default " 263 "disk image...") 264 mdesc.diskname = 'linaro-minimal-aarch64.img' 265 266 267 # Attach any PCI devices this platform supports 268 self.realview.attachPciDevices() 269 270 self.cf0 = CowIdeDisk(driveID='master') 271 self.cf0.childImage(mdesc.disk()) 272 # Old platforms have a built-in IDE or CF controller. Default to 273 # the IDE controller if both exist. New platforms expect the 274 # storage controller to be added from the config script. 275 if hasattr(self.realview, "ide"): 276 self.realview.ide.disks = [self.cf0] 277 elif hasattr(self.realview, "cf_ctrl"): 278 self.realview.cf_ctrl.disks = [self.cf0] 279 else: 280 self.pci_ide = IdeController(disks=[self.cf0]) 281 pci_devices.append(self.pci_ide) 282 283 self.mem_ranges = [] 284 size_remain = long(Addr(mdesc.mem())) 285 for region in self.realview._mem_regions: 286 if size_remain > long(region[1]): 287 self.mem_ranges.append(AddrRange(region[0], size=region[1])) 288 size_remain = size_remain - long(region[1]) 289 else: 290 self.mem_ranges.append(AddrRange(region[0], size=size_remain)) 291 size_remain = 0 292 break 293 warn("Memory size specified spans more than one region. Creating" \ 294 " another memory controller for that range.") 295 296 if size_remain > 0: 297 fatal("The currently selected ARM platforms doesn't support" \ 298 " the amount of DRAM you've selected. Please try" \ 299 " another platform") 300 301 self.have_security = security 302 303 if bare_metal: 304 # EOT character on UART will end the simulation 305 self.realview.uart[0].end_on_eot = True 306 else: 307 if machine_type in default_kernels: 308 self.kernel = binary(default_kernels[machine_type]) 309 310 if dtb_filename and not ignore_dtb: 311 self.dtb_filename = binary(dtb_filename) 312 313 self.machine_type = machine_type if machine_type in ArmMachineType.map \ 314 else "DTOnly" 315 316 # Ensure that writes to the UART actually go out early in the boot 317 if not cmdline: 318 cmdline = 'earlyprintk=pl011,0x1c090000 console=ttyAMA0 ' + \ 319 'lpj=19988480 norandmaps rw loglevel=8 ' + \ 320 'mem=%(mem)s root=%(rootdev)s' 321 322 # When using external memory, gem5 writes the boot loader to nvmem 323 # and then SST will read from it, but SST can only get to nvmem from 324 # iobus, as gem5's membus is only used for initialization and 325 # SST doesn't use it. Attaching nvmem to iobus solves this issue. 326 # During initialization, system_port -> membus -> iobus -> nvmem. 327 if external_memory: 328 self.realview.setupBootLoader(self.iobus, self, binary) 329 elif ruby: 330 self.realview.setupBootLoader(None, self, binary) 331 else: 332 self.realview.setupBootLoader(self.membus, self, binary) 333 334 if hasattr(self.realview.gic, 'cpu_addr'): 335 self.gic_cpu_addr = self.realview.gic.cpu_addr 336 337 self.flags_addr = self.realview.realview_io.pio_addr + 0x30 338 339 # This check is for users who have previously put 'android' in 340 # the disk image filename to tell the config scripts to 341 # prepare the kernel with android-specific boot options. That 342 # behavior has been replaced with a more explicit option per 343 # the error message below. The disk can have any name now and 344 # doesn't need to include 'android' substring. 345 if (os.path.split(mdesc.disk())[-1]).lower().count('android'): 346 if 'android' not in mdesc.os_type(): 347 fatal("It looks like you are trying to boot an Android " \ 348 "platform. To boot Android, you must specify " \ 349 "--os-type with an appropriate Android release on " \ 350 "the command line.") 351 352 # android-specific tweaks 353 if 'android' in mdesc.os_type(): 354 # generic tweaks 355 cmdline += " init=/init" 356 357 # release-specific tweaks 358 if 'kitkat' in mdesc.os_type(): 359 cmdline += " androidboot.hardware=gem5 qemu=1 qemu.gles=0 " + \ 360 "android.bootanim=0 " 361 elif 'nougat' in mdesc.os_type(): 362 cmdline += " androidboot.hardware=gem5 qemu=1 qemu.gles=0 " + \ 363 "android.bootanim=0 " + \ 364 "vmalloc=640MB " + \ 365 "android.early.fstab=/fstab.gem5 " + \ 366 "androidboot.selinux=permissive " + \ 367 "video=Virtual-1:1920x1080-16" 368 369 self.boot_osflags = fillInCmdline(mdesc, cmdline) 370 371 if external_memory: 372 # I/O traffic enters iobus 373 self.external_io = ExternalMaster(port_data="external_io", 374 port_type=external_memory) 375 self.external_io.port = self.iobus.slave 376 377 # Ensure iocache only receives traffic destined for (actual) memory. 378 self.iocache = ExternalSlave(port_data="iocache", 379 port_type=external_memory, 380 addr_ranges=self.mem_ranges) 381 self.iocache.port = self.iobus.master 382 383 # Let system_port get to nvmem and nothing else. 384 self.bridge.ranges = [self.realview.nvmem.range] 385 386 self.realview.attachOnChipIO(self.iobus) 387 # Attach off-chip devices 388 self.realview.attachIO(self.iobus) 389 elif ruby: 390 self._dma_ports = [ ] 391 self.realview.attachOnChipIO(self.iobus, dma_ports=self._dma_ports) 392 self.realview.attachIO(self.iobus, dma_ports=self._dma_ports) 393 else: 394 self.realview.attachOnChipIO(self.membus, self.bridge) 395 # Attach off-chip devices 396 self.realview.attachIO(self.iobus) 397 398 for dev_id, dev in enumerate(pci_devices): 399 dev.pci_bus, dev.pci_dev, dev.pci_func = (0, dev_id + 1, 0) 400 self.realview.attachPciDevice( 401 dev, self.iobus, 402 dma_ports=self._dma_ports if ruby else None) 403 404 self.intrctrl = IntrControl() 405 self.terminal = Terminal() 406 self.vncserver = VncServer() 407 408 if not ruby: 409 self.system_port = self.membus.slave 410 411 if ruby: 412 if buildEnv['PROTOCOL'] == 'MI_example' and num_cpus > 1: 413 fatal("The MI_example protocol cannot implement Load/Store " 414 "Exclusive operations. Multicore ARM systems configured " 415 "with the MI_example protocol will not work properly.") 416 warn("You are trying to use Ruby on ARM, which is not working " 417 "properly yet.") 418 419 return self 420 421 422def makeLinuxMipsSystem(mem_mode, mdesc=None, cmdline=None): 423 class BaseMalta(Malta): 424 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 425 ide = IdeController(disks=[Parent.disk0, Parent.disk2], 426 pci_func=0, pci_dev=0, pci_bus=0) 427 428 self = LinuxMipsSystem() 429 if not mdesc: 430 # generic system 431 mdesc = SysConfig() 432 self.readfile = mdesc.script() 433 self.iobus = IOXBar() 434 self.membus = MemBus() 435 self.bridge = Bridge(delay='50ns') 436 self.mem_ranges = [AddrRange('1GB')] 437 self.bridge.master = self.iobus.slave 438 self.bridge.slave = self.membus.master 439 self.disk0 = CowIdeDisk(driveID='master') 440 self.disk2 = CowIdeDisk(driveID='master') 441 self.disk0.childImage(mdesc.disk()) 442 self.disk2.childImage(disk('linux-bigswap2.img')) 443 self.malta = BaseMalta() 444 self.malta.attachIO(self.iobus) 445 self.malta.ide.pio = self.iobus.master 446 self.malta.ide.dma = self.iobus.slave 447 self.malta.ethernet.pio = self.iobus.master 448 self.malta.ethernet.dma = self.iobus.slave 449 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 450 read_only = True)) 451 self.intrctrl = IntrControl() 452 self.mem_mode = mem_mode 453 self.terminal = Terminal() 454 self.kernel = binary('mips/vmlinux') 455 self.console = binary('mips/console') 456 if not cmdline: 457 cmdline = 'root=/dev/hda1 console=ttyS0' 458 self.boot_osflags = fillInCmdline(mdesc, cmdline) 459 460 self.system_port = self.membus.slave 461 462 return self 463 464def x86IOAddress(port): 465 IO_address_space_base = 0x8000000000000000 466 return IO_address_space_base + port 467 468def connectX86ClassicSystem(x86_sys, numCPUs): 469 # Constants similar to x86_traits.hh 470 IO_address_space_base = 0x8000000000000000 471 pci_config_address_space_base = 0xc000000000000000 472 interrupts_address_space_base = 0xa000000000000000 473 APIC_range_size = 1 << 12; 474 475 x86_sys.membus = MemBus() 476 477 # North Bridge 478 x86_sys.iobus = IOXBar() 479 x86_sys.bridge = Bridge(delay='50ns') 480 x86_sys.bridge.master = x86_sys.iobus.slave 481 x86_sys.bridge.slave = x86_sys.membus.master 482 # Allow the bridge to pass through: 483 # 1) kernel configured PCI device memory map address: address range 484 # [0xC0000000, 0xFFFF0000). (The upper 64kB are reserved for m5ops.) 485 # 2) the bridge to pass through the IO APIC (two pages, already contained in 1), 486 # 3) everything in the IO address range up to the local APIC, and 487 # 4) then the entire PCI address space and beyond. 488 x86_sys.bridge.ranges = \ 489 [ 490 AddrRange(0xC0000000, 0xFFFF0000), 491 AddrRange(IO_address_space_base, 492 interrupts_address_space_base - 1), 493 AddrRange(pci_config_address_space_base, 494 Addr.max) 495 ] 496 497 # Create a bridge from the IO bus to the memory bus to allow access to 498 # the local APIC (two pages) 499 x86_sys.apicbridge = Bridge(delay='50ns') 500 x86_sys.apicbridge.slave = x86_sys.iobus.master 501 x86_sys.apicbridge.master = x86_sys.membus.slave 502 x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base, 503 interrupts_address_space_base + 504 numCPUs * APIC_range_size 505 - 1)] 506 507 # connect the io bus 508 x86_sys.pc.attachIO(x86_sys.iobus) 509 510 x86_sys.system_port = x86_sys.membus.slave 511 512def connectX86RubySystem(x86_sys): 513 # North Bridge 514 x86_sys.iobus = IOXBar() 515 516 # add the ide to the list of dma devices that later need to attach to 517 # dma controllers 518 x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma] 519 x86_sys.pc.attachIO(x86_sys.iobus, x86_sys._dma_ports) 520 521 522def makeX86System(mem_mode, numCPUs=1, mdesc=None, self=None, Ruby=False): 523 if self == None: 524 self = X86System() 525 526 if not mdesc: 527 # generic system 528 mdesc = SysConfig() 529 self.readfile = mdesc.script() 530 531 self.mem_mode = mem_mode 532 533 # Physical memory 534 # On the PC platform, the memory region 0xC0000000-0xFFFFFFFF is reserved 535 # for various devices. Hence, if the physical memory size is greater than 536 # 3GB, we need to split it into two parts. 537 excess_mem_size = \ 538 convert.toMemorySize(mdesc.mem()) - convert.toMemorySize('3GB') 539 if excess_mem_size <= 0: 540 self.mem_ranges = [AddrRange(mdesc.mem())] 541 else: 542 warn("Physical memory size specified is %s which is greater than " \ 543 "3GB. Twice the number of memory controllers would be " \ 544 "created." % (mdesc.mem())) 545 546 self.mem_ranges = [AddrRange('3GB'), 547 AddrRange(Addr('4GB'), size = excess_mem_size)] 548 549 # Platform 550 self.pc = Pc() 551 552 # Create and connect the busses required by each memory system 553 if Ruby: 554 connectX86RubySystem(self) 555 else: 556 connectX86ClassicSystem(self, numCPUs) 557 558 self.intrctrl = IntrControl() 559 560 # Disks 561 disk0 = CowIdeDisk(driveID='master') 562 disk2 = CowIdeDisk(driveID='master') 563 disk0.childImage(mdesc.disk()) 564 disk2.childImage(disk('linux-bigswap2.img')) 565 self.pc.south_bridge.ide.disks = [disk0, disk2] 566 567 # Add in a Bios information structure. 568 structures = [X86SMBiosBiosInformation()] 569 self.smbios_table.structures = structures 570 571 # Set up the Intel MP table 572 base_entries = [] 573 ext_entries = [] 574 for i in xrange(numCPUs): 575 bp = X86IntelMPProcessor( 576 local_apic_id = i, 577 local_apic_version = 0x14, 578 enable = True, 579 bootstrap = (i == 0)) 580 base_entries.append(bp) 581 io_apic = X86IntelMPIOAPIC( 582 id = numCPUs, 583 version = 0x11, 584 enable = True, 585 address = 0xfec00000) 586 self.pc.south_bridge.io_apic.apic_id = io_apic.id 587 base_entries.append(io_apic) 588 # In gem5 Pc::calcPciConfigAddr(), it required "assert(bus==0)", 589 # but linux kernel cannot config PCI device if it was not connected to PCI bus, 590 # so we fix PCI bus id to 0, and ISA bus id to 1. 591 pci_bus = X86IntelMPBus(bus_id = 0, bus_type='PCI ') 592 base_entries.append(pci_bus) 593 isa_bus = X86IntelMPBus(bus_id = 1, bus_type='ISA ') 594 base_entries.append(isa_bus) 595 connect_busses = X86IntelMPBusHierarchy(bus_id=1, 596 subtractive_decode=True, parent_bus=0) 597 ext_entries.append(connect_busses) 598 pci_dev4_inta = X86IntelMPIOIntAssignment( 599 interrupt_type = 'INT', 600 polarity = 'ConformPolarity', 601 trigger = 'ConformTrigger', 602 source_bus_id = 0, 603 source_bus_irq = 0 + (4 << 2), 604 dest_io_apic_id = io_apic.id, 605 dest_io_apic_intin = 16) 606 base_entries.append(pci_dev4_inta) 607 def assignISAInt(irq, apicPin): 608 assign_8259_to_apic = X86IntelMPIOIntAssignment( 609 interrupt_type = 'ExtInt', 610 polarity = 'ConformPolarity', 611 trigger = 'ConformTrigger', 612 source_bus_id = 1, 613 source_bus_irq = irq, 614 dest_io_apic_id = io_apic.id, 615 dest_io_apic_intin = 0) 616 base_entries.append(assign_8259_to_apic) 617 assign_to_apic = X86IntelMPIOIntAssignment( 618 interrupt_type = 'INT', 619 polarity = 'ConformPolarity', 620 trigger = 'ConformTrigger', 621 source_bus_id = 1, 622 source_bus_irq = irq, 623 dest_io_apic_id = io_apic.id, 624 dest_io_apic_intin = apicPin) 625 base_entries.append(assign_to_apic) 626 assignISAInt(0, 2) 627 assignISAInt(1, 1) 628 for i in range(3, 15): 629 assignISAInt(i, i) 630 self.intel_mp_table.base_entries = base_entries 631 self.intel_mp_table.ext_entries = ext_entries 632 633def makeLinuxX86System(mem_mode, numCPUs=1, mdesc=None, Ruby=False, 634 cmdline=None): 635 self = LinuxX86System() 636 637 # Build up the x86 system and then specialize it for Linux 638 makeX86System(mem_mode, numCPUs, mdesc, self, Ruby) 639 640 # We assume below that there's at least 1MB of memory. We'll require 2 641 # just to avoid corner cases. 642 phys_mem_size = sum(map(lambda r: r.size(), self.mem_ranges)) 643 assert(phys_mem_size >= 0x200000) 644 assert(len(self.mem_ranges) <= 2) 645 646 entries = \ 647 [ 648 # Mark the first megabyte of memory as reserved 649 X86E820Entry(addr = 0, size = '639kB', range_type = 1), 650 X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2), 651 # Mark the rest of physical memory as available 652 X86E820Entry(addr = 0x100000, 653 size = '%dB' % (self.mem_ranges[0].size() - 0x100000), 654 range_type = 1), 655 ] 656 657 # Mark [mem_size, 3GB) as reserved if memory less than 3GB, which force 658 # IO devices to be mapped to [0xC0000000, 0xFFFF0000). Requests to this 659 # specific range can pass though bridge to iobus. 660 if len(self.mem_ranges) == 1: 661 entries.append(X86E820Entry(addr = self.mem_ranges[0].size(), 662 size='%dB' % (0xC0000000 - self.mem_ranges[0].size()), 663 range_type=2)) 664 665 # Reserve the last 16kB of the 32-bit address space for the m5op interface 666 entries.append(X86E820Entry(addr=0xFFFF0000, size='64kB', range_type=2)) 667 668 # In case the physical memory is greater than 3GB, we split it into two 669 # parts and add a separate e820 entry for the second part. This entry 670 # starts at 0x100000000, which is the first address after the space 671 # reserved for devices. 672 if len(self.mem_ranges) == 2: 673 entries.append(X86E820Entry(addr = 0x100000000, 674 size = '%dB' % (self.mem_ranges[1].size()), range_type = 1)) 675 676 self.e820_table.entries = entries 677 678 # Command line 679 if not cmdline: 680 cmdline = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1' 681 self.boot_osflags = fillInCmdline(mdesc, cmdline) 682 self.kernel = binary('x86_64-vmlinux-2.6.22.9') 683 return self 684 685 686def makeDualRoot(full_system, testSystem, driveSystem, dumpfile): 687 self = Root(full_system = full_system) 688 self.testsys = testSystem 689 self.drivesys = driveSystem 690 self.etherlink = EtherLink() 691 692 if hasattr(testSystem, 'realview'): 693 self.etherlink.int0 = Parent.testsys.realview.ethernet.interface 694 self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface 695 elif hasattr(testSystem, 'tsunami'): 696 self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 697 self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 698 else: 699 fatal("Don't know how to connect these system together") 700 701 if dumpfile: 702 self.etherdump = EtherDump(file=dumpfile) 703 self.etherlink.dump = Parent.etherdump 704 705 return self 706 707 708def makeDistRoot(testSystem, 709 rank, 710 size, 711 server_name, 712 server_port, 713 sync_repeat, 714 sync_start, 715 linkspeed, 716 linkdelay, 717 dumpfile): 718 self = Root(full_system = True) 719 self.testsys = testSystem 720 721 self.etherlink = DistEtherLink(speed = linkspeed, 722 delay = linkdelay, 723 dist_rank = rank, 724 dist_size = size, 725 server_name = server_name, 726 server_port = server_port, 727 sync_start = sync_start, 728 sync_repeat = sync_repeat) 729 730 if hasattr(testSystem, 'realview'): 731 self.etherlink.int0 = Parent.testsys.realview.ethernet.interface 732 elif hasattr(testSystem, 'tsunami'): 733 self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 734 else: 735 fatal("Don't know how to connect DistEtherLink to this system") 736 737 if dumpfile: 738 self.etherdump = EtherDump(file=dumpfile) 739 self.etherlink.dump = Parent.etherdump 740 741 return self 742