FSConfig.py revision 12598:b80b2d9a251b
1955SN/A# Copyright (c) 2010-2012, 2015-2018 ARM Limited 2955SN/A# All rights reserved. 35871Snate@binkert.org# 41762SN/A# The license below extends only to copyright in the software and shall 5955SN/A# not be construed as granting a license to any other intellectual 6955SN/A# property including but not limited to intellectual property relating 7955SN/A# to a hardware implementation of the functionality of the software 8955SN/A# licensed hereunder. You may use the software subject to the license 9955SN/A# terms below provided that you ensure that this notice is replicated 10955SN/A# unmodified and in its entirety in all distributions of the software, 11955SN/A# modified or unmodified, in source code or in binary form. 12955SN/A# 13955SN/A# Copyright (c) 2010-2011 Advanced Micro Devices, Inc. 14955SN/A# Copyright (c) 2006-2008 The Regents of The University of Michigan 15955SN/A# All rights reserved. 16955SN/A# 17955SN/A# Redistribution and use in source and binary forms, with or without 18955SN/A# modification, are permitted provided that the following conditions are 19955SN/A# met: redistributions of source code must retain the above copyright 20955SN/A# notice, this list of conditions and the following disclaimer; 21955SN/A# redistributions in binary form must reproduce the above copyright 22955SN/A# notice, this list of conditions and the following disclaimer in the 23955SN/A# documentation and/or other materials provided with the distribution; 24955SN/A# neither the name of the copyright holders nor the names of its 25955SN/A# contributors may be used to endorse or promote products derived from 26955SN/A# this software without specific prior written permission. 27955SN/A# 28955SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292665Ssaidi@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302665Ssaidi@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 315863Snate@binkert.org# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32955SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33955SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34955SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35955SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36955SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372632Sstever@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382632Sstever@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392632Sstever@eecs.umich.edu# 402632Sstever@eecs.umich.edu# Authors: Kevin Lim 41955SN/A 422632Sstever@eecs.umich.edufrom __future__ import print_function 432632Sstever@eecs.umich.edu 442761Sstever@eecs.umich.edufrom m5.objects import * 452632Sstever@eecs.umich.edufrom Benchmarks import * 462632Sstever@eecs.umich.edufrom m5.util import * 472632Sstever@eecs.umich.edufrom common import PlatformConfig 482761Sstever@eecs.umich.edu 492761Sstever@eecs.umich.edu# Populate to reflect supported os types per target ISA 502761Sstever@eecs.umich.eduos_types = { 'alpha' : [ 'linux' ], 512632Sstever@eecs.umich.edu 'mips' : [ 'linux' ], 522632Sstever@eecs.umich.edu 'sparc' : [ 'linux' ], 532761Sstever@eecs.umich.edu 'x86' : [ 'linux' ], 542761Sstever@eecs.umich.edu 'arm' : [ 'linux', 552761Sstever@eecs.umich.edu 'android-gingerbread', 562761Sstever@eecs.umich.edu 'android-ics', 572761Sstever@eecs.umich.edu 'android-jellybean', 582632Sstever@eecs.umich.edu 'android-kitkat', 592632Sstever@eecs.umich.edu 'android-nougat', ], 602632Sstever@eecs.umich.edu } 612632Sstever@eecs.umich.edu 622632Sstever@eecs.umich.educlass CowIdeDisk(IdeDisk): 632632Sstever@eecs.umich.edu image = CowDiskImage(child=RawDiskImage(read_only=True), 642632Sstever@eecs.umich.edu read_only=False) 65955SN/A 66955SN/A def childImage(self, ci): 67955SN/A self.image.child.image_file = ci 685863Snate@binkert.org 695863Snate@binkert.orgclass MemBus(SystemXBar): 705863Snate@binkert.org badaddr_responder = BadAddr() 715863Snate@binkert.org default = Self.badaddr_responder.pio 725863Snate@binkert.org 735863Snate@binkert.orgdef fillInCmdline(mdesc, template, **kwargs): 745863Snate@binkert.org kwargs.setdefault('disk', mdesc.disk()) 755863Snate@binkert.org kwargs.setdefault('rootdev', mdesc.rootdev()) 765863Snate@binkert.org kwargs.setdefault('mem', mdesc.mem()) 775863Snate@binkert.org kwargs.setdefault('script', mdesc.script()) 785863Snate@binkert.org return template % kwargs 795863Snate@binkert.org 805863Snate@binkert.orgdef makeLinuxAlphaSystem(mem_mode, mdesc=None, ruby=False, cmdline=None): 815863Snate@binkert.org 825863Snate@binkert.org class BaseTsunami(Tsunami): 835863Snate@binkert.org ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 845863Snate@binkert.org ide = IdeController(disks=[Parent.disk0, Parent.disk2], 855863Snate@binkert.org pci_func=0, pci_dev=0, pci_bus=0) 865863Snate@binkert.org 875863Snate@binkert.org self = LinuxAlphaSystem() 885863Snate@binkert.org if not mdesc: 895863Snate@binkert.org # generic system 905863Snate@binkert.org mdesc = SysConfig() 915863Snate@binkert.org self.readfile = mdesc.script() 925863Snate@binkert.org 935863Snate@binkert.org self.tsunami = BaseTsunami() 945863Snate@binkert.org 955863Snate@binkert.org # Create the io bus to connect all device ports 965863Snate@binkert.org self.iobus = IOXBar() 975863Snate@binkert.org self.tsunami.attachIO(self.iobus) 985863Snate@binkert.org 99955SN/A self.tsunami.ide.pio = self.iobus.master 1005396Ssaidi@eecs.umich.edu 1015863Snate@binkert.org self.tsunami.ethernet.pio = self.iobus.master 1025863Snate@binkert.org 1034202Sbinkertn@umich.edu if ruby: 1045863Snate@binkert.org # Store the dma devices for later connection to dma ruby ports. 1055863Snate@binkert.org # Append an underscore to dma_ports to avoid the SimObjectVector check. 1065863Snate@binkert.org self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma] 1075863Snate@binkert.org else: 108955SN/A self.membus = MemBus() 1095273Sstever@gmail.com 1105871Snate@binkert.org # By default the bridge responds to all addresses above the I/O 1115273Sstever@gmail.com # base address (including the PCI config space) 1125871Snate@binkert.org IO_address_space_base = 0x80000000000 1135863Snate@binkert.org self.bridge = Bridge(delay='50ns', 1145863Snate@binkert.org ranges = [AddrRange(IO_address_space_base, Addr.max)]) 1155863Snate@binkert.org self.bridge.master = self.iobus.slave 1165871Snate@binkert.org self.bridge.slave = self.membus.master 1175871Snate@binkert.org 1185871Snate@binkert.org self.tsunami.ide.dma = self.iobus.slave 1195871Snate@binkert.org self.tsunami.ethernet.dma = self.iobus.slave 1205871Snate@binkert.org 1215871Snate@binkert.org self.system_port = self.membus.slave 1225871Snate@binkert.org 1235871Snate@binkert.org self.mem_ranges = [AddrRange(mdesc.mem())] 1245871Snate@binkert.org self.disk0 = CowIdeDisk(driveID='master') 1255871Snate@binkert.org self.disk2 = CowIdeDisk(driveID='master') 1265871Snate@binkert.org self.disk0.childImage(mdesc.disk()) 1275871Snate@binkert.org self.disk2.childImage(disk('linux-bigswap2.img')) 1285871Snate@binkert.org self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 1295871Snate@binkert.org read_only = True)) 1305871Snate@binkert.org self.intrctrl = IntrControl() 1315863Snate@binkert.org self.mem_mode = mem_mode 1325227Ssaidi@eecs.umich.edu self.terminal = Terminal() 1335396Ssaidi@eecs.umich.edu self.kernel = binary('vmlinux') 1345396Ssaidi@eecs.umich.edu self.pal = binary('ts_osfpal') 1355396Ssaidi@eecs.umich.edu self.console = binary('console') 1365396Ssaidi@eecs.umich.edu if not cmdline: 1375396Ssaidi@eecs.umich.edu cmdline = 'root=/dev/hda1 console=ttyS0' 1385396Ssaidi@eecs.umich.edu self.boot_osflags = fillInCmdline(mdesc, cmdline) 1395396Ssaidi@eecs.umich.edu 1405396Ssaidi@eecs.umich.edu return self 1415588Ssaidi@eecs.umich.edu 1425396Ssaidi@eecs.umich.edudef makeSparcSystem(mem_mode, mdesc=None, cmdline=None): 1435396Ssaidi@eecs.umich.edu # Constants from iob.cc and uart8250.cc 1445396Ssaidi@eecs.umich.edu iob_man_addr = 0x9800000000 1455396Ssaidi@eecs.umich.edu uart_pio_size = 8 1465396Ssaidi@eecs.umich.edu 1475396Ssaidi@eecs.umich.edu class CowMmDisk(MmDisk): 1485396Ssaidi@eecs.umich.edu image = CowDiskImage(child=RawDiskImage(read_only=True), 1495396Ssaidi@eecs.umich.edu read_only=False) 1505396Ssaidi@eecs.umich.edu 1515396Ssaidi@eecs.umich.edu def childImage(self, ci): 1525396Ssaidi@eecs.umich.edu self.image.child.image_file = ci 1535396Ssaidi@eecs.umich.edu 1545396Ssaidi@eecs.umich.edu self = SparcSystem() 1555396Ssaidi@eecs.umich.edu if not mdesc: 1565871Snate@binkert.org # generic system 1575871Snate@binkert.org mdesc = SysConfig() 1585871Snate@binkert.org self.readfile = mdesc.script() 1595871Snate@binkert.org self.iobus = IOXBar() 1605871Snate@binkert.org self.membus = MemBus() 1615871Snate@binkert.org self.bridge = Bridge(delay='50ns') 162955SN/A self.t1000 = T1000() 1635871Snate@binkert.org self.t1000.attachOnChipIO(self.membus) 1645871Snate@binkert.org self.t1000.attachIO(self.iobus) 1655871Snate@binkert.org self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'), 1665871Snate@binkert.org AddrRange(Addr('2GB'), size ='256MB')] 167955SN/A self.bridge.master = self.iobus.slave 1685871Snate@binkert.org self.bridge.slave = self.membus.master 1695871Snate@binkert.org self.rom.port = self.membus.master 1705871Snate@binkert.org self.nvram.port = self.membus.master 1711533SN/A self.hypervisor_desc.port = self.membus.master 1725871Snate@binkert.org self.partition_desc.port = self.membus.master 1735871Snate@binkert.org self.intrctrl = IntrControl() 1745863Snate@binkert.org self.disk0 = CowMmDisk() 1755871Snate@binkert.org self.disk0.childImage(mdesc.disk()) 1765871Snate@binkert.org self.disk0.pio = self.iobus.master 1775871Snate@binkert.org 1785871Snate@binkert.org # The puart0 and hvuart are placed on the IO bus, so create ranges 1795871Snate@binkert.org # for them. The remaining IO range is rather fragmented, so poke 1805863Snate@binkert.org # holes for the iob and partition descriptors etc. 1815871Snate@binkert.org self.bridge.ranges = \ 1825863Snate@binkert.org [ 1835871Snate@binkert.org AddrRange(self.t1000.puart0.pio_addr, 1844678Snate@binkert.org self.t1000.puart0.pio_addr + uart_pio_size - 1), 1854678Snate@binkert.org AddrRange(self.disk0.pio_addr, 1864678Snate@binkert.org self.t1000.fake_jbi.pio_addr + 1874678Snate@binkert.org self.t1000.fake_jbi.pio_size - 1), 1884678Snate@binkert.org AddrRange(self.t1000.fake_clk.pio_addr, 1894678Snate@binkert.org iob_man_addr - 1), 1904678Snate@binkert.org AddrRange(self.t1000.fake_l2_1.pio_addr, 1914678Snate@binkert.org self.t1000.fake_ssi.pio_addr + 1924678Snate@binkert.org self.t1000.fake_ssi.pio_size - 1), 1934678Snate@binkert.org AddrRange(self.t1000.hvuart.pio_addr, 1944678Snate@binkert.org self.t1000.hvuart.pio_addr + uart_pio_size - 1) 1954678Snate@binkert.org ] 1965871Snate@binkert.org self.reset_bin = binary('reset_new.bin') 1974678Snate@binkert.org self.hypervisor_bin = binary('q_new.bin') 1985871Snate@binkert.org self.openboot_bin = binary('openboot_new.bin') 1995871Snate@binkert.org self.nvram_bin = binary('nvram1') 2005871Snate@binkert.org self.hypervisor_desc_bin = binary('1up-hv.bin') 2015871Snate@binkert.org self.partition_desc_bin = binary('1up-md.bin') 2025871Snate@binkert.org 2035871Snate@binkert.org self.system_port = self.membus.slave 2045871Snate@binkert.org 2055871Snate@binkert.org return self 2065871Snate@binkert.org 2075871Snate@binkert.orgdef makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None, 2085871Snate@binkert.org dtb_filename=None, bare_metal=False, cmdline=None, 2095871Snate@binkert.org external_memory="", ruby=False, security=False, 2105871Snate@binkert.org ignore_dtb=False): 2115871Snate@binkert.org assert machine_type 2125871Snate@binkert.org 2135871Snate@binkert.org default_dtbs = { 2144678Snate@binkert.org "RealViewEB": None, 2155871Snate@binkert.org "RealViewPBX": None, 2165871Snate@binkert.org "VExpress_EMM": "vexpress.aarch32.ll_20131205.0-gem5.%dcpu.dtb" % num_cpus, 2175871Snate@binkert.org "VExpress_EMM64": "vexpress.aarch64.20140821.dtb", 2185871Snate@binkert.org } 2195871Snate@binkert.org 2205871Snate@binkert.org default_kernels = { 2215871Snate@binkert.org "RealViewEB": "vmlinux.arm.smp.fb.2.6.38.8", 2225871Snate@binkert.org "RealViewPBX": "vmlinux.arm.smp.fb.2.6.38.8", 2235871Snate@binkert.org "VExpress_EMM": "vmlinux.aarch32.ll_20131205.0-gem5", 2245871Snate@binkert.org "VExpress_EMM64": "vmlinux.aarch64.20140821", 2255871Snate@binkert.org } 2265871Snate@binkert.org 2275871Snate@binkert.org pci_devices = [] 2284678Snate@binkert.org 2295871Snate@binkert.org if bare_metal: 2304678Snate@binkert.org self = ArmSystem() 2315871Snate@binkert.org else: 2325871Snate@binkert.org self = LinuxArmSystem() 2335871Snate@binkert.org 2345871Snate@binkert.org if not mdesc: 2355871Snate@binkert.org # generic system 2365871Snate@binkert.org mdesc = SysConfig() 2375871Snate@binkert.org 2385871Snate@binkert.org self.readfile = mdesc.script() 2395871Snate@binkert.org self.iobus = IOXBar() 2405863Snate@binkert.org if not ruby: 241955SN/A self.bridge = Bridge(delay='50ns') 242955SN/A self.bridge.master = self.iobus.slave 2432632Sstever@eecs.umich.edu self.membus = MemBus() 2442632Sstever@eecs.umich.edu self.membus.badaddr_responder.warn_access = "warn" 245955SN/A self.bridge.slave = self.membus.master 246955SN/A 247955SN/A self.mem_mode = mem_mode 248955SN/A 2495863Snate@binkert.org platform_class = PlatformConfig.get(machine_type) 250955SN/A # Resolve the real platform name, the original machine_type 2512632Sstever@eecs.umich.edu # variable might have been an alias. 2522632Sstever@eecs.umich.edu machine_type = platform_class.__name__ 2532632Sstever@eecs.umich.edu self.realview = platform_class() 2542632Sstever@eecs.umich.edu 2552632Sstever@eecs.umich.edu if not dtb_filename and not (bare_metal or ignore_dtb): 2562632Sstever@eecs.umich.edu try: 2572632Sstever@eecs.umich.edu dtb_filename = default_dtbs[machine_type] 2582632Sstever@eecs.umich.edu except KeyError: 2592632Sstever@eecs.umich.edu fatal("No DTB specified and no default DTB known for '%s'" % \ 2602632Sstever@eecs.umich.edu machine_type) 2612632Sstever@eecs.umich.edu 2622632Sstever@eecs.umich.edu if isinstance(self.realview, VExpress_EMM64): 2632632Sstever@eecs.umich.edu if os.path.split(mdesc.disk())[-1] == 'linux-aarch32-ael.img': 2643718Sstever@eecs.umich.edu print("Selected 64-bit ARM architecture, updating default " 2653718Sstever@eecs.umich.edu "disk image...") 2663718Sstever@eecs.umich.edu mdesc.diskname = 'linaro-minimal-aarch64.img' 2673718Sstever@eecs.umich.edu 2683718Sstever@eecs.umich.edu 2695863Snate@binkert.org # Attach any PCI devices this platform supports 2705863Snate@binkert.org self.realview.attachPciDevices() 2713718Sstever@eecs.umich.edu 2723718Sstever@eecs.umich.edu self.cf0 = CowIdeDisk(driveID='master') 2735863Snate@binkert.org self.cf0.childImage(mdesc.disk()) 2745863Snate@binkert.org # Old platforms have a built-in IDE or CF controller. Default to 2753718Sstever@eecs.umich.edu # the IDE controller if both exist. New platforms expect the 2763718Sstever@eecs.umich.edu # storage controller to be added from the config script. 2772634Sstever@eecs.umich.edu if hasattr(self.realview, "ide"): 2782634Sstever@eecs.umich.edu self.realview.ide.disks = [self.cf0] 2795863Snate@binkert.org elif hasattr(self.realview, "cf_ctrl"): 2802638Sstever@eecs.umich.edu self.realview.cf_ctrl.disks = [self.cf0] 2812632Sstever@eecs.umich.edu else: 2822632Sstever@eecs.umich.edu self.pci_ide = IdeController(disks=[self.cf0]) 2832632Sstever@eecs.umich.edu pci_devices.append(self.pci_ide) 2842632Sstever@eecs.umich.edu 2852632Sstever@eecs.umich.edu self.mem_ranges = [] 2862632Sstever@eecs.umich.edu size_remain = long(Addr(mdesc.mem())) 2871858SN/A for region in self.realview._mem_regions: 2883716Sstever@eecs.umich.edu if size_remain > long(region[1]): 2892638Sstever@eecs.umich.edu self.mem_ranges.append(AddrRange(region[0], size=region[1])) 2902638Sstever@eecs.umich.edu size_remain = size_remain - long(region[1]) 2912638Sstever@eecs.umich.edu else: 2922638Sstever@eecs.umich.edu self.mem_ranges.append(AddrRange(region[0], size=size_remain)) 2932638Sstever@eecs.umich.edu size_remain = 0 2942638Sstever@eecs.umich.edu break 2952638Sstever@eecs.umich.edu warn("Memory size specified spans more than one region. Creating" \ 2965863Snate@binkert.org " another memory controller for that range.") 2975863Snate@binkert.org 2985863Snate@binkert.org if size_remain > 0: 299955SN/A fatal("The currently selected ARM platforms doesn't support" \ 3005341Sstever@gmail.com " the amount of DRAM you've selected. Please try" \ 3015341Sstever@gmail.com " another platform") 3025863Snate@binkert.org 3035341Sstever@gmail.com self.have_security = security 3044494Ssaidi@eecs.umich.edu 3054494Ssaidi@eecs.umich.edu if bare_metal: 3065863Snate@binkert.org # EOT character on UART will end the simulation 3071105SN/A self.realview.uart.end_on_eot = True 3082667Sstever@eecs.umich.edu else: 3092667Sstever@eecs.umich.edu if machine_type in default_kernels: 3102667Sstever@eecs.umich.edu self.kernel = binary(default_kernels[machine_type]) 3112667Sstever@eecs.umich.edu 3122667Sstever@eecs.umich.edu if dtb_filename and not ignore_dtb: 3132667Sstever@eecs.umich.edu self.dtb_filename = binary(dtb_filename) 3145341Sstever@gmail.com 3155863Snate@binkert.org self.machine_type = machine_type if machine_type in ArmMachineType.map \ 3165341Sstever@gmail.com else "DTOnly" 3175341Sstever@gmail.com 3185341Sstever@gmail.com # Ensure that writes to the UART actually go out early in the boot 3195863Snate@binkert.org if not cmdline: 3205341Sstever@gmail.com cmdline = 'earlyprintk=pl011,0x1c090000 console=ttyAMA0 ' + \ 3215341Sstever@gmail.com 'lpj=19988480 norandmaps rw loglevel=8 ' + \ 3225341Sstever@gmail.com 'mem=%(mem)s root=%(rootdev)s' 3235863Snate@binkert.org 3245341Sstever@gmail.com # When using external memory, gem5 writes the boot loader to nvmem 3255341Sstever@gmail.com # and then SST will read from it, but SST can only get to nvmem from 3265341Sstever@gmail.com # iobus, as gem5's membus is only used for initialization and 3275341Sstever@gmail.com # SST doesn't use it. Attaching nvmem to iobus solves this issue. 3285341Sstever@gmail.com # During initialization, system_port -> membus -> iobus -> nvmem. 3295341Sstever@gmail.com if external_memory: 3305341Sstever@gmail.com self.realview.setupBootLoader(self.iobus, self, binary) 3315341Sstever@gmail.com elif ruby: 3325341Sstever@gmail.com self.realview.setupBootLoader(None, self, binary) 3335341Sstever@gmail.com else: 3345863Snate@binkert.org self.realview.setupBootLoader(self.membus, self, binary) 3355341Sstever@gmail.com self.gic_cpu_addr = self.realview.gic.cpu_addr 3365863Snate@binkert.org self.flags_addr = self.realview.realview_io.pio_addr + 0x30 3375341Sstever@gmail.com 3385863Snate@binkert.org # This check is for users who have previously put 'android' in 3395863Snate@binkert.org # the disk image filename to tell the config scripts to 3405863Snate@binkert.org # prepare the kernel with android-specific boot options. That 3415397Ssaidi@eecs.umich.edu # behavior has been replaced with a more explicit option per 3425397Ssaidi@eecs.umich.edu # the error message below. The disk can have any name now and 3435341Sstever@gmail.com # doesn't need to include 'android' substring. 3445341Sstever@gmail.com if (os.path.split(mdesc.disk())[-1]).lower().count('android'): 3455341Sstever@gmail.com if 'android' not in mdesc.os_type(): 3465341Sstever@gmail.com fatal("It looks like you are trying to boot an Android " \ 3475341Sstever@gmail.com "platform. To boot Android, you must specify " \ 3485341Sstever@gmail.com "--os-type with an appropriate Android release on " \ 3495341Sstever@gmail.com "the command line.") 3505341Sstever@gmail.com 3515863Snate@binkert.org # android-specific tweaks 3525341Sstever@gmail.com if 'android' in mdesc.os_type(): 3535341Sstever@gmail.com # generic tweaks 3545863Snate@binkert.org cmdline += " init=/init" 3555341Sstever@gmail.com 3565863Snate@binkert.org # release-specific tweaks 3575863Snate@binkert.org if 'kitkat' in mdesc.os_type(): 3585341Sstever@gmail.com cmdline += " androidboot.hardware=gem5 qemu=1 qemu.gles=0 " + \ 3595863Snate@binkert.org "android.bootanim=0 " 3605863Snate@binkert.org elif 'nougat' in mdesc.os_type(): 3615341Sstever@gmail.com cmdline += " androidboot.hardware=gem5 qemu=1 qemu.gles=0 " + \ 3625863Snate@binkert.org "android.bootanim=0 " + \ 3635341Sstever@gmail.com "vmalloc=640MB " + \ 3645871Snate@binkert.org "android.early.fstab=/fstab.gem5 " + \ 3655341Sstever@gmail.com "androidboot.selinux=permissive " + \ 3665742Snate@binkert.org "video=Virtual-1:1920x1080-16" 3675742Snate@binkert.org 3685742Snate@binkert.org self.boot_osflags = fillInCmdline(mdesc, cmdline) 3695341Sstever@gmail.com 3705742Snate@binkert.org if external_memory: 3715742Snate@binkert.org # I/O traffic enters iobus 3725341Sstever@gmail.com self.external_io = ExternalMaster(port_data="external_io", 3732632Sstever@eecs.umich.edu port_type=external_memory) 3745199Sstever@gmail.com self.external_io.port = self.iobus.slave 3755871Snate@binkert.org 3765871Snate@binkert.org # Ensure iocache only receives traffic destined for (actual) memory. 3775871Snate@binkert.org self.iocache = ExternalSlave(port_data="iocache", 3785871Snate@binkert.org port_type=external_memory, 3795871Snate@binkert.org addr_ranges=self.mem_ranges) 3805871Snate@binkert.org self.iocache.port = self.iobus.master 3815871Snate@binkert.org 3823942Ssaidi@eecs.umich.edu # Let system_port get to nvmem and nothing else. 3833940Ssaidi@eecs.umich.edu self.bridge.ranges = [self.realview.nvmem.range] 3843918Ssaidi@eecs.umich.edu 3853918Ssaidi@eecs.umich.edu self.realview.attachOnChipIO(self.iobus) 3861858SN/A # Attach off-chip devices 3873918Ssaidi@eecs.umich.edu self.realview.attachIO(self.iobus) 3883918Ssaidi@eecs.umich.edu elif ruby: 3893918Ssaidi@eecs.umich.edu self._dma_ports = [ ] 3903918Ssaidi@eecs.umich.edu self.realview.attachOnChipIO(self.iobus, dma_ports=self._dma_ports) 3915571Snate@binkert.org self.realview.attachIO(self.iobus, dma_ports=self._dma_ports) 3923940Ssaidi@eecs.umich.edu else: 3933940Ssaidi@eecs.umich.edu self.realview.attachOnChipIO(self.membus, self.bridge) 3943918Ssaidi@eecs.umich.edu # Attach off-chip devices 3953918Ssaidi@eecs.umich.edu self.realview.attachIO(self.iobus) 3963918Ssaidi@eecs.umich.edu 3973918Ssaidi@eecs.umich.edu for dev_id, dev in enumerate(pci_devices): 3983918Ssaidi@eecs.umich.edu dev.pci_bus, dev.pci_dev, dev.pci_func = (0, dev_id + 1, 0) 3993918Ssaidi@eecs.umich.edu self.realview.attachPciDevice( 4005871Snate@binkert.org dev, self.iobus, 4013918Ssaidi@eecs.umich.edu dma_ports=self._dma_ports if ruby else None) 4023918Ssaidi@eecs.umich.edu 4033940Ssaidi@eecs.umich.edu self.intrctrl = IntrControl() 4043918Ssaidi@eecs.umich.edu self.terminal = Terminal() 4053918Ssaidi@eecs.umich.edu self.vncserver = VncServer() 4065397Ssaidi@eecs.umich.edu 4075397Ssaidi@eecs.umich.edu if not ruby: 4085397Ssaidi@eecs.umich.edu self.system_port = self.membus.slave 4095708Ssaidi@eecs.umich.edu 4105708Ssaidi@eecs.umich.edu if ruby: 4115708Ssaidi@eecs.umich.edu if buildEnv['PROTOCOL'] == 'MI_example' and num_cpus > 1: 4125708Ssaidi@eecs.umich.edu fatal("The MI_example protocol cannot implement Load/Store " 4135708Ssaidi@eecs.umich.edu "Exclusive operations. Multicore ARM systems configured " 4145397Ssaidi@eecs.umich.edu "with the MI_example protocol will not work properly.") 4151851SN/A warn("You are trying to use Ruby on ARM, which is not working " 4161851SN/A "properly yet.") 4171858SN/A 4185200Sstever@gmail.com return self 419955SN/A 4203053Sstever@eecs.umich.edu 4213053Sstever@eecs.umich.edudef makeLinuxMipsSystem(mem_mode, mdesc=None, cmdline=None): 4223053Sstever@eecs.umich.edu class BaseMalta(Malta): 4233053Sstever@eecs.umich.edu ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 4243053Sstever@eecs.umich.edu ide = IdeController(disks=[Parent.disk0, Parent.disk2], 4253053Sstever@eecs.umich.edu pci_func=0, pci_dev=0, pci_bus=0) 4263053Sstever@eecs.umich.edu 4275871Snate@binkert.org self = LinuxMipsSystem() 4283053Sstever@eecs.umich.edu if not mdesc: 4294742Sstever@eecs.umich.edu # generic system 4304742Sstever@eecs.umich.edu mdesc = SysConfig() 4313053Sstever@eecs.umich.edu self.readfile = mdesc.script() 4323053Sstever@eecs.umich.edu self.iobus = IOXBar() 4333053Sstever@eecs.umich.edu self.membus = MemBus() 4343053Sstever@eecs.umich.edu self.bridge = Bridge(delay='50ns') 4353053Sstever@eecs.umich.edu self.mem_ranges = [AddrRange('1GB')] 4363053Sstever@eecs.umich.edu self.bridge.master = self.iobus.slave 4373053Sstever@eecs.umich.edu self.bridge.slave = self.membus.master 4383053Sstever@eecs.umich.edu self.disk0 = CowIdeDisk(driveID='master') 4393053Sstever@eecs.umich.edu self.disk2 = CowIdeDisk(driveID='master') 4402667Sstever@eecs.umich.edu self.disk0.childImage(mdesc.disk()) 4414554Sbinkertn@umich.edu self.disk2.childImage(disk('linux-bigswap2.img')) 4424554Sbinkertn@umich.edu self.malta = BaseMalta() 4432667Sstever@eecs.umich.edu self.malta.attachIO(self.iobus) 4444554Sbinkertn@umich.edu self.malta.ide.pio = self.iobus.master 4454554Sbinkertn@umich.edu self.malta.ide.dma = self.iobus.slave 4464554Sbinkertn@umich.edu self.malta.ethernet.pio = self.iobus.master 4474554Sbinkertn@umich.edu self.malta.ethernet.dma = self.iobus.slave 4484554Sbinkertn@umich.edu self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 4494554Sbinkertn@umich.edu read_only = True)) 4504554Sbinkertn@umich.edu self.intrctrl = IntrControl() 4514781Snate@binkert.org self.mem_mode = mem_mode 4524554Sbinkertn@umich.edu self.terminal = Terminal() 4534554Sbinkertn@umich.edu self.kernel = binary('mips/vmlinux') 4542667Sstever@eecs.umich.edu self.console = binary('mips/console') 4554554Sbinkertn@umich.edu if not cmdline: 4564554Sbinkertn@umich.edu cmdline = 'root=/dev/hda1 console=ttyS0' 4574554Sbinkertn@umich.edu self.boot_osflags = fillInCmdline(mdesc, cmdline) 4584554Sbinkertn@umich.edu 4592667Sstever@eecs.umich.edu self.system_port = self.membus.slave 4604554Sbinkertn@umich.edu 4612667Sstever@eecs.umich.edu return self 4624554Sbinkertn@umich.edu 4634554Sbinkertn@umich.edudef x86IOAddress(port): 4642667Sstever@eecs.umich.edu IO_address_space_base = 0x8000000000000000 4655522Snate@binkert.org return IO_address_space_base + port 4665522Snate@binkert.org 4675522Snate@binkert.orgdef connectX86ClassicSystem(x86_sys, numCPUs): 4685522Snate@binkert.org # Constants similar to x86_traits.hh 4695522Snate@binkert.org IO_address_space_base = 0x8000000000000000 4705522Snate@binkert.org pci_config_address_space_base = 0xc000000000000000 4715522Snate@binkert.org interrupts_address_space_base = 0xa000000000000000 4725522Snate@binkert.org APIC_range_size = 1 << 12; 4735522Snate@binkert.org 4745522Snate@binkert.org x86_sys.membus = MemBus() 4755522Snate@binkert.org 4765522Snate@binkert.org # North Bridge 4775522Snate@binkert.org x86_sys.iobus = IOXBar() 4785522Snate@binkert.org x86_sys.bridge = Bridge(delay='50ns') 4795522Snate@binkert.org x86_sys.bridge.master = x86_sys.iobus.slave 4805522Snate@binkert.org x86_sys.bridge.slave = x86_sys.membus.master 4815522Snate@binkert.org # Allow the bridge to pass through: 4825522Snate@binkert.org # 1) kernel configured PCI device memory map address: address range 4835522Snate@binkert.org # [0xC0000000, 0xFFFF0000). (The upper 64kB are reserved for m5ops.) 4845522Snate@binkert.org # 2) the bridge to pass through the IO APIC (two pages, already contained in 1), 4855522Snate@binkert.org # 3) everything in the IO address range up to the local APIC, and 4865522Snate@binkert.org # 4) then the entire PCI address space and beyond. 4875522Snate@binkert.org x86_sys.bridge.ranges = \ 4885522Snate@binkert.org [ 4895522Snate@binkert.org AddrRange(0xC0000000, 0xFFFF0000), 4905522Snate@binkert.org AddrRange(IO_address_space_base, 4912638Sstever@eecs.umich.edu interrupts_address_space_base - 1), 4922638Sstever@eecs.umich.edu AddrRange(pci_config_address_space_base, 4932638Sstever@eecs.umich.edu Addr.max) 4943716Sstever@eecs.umich.edu ] 4955522Snate@binkert.org 4965522Snate@binkert.org # Create a bridge from the IO bus to the memory bus to allow access to 4975522Snate@binkert.org # the local APIC (two pages) 4985522Snate@binkert.org x86_sys.apicbridge = Bridge(delay='50ns') 4995522Snate@binkert.org x86_sys.apicbridge.slave = x86_sys.iobus.master 5005522Snate@binkert.org x86_sys.apicbridge.master = x86_sys.membus.slave 5011858SN/A x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base, 5025227Ssaidi@eecs.umich.edu interrupts_address_space_base + 5035227Ssaidi@eecs.umich.edu numCPUs * APIC_range_size 5045227Ssaidi@eecs.umich.edu - 1)] 5055227Ssaidi@eecs.umich.edu 5065227Ssaidi@eecs.umich.edu # connect the io bus 5075863Snate@binkert.org x86_sys.pc.attachIO(x86_sys.iobus) 5085227Ssaidi@eecs.umich.edu 5095227Ssaidi@eecs.umich.edu x86_sys.system_port = x86_sys.membus.slave 5105227Ssaidi@eecs.umich.edu 5115227Ssaidi@eecs.umich.edudef connectX86RubySystem(x86_sys): 5125227Ssaidi@eecs.umich.edu # North Bridge 5135227Ssaidi@eecs.umich.edu x86_sys.iobus = IOXBar() 5145227Ssaidi@eecs.umich.edu 5155204Sstever@gmail.com # add the ide to the list of dma devices that later need to attach to 5165204Sstever@gmail.com # dma controllers 5175204Sstever@gmail.com x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma] 5185204Sstever@gmail.com x86_sys.pc.attachIO(x86_sys.iobus, x86_sys._dma_ports) 5195204Sstever@gmail.com 5205204Sstever@gmail.com 5215204Sstever@gmail.comdef makeX86System(mem_mode, numCPUs=1, mdesc=None, self=None, Ruby=False): 5225204Sstever@gmail.com if self == None: 5235204Sstever@gmail.com self = X86System() 5245204Sstever@gmail.com 5255204Sstever@gmail.com if not mdesc: 5265204Sstever@gmail.com # generic system 5275204Sstever@gmail.com mdesc = SysConfig() 5285204Sstever@gmail.com self.readfile = mdesc.script() 5295204Sstever@gmail.com 5305204Sstever@gmail.com self.mem_mode = mem_mode 5315204Sstever@gmail.com 5325204Sstever@gmail.com # Physical memory 5335204Sstever@gmail.com # On the PC platform, the memory region 0xC0000000-0xFFFFFFFF is reserved 5343118Sstever@eecs.umich.edu # for various devices. Hence, if the physical memory size is greater than 5353118Sstever@eecs.umich.edu # 3GB, we need to split it into two parts. 5363118Sstever@eecs.umich.edu excess_mem_size = \ 5373118Sstever@eecs.umich.edu convert.toMemorySize(mdesc.mem()) - convert.toMemorySize('3GB') 5383118Sstever@eecs.umich.edu if excess_mem_size <= 0: 5395863Snate@binkert.org self.mem_ranges = [AddrRange(mdesc.mem())] 5403118Sstever@eecs.umich.edu else: 5415863Snate@binkert.org warn("Physical memory size specified is %s which is greater than " \ 5423118Sstever@eecs.umich.edu "3GB. Twice the number of memory controllers would be " \ 5435863Snate@binkert.org "created." % (mdesc.mem())) 5445863Snate@binkert.org 5455863Snate@binkert.org self.mem_ranges = [AddrRange('3GB'), 5465863Snate@binkert.org AddrRange(Addr('4GB'), size = excess_mem_size)] 5475863Snate@binkert.org 5485863Snate@binkert.org # Platform 5495863Snate@binkert.org self.pc = Pc() 5505863Snate@binkert.org 5515863Snate@binkert.org # Create and connect the busses required by each memory system 5525863Snate@binkert.org if Ruby: 5535863Snate@binkert.org connectX86RubySystem(self) 5545863Snate@binkert.org else: 5555863Snate@binkert.org connectX86ClassicSystem(self, numCPUs) 5565863Snate@binkert.org 5575863Snate@binkert.org self.intrctrl = IntrControl() 5585863Snate@binkert.org 5595863Snate@binkert.org # Disks 5605863Snate@binkert.org disk0 = CowIdeDisk(driveID='master') 5615863Snate@binkert.org disk2 = CowIdeDisk(driveID='master') 5625863Snate@binkert.org disk0.childImage(mdesc.disk()) 5635863Snate@binkert.org disk2.childImage(disk('linux-bigswap2.img')) 5645863Snate@binkert.org self.pc.south_bridge.ide.disks = [disk0, disk2] 5655863Snate@binkert.org 5665863Snate@binkert.org # Add in a Bios information structure. 5675863Snate@binkert.org structures = [X86SMBiosBiosInformation()] 5683118Sstever@eecs.umich.edu self.smbios_table.structures = structures 5695863Snate@binkert.org 5703118Sstever@eecs.umich.edu # Set up the Intel MP table 5713118Sstever@eecs.umich.edu base_entries = [] 5725863Snate@binkert.org ext_entries = [] 5735863Snate@binkert.org for i in xrange(numCPUs): 5745863Snate@binkert.org bp = X86IntelMPProcessor( 5755863Snate@binkert.org local_apic_id = i, 5765863Snate@binkert.org local_apic_version = 0x14, 5775863Snate@binkert.org enable = True, 5783118Sstever@eecs.umich.edu bootstrap = (i == 0)) 5793483Ssaidi@eecs.umich.edu base_entries.append(bp) 5803494Ssaidi@eecs.umich.edu io_apic = X86IntelMPIOAPIC( 5813494Ssaidi@eecs.umich.edu id = numCPUs, 5823483Ssaidi@eecs.umich.edu version = 0x11, 5833483Ssaidi@eecs.umich.edu enable = True, 5843483Ssaidi@eecs.umich.edu address = 0xfec00000) 5853053Sstever@eecs.umich.edu self.pc.south_bridge.io_apic.apic_id = io_apic.id 5863053Sstever@eecs.umich.edu base_entries.append(io_apic) 5873918Ssaidi@eecs.umich.edu # In gem5 Pc::calcPciConfigAddr(), it required "assert(bus==0)", 5883053Sstever@eecs.umich.edu # but linux kernel cannot config PCI device if it was not connected to PCI bus, 5893053Sstever@eecs.umich.edu # so we fix PCI bus id to 0, and ISA bus id to 1. 5903053Sstever@eecs.umich.edu pci_bus = X86IntelMPBus(bus_id = 0, bus_type='PCI ') 5913053Sstever@eecs.umich.edu base_entries.append(pci_bus) 5923053Sstever@eecs.umich.edu isa_bus = X86IntelMPBus(bus_id = 1, bus_type='ISA ') 5931858SN/A base_entries.append(isa_bus) 5941858SN/A connect_busses = X86IntelMPBusHierarchy(bus_id=1, 5951858SN/A subtractive_decode=True, parent_bus=0) 5961858SN/A ext_entries.append(connect_busses) 5971858SN/A pci_dev4_inta = X86IntelMPIOIntAssignment( 5981858SN/A interrupt_type = 'INT', 5995863Snate@binkert.org polarity = 'ConformPolarity', 6005863Snate@binkert.org trigger = 'ConformTrigger', 6011859SN/A source_bus_id = 0, 6025863Snate@binkert.org source_bus_irq = 0 + (4 << 2), 6031858SN/A dest_io_apic_id = io_apic.id, 6045863Snate@binkert.org dest_io_apic_intin = 16) 6051858SN/A base_entries.append(pci_dev4_inta) 6061859SN/A def assignISAInt(irq, apicPin): 6071859SN/A assign_8259_to_apic = X86IntelMPIOIntAssignment( 6085863Snate@binkert.org interrupt_type = 'ExtInt', 6093053Sstever@eecs.umich.edu polarity = 'ConformPolarity', 6103053Sstever@eecs.umich.edu trigger = 'ConformTrigger', 6113053Sstever@eecs.umich.edu source_bus_id = 1, 6123053Sstever@eecs.umich.edu source_bus_irq = irq, 6131859SN/A dest_io_apic_id = io_apic.id, 6141859SN/A dest_io_apic_intin = 0) 6151859SN/A base_entries.append(assign_8259_to_apic) 6161859SN/A assign_to_apic = X86IntelMPIOIntAssignment( 6171859SN/A interrupt_type = 'INT', 6181859SN/A polarity = 'ConformPolarity', 6191859SN/A trigger = 'ConformTrigger', 6201859SN/A source_bus_id = 1, 6211862SN/A source_bus_irq = irq, 6221859SN/A dest_io_apic_id = io_apic.id, 6231859SN/A dest_io_apic_intin = apicPin) 6241859SN/A base_entries.append(assign_to_apic) 6255863Snate@binkert.org assignISAInt(0, 2) 6265863Snate@binkert.org assignISAInt(1, 1) 6275863Snate@binkert.org for i in range(3, 15): 6285863Snate@binkert.org assignISAInt(i, i) 6291858SN/A self.intel_mp_table.base_entries = base_entries 6301858SN/A self.intel_mp_table.ext_entries = ext_entries 6315863Snate@binkert.org 6325863Snate@binkert.orgdef makeLinuxX86System(mem_mode, numCPUs=1, mdesc=None, Ruby=False, 6335863Snate@binkert.org cmdline=None): 6345863Snate@binkert.org self = LinuxX86System() 6355863Snate@binkert.org 6365871Snate@binkert.org # Build up the x86 system and then specialize it for Linux 6375871Snate@binkert.org makeX86System(mem_mode, numCPUs, mdesc, self, Ruby) 6382139SN/A 6394202Sbinkertn@umich.edu # We assume below that there's at least 1MB of memory. We'll require 2 6404202Sbinkertn@umich.edu # just to avoid corner cases. 6412139SN/A phys_mem_size = sum(map(lambda r: r.size(), self.mem_ranges)) 6422155SN/A assert(phys_mem_size >= 0x200000) 6434202Sbinkertn@umich.edu assert(len(self.mem_ranges) <= 2) 6444202Sbinkertn@umich.edu 6454202Sbinkertn@umich.edu entries = \ 6462155SN/A [ 6475863Snate@binkert.org # Mark the first megabyte of memory as reserved 6481869SN/A X86E820Entry(addr = 0, size = '639kB', range_type = 1), 6491869SN/A X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2), 6505863Snate@binkert.org # Mark the rest of physical memory as available 6515863Snate@binkert.org X86E820Entry(addr = 0x100000, 6524202Sbinkertn@umich.edu size = '%dB' % (self.mem_ranges[0].size() - 0x100000), 6535863Snate@binkert.org range_type = 1), 6545863Snate@binkert.org ] 6555863Snate@binkert.org 6564202Sbinkertn@umich.edu # Mark [mem_size, 3GB) as reserved if memory less than 3GB, which force 6574202Sbinkertn@umich.edu # IO devices to be mapped to [0xC0000000, 0xFFFF0000). Requests to this 6585863Snate@binkert.org # specific range can pass though bridge to iobus. 6595742Snate@binkert.org if len(self.mem_ranges) == 1: 6605742Snate@binkert.org entries.append(X86E820Entry(addr = self.mem_ranges[0].size(), 6615341Sstever@gmail.com size='%dB' % (0xC0000000 - self.mem_ranges[0].size()), 6625342Sstever@gmail.com range_type=2)) 6635342Sstever@gmail.com 6644202Sbinkertn@umich.edu # Reserve the last 16kB of the 32-bit address space for the m5op interface 6654202Sbinkertn@umich.edu entries.append(X86E820Entry(addr=0xFFFF0000, size='64kB', range_type=2)) 6664202Sbinkertn@umich.edu 6674202Sbinkertn@umich.edu # In case the physical memory is greater than 3GB, we split it into two 6684202Sbinkertn@umich.edu # parts and add a separate e820 entry for the second part. This entry 6695863Snate@binkert.org # starts at 0x100000000, which is the first address after the space 6705863Snate@binkert.org # reserved for devices. 6715863Snate@binkert.org if len(self.mem_ranges) == 2: 6725863Snate@binkert.org entries.append(X86E820Entry(addr = 0x100000000, 6735863Snate@binkert.org size = '%dB' % (self.mem_ranges[1].size()), range_type = 1)) 6745863Snate@binkert.org 6755863Snate@binkert.org self.e820_table.entries = entries 6765863Snate@binkert.org 6775863Snate@binkert.org # Command line 6785863Snate@binkert.org if not cmdline: 6795863Snate@binkert.org cmdline = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1' 6805863Snate@binkert.org self.boot_osflags = fillInCmdline(mdesc, cmdline) 6815863Snate@binkert.org self.kernel = binary('x86_64-vmlinux-2.6.22.9') 6825863Snate@binkert.org return self 6835863Snate@binkert.org 6845863Snate@binkert.org 6855863Snate@binkert.orgdef makeDualRoot(full_system, testSystem, driveSystem, dumpfile): 6865863Snate@binkert.org self = Root(full_system = full_system) 6875863Snate@binkert.org self.testsys = testSystem 6885863Snate@binkert.org self.drivesys = driveSystem 6891869SN/A self.etherlink = EtherLink() 6901858SN/A 6915863Snate@binkert.org if hasattr(testSystem, 'realview'): 6925863Snate@binkert.org self.etherlink.int0 = Parent.testsys.realview.ethernet.interface 6931869SN/A self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface 6941858SN/A elif hasattr(testSystem, 'tsunami'): 6955863Snate@binkert.org self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 6965863Snate@binkert.org self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 6975863Snate@binkert.org else: 6985863Snate@binkert.org fatal("Don't know how to connect these system together") 6995863Snate@binkert.org 7001858SN/A if dumpfile: 701955SN/A self.etherdump = EtherDump(file=dumpfile) 702955SN/A self.etherlink.dump = Parent.etherdump 7031869SN/A 7041869SN/A return self 7051869SN/A 7061869SN/A 7071869SN/Adef makeDistRoot(testSystem, 7085863Snate@binkert.org rank, 7095863Snate@binkert.org size, 7105863Snate@binkert.org server_name, 7111869SN/A server_port, 7125863Snate@binkert.org sync_repeat, 7131869SN/A sync_start, 7145863Snate@binkert.org linkspeed, 7151869SN/A linkdelay, 7161869SN/A dumpfile): 7171869SN/A self = Root(full_system = True) 7181869SN/A self.testsys = testSystem 7191869SN/A 7205863Snate@binkert.org self.etherlink = DistEtherLink(speed = linkspeed, 7215863Snate@binkert.org delay = linkdelay, 7221869SN/A dist_rank = rank, 7231869SN/A dist_size = size, 7241869SN/A server_name = server_name, 7251869SN/A server_port = server_port, 7261869SN/A sync_start = sync_start, 7271869SN/A sync_repeat = sync_repeat) 7281869SN/A 7295863Snate@binkert.org if hasattr(testSystem, 'realview'): 7305863Snate@binkert.org self.etherlink.int0 = Parent.testsys.realview.ethernet.interface 7311869SN/A elif hasattr(testSystem, 'tsunami'): 7325863Snate@binkert.org self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 7335863Snate@binkert.org else: 7343356Sbinkertn@umich.edu fatal("Don't know how to connect DistEtherLink to this system") 7353356Sbinkertn@umich.edu 7363356Sbinkertn@umich.edu if dumpfile: 7373356Sbinkertn@umich.edu self.etherdump = EtherDump(file=dumpfile) 7383356Sbinkertn@umich.edu self.etherlink.dump = Parent.etherdump 7394781Snate@binkert.org 7405863Snate@binkert.org return self 7415863Snate@binkert.org