FSConfig.py revision 12564
1955SN/A# Copyright (c) 2010-2012, 2015-2017 ARM Limited 2955SN/A# All rights reserved. 37816Ssteve.reinhardt@amd.com# 45871Snate@binkert.org# The license below extends only to copyright in the software and shall 51762SN/A# not be construed as granting a license to any other intellectual 6955SN/A# property including but not limited to intellectual property relating 7955SN/A# to a hardware implementation of the functionality of the software 8955SN/A# licensed hereunder. You may use the software subject to the license 9955SN/A# terms below provided that you ensure that this notice is replicated 10955SN/A# unmodified and in its entirety in all distributions of the software, 11955SN/A# modified or unmodified, in source code or in binary form. 12955SN/A# 13955SN/A# Copyright (c) 2010-2011 Advanced Micro Devices, Inc. 14955SN/A# Copyright (c) 2006-2008 The Regents of The University of Michigan 15955SN/A# All rights reserved. 16955SN/A# 17955SN/A# Redistribution and use in source and binary forms, with or without 18955SN/A# modification, are permitted provided that the following conditions are 19955SN/A# met: redistributions of source code must retain the above copyright 20955SN/A# notice, this list of conditions and the following disclaimer; 21955SN/A# redistributions in binary form must reproduce the above copyright 22955SN/A# notice, this list of conditions and the following disclaimer in the 23955SN/A# documentation and/or other materials provided with the distribution; 24955SN/A# neither the name of the copyright holders nor the names of its 25955SN/A# contributors may be used to endorse or promote products derived from 26955SN/A# this software without specific prior written permission. 27955SN/A# 28955SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29955SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302665Ssaidi@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312665Ssaidi@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 325863Snate@binkert.org# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33955SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34955SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35955SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36955SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37955SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 388878Ssteve.reinhardt@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392632Sstever@eecs.umich.edu# 408878Ssteve.reinhardt@amd.com# Authors: Kevin Lim 412632Sstever@eecs.umich.edu 42955SN/Afrom __future__ import print_function 438878Ssteve.reinhardt@amd.com 442632Sstever@eecs.umich.edufrom m5.objects import * 452761Sstever@eecs.umich.edufrom Benchmarks import * 462632Sstever@eecs.umich.edufrom m5.util import * 472632Sstever@eecs.umich.edufrom common import PlatformConfig 482632Sstever@eecs.umich.edu 492761Sstever@eecs.umich.edu# Populate to reflect supported os types per target ISA 502761Sstever@eecs.umich.eduos_types = { 'alpha' : [ 'linux' ], 512761Sstever@eecs.umich.edu 'mips' : [ 'linux' ], 528878Ssteve.reinhardt@amd.com 'sparc' : [ 'linux' ], 538878Ssteve.reinhardt@amd.com 'x86' : [ 'linux' ], 542761Sstever@eecs.umich.edu 'arm' : [ 'linux', 552761Sstever@eecs.umich.edu 'android-gingerbread', 562761Sstever@eecs.umich.edu 'android-ics', 572761Sstever@eecs.umich.edu 'android-jellybean', 582761Sstever@eecs.umich.edu 'android-kitkat', 598878Ssteve.reinhardt@amd.com 'android-nougat', ], 608878Ssteve.reinhardt@amd.com } 612632Sstever@eecs.umich.edu 622632Sstever@eecs.umich.educlass CowIdeDisk(IdeDisk): 638878Ssteve.reinhardt@amd.com image = CowDiskImage(child=RawDiskImage(read_only=True), 648878Ssteve.reinhardt@amd.com read_only=False) 652632Sstever@eecs.umich.edu 66955SN/A def childImage(self, ci): 67955SN/A self.image.child.image_file = ci 68955SN/A 695863Snate@binkert.orgclass MemBus(SystemXBar): 705863Snate@binkert.org badaddr_responder = BadAddr() 715863Snate@binkert.org default = Self.badaddr_responder.pio 725863Snate@binkert.org 735863Snate@binkert.orgdef fillInCmdline(mdesc, template, **kwargs): 745863Snate@binkert.org kwargs.setdefault('disk', mdesc.disk()) 755863Snate@binkert.org kwargs.setdefault('rootdev', mdesc.rootdev()) 765863Snate@binkert.org kwargs.setdefault('mem', mdesc.mem()) 775863Snate@binkert.org kwargs.setdefault('script', mdesc.script()) 785863Snate@binkert.org return template % kwargs 795863Snate@binkert.org 808878Ssteve.reinhardt@amd.comdef makeLinuxAlphaSystem(mem_mode, mdesc=None, ruby=False, cmdline=None): 815863Snate@binkert.org 825863Snate@binkert.org class BaseTsunami(Tsunami): 835863Snate@binkert.org ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 845863Snate@binkert.org ide = IdeController(disks=[Parent.disk0, Parent.disk2], 855863Snate@binkert.org pci_func=0, pci_dev=0, pci_bus=0) 865863Snate@binkert.org 875863Snate@binkert.org self = LinuxAlphaSystem() 885863Snate@binkert.org if not mdesc: 895863Snate@binkert.org # generic system 905863Snate@binkert.org mdesc = SysConfig() 915863Snate@binkert.org self.readfile = mdesc.script() 925863Snate@binkert.org 935863Snate@binkert.org self.tsunami = BaseTsunami() 945863Snate@binkert.org 955863Snate@binkert.org # Create the io bus to connect all device ports 968878Ssteve.reinhardt@amd.com self.iobus = IOXBar() 975863Snate@binkert.org self.tsunami.attachIO(self.iobus) 985863Snate@binkert.org 995863Snate@binkert.org self.tsunami.ide.pio = self.iobus.master 1006654Snate@binkert.org 101955SN/A self.tsunami.ethernet.pio = self.iobus.master 1025396Ssaidi@eecs.umich.edu 1035863Snate@binkert.org if ruby: 1045863Snate@binkert.org # Store the dma devices for later connection to dma ruby ports. 1054202Sbinkertn@umich.edu # Append an underscore to dma_ports to avoid the SimObjectVector check. 1065863Snate@binkert.org self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma] 1075863Snate@binkert.org else: 1085863Snate@binkert.org self.membus = MemBus() 1095863Snate@binkert.org 110955SN/A # By default the bridge responds to all addresses above the I/O 1116654Snate@binkert.org # base address (including the PCI config space) 1125273Sstever@gmail.com IO_address_space_base = 0x80000000000 1135871Snate@binkert.org self.bridge = Bridge(delay='50ns', 1145273Sstever@gmail.com ranges = [AddrRange(IO_address_space_base, Addr.max)]) 1156655Snate@binkert.org self.bridge.master = self.iobus.slave 1168878Ssteve.reinhardt@amd.com self.bridge.slave = self.membus.master 1176655Snate@binkert.org 1186655Snate@binkert.org self.tsunami.ide.dma = self.iobus.slave 1196655Snate@binkert.org self.tsunami.ethernet.dma = self.iobus.slave 1206655Snate@binkert.org 1215871Snate@binkert.org self.system_port = self.membus.slave 1226654Snate@binkert.org 1238947Sandreas.hansson@arm.com self.mem_ranges = [AddrRange(mdesc.mem())] 1245396Ssaidi@eecs.umich.edu self.disk0 = CowIdeDisk(driveID='master') 1258120Sgblack@eecs.umich.edu self.disk2 = CowIdeDisk(driveID='master') 1268120Sgblack@eecs.umich.edu self.disk0.childImage(mdesc.disk()) 1278120Sgblack@eecs.umich.edu self.disk2.childImage(disk('linux-bigswap2.img')) 1288120Sgblack@eecs.umich.edu self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 1298120Sgblack@eecs.umich.edu read_only = True)) 1308120Sgblack@eecs.umich.edu self.intrctrl = IntrControl() 1318120Sgblack@eecs.umich.edu self.mem_mode = mem_mode 1328120Sgblack@eecs.umich.edu self.terminal = Terminal() 1338879Ssteve.reinhardt@amd.com self.kernel = binary('vmlinux') 1348879Ssteve.reinhardt@amd.com self.pal = binary('ts_osfpal') 1358879Ssteve.reinhardt@amd.com self.console = binary('console') 1368879Ssteve.reinhardt@amd.com if not cmdline: 1378879Ssteve.reinhardt@amd.com cmdline = 'root=/dev/hda1 console=ttyS0' 1388879Ssteve.reinhardt@amd.com self.boot_osflags = fillInCmdline(mdesc, cmdline) 1398879Ssteve.reinhardt@amd.com 1408879Ssteve.reinhardt@amd.com return self 1418879Ssteve.reinhardt@amd.com 1428879Ssteve.reinhardt@amd.comdef makeSparcSystem(mem_mode, mdesc=None, cmdline=None): 1438879Ssteve.reinhardt@amd.com # Constants from iob.cc and uart8250.cc 1448879Ssteve.reinhardt@amd.com iob_man_addr = 0x9800000000 1458879Ssteve.reinhardt@amd.com uart_pio_size = 8 1468120Sgblack@eecs.umich.edu 1478120Sgblack@eecs.umich.edu class CowMmDisk(MmDisk): 1488120Sgblack@eecs.umich.edu image = CowDiskImage(child=RawDiskImage(read_only=True), 1498120Sgblack@eecs.umich.edu read_only=False) 1508120Sgblack@eecs.umich.edu 1518120Sgblack@eecs.umich.edu def childImage(self, ci): 1528120Sgblack@eecs.umich.edu self.image.child.image_file = ci 1538120Sgblack@eecs.umich.edu 1548120Sgblack@eecs.umich.edu self = SparcSystem() 1558120Sgblack@eecs.umich.edu if not mdesc: 1568120Sgblack@eecs.umich.edu # generic system 1578120Sgblack@eecs.umich.edu mdesc = SysConfig() 1588120Sgblack@eecs.umich.edu self.readfile = mdesc.script() 1598120Sgblack@eecs.umich.edu self.iobus = IOXBar() 1608879Ssteve.reinhardt@amd.com self.membus = MemBus() 1618879Ssteve.reinhardt@amd.com self.bridge = Bridge(delay='50ns') 1628879Ssteve.reinhardt@amd.com self.t1000 = T1000() 1638879Ssteve.reinhardt@amd.com self.t1000.attachOnChipIO(self.membus) 1648879Ssteve.reinhardt@amd.com self.t1000.attachIO(self.iobus) 1658879Ssteve.reinhardt@amd.com self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'), 1668879Ssteve.reinhardt@amd.com AddrRange(Addr('2GB'), size ='256MB')] 1678879Ssteve.reinhardt@amd.com self.bridge.master = self.iobus.slave 1688879Ssteve.reinhardt@amd.com self.bridge.slave = self.membus.master 1698879Ssteve.reinhardt@amd.com self.rom.port = self.membus.master 1708879Ssteve.reinhardt@amd.com self.nvram.port = self.membus.master 1718879Ssteve.reinhardt@amd.com self.hypervisor_desc.port = self.membus.master 1728120Sgblack@eecs.umich.edu self.partition_desc.port = self.membus.master 1738947Sandreas.hansson@arm.com self.intrctrl = IntrControl() 1747816Ssteve.reinhardt@amd.com self.disk0 = CowMmDisk() 1755871Snate@binkert.org self.disk0.childImage(mdesc.disk()) 1765871Snate@binkert.org self.disk0.pio = self.iobus.master 1776121Snate@binkert.org 1785871Snate@binkert.org # The puart0 and hvuart are placed on the IO bus, so create ranges 1795871Snate@binkert.org # for them. The remaining IO range is rather fragmented, so poke 1806003Snate@binkert.org # holes for the iob and partition descriptors etc. 1818980Ssteve.reinhardt@amd.com self.bridge.ranges = \ 182955SN/A [ 1835871Snate@binkert.org AddrRange(self.t1000.puart0.pio_addr, 1845871Snate@binkert.org self.t1000.puart0.pio_addr + uart_pio_size - 1), 1855871Snate@binkert.org AddrRange(self.disk0.pio_addr, 1865871Snate@binkert.org self.t1000.fake_jbi.pio_addr + 187955SN/A self.t1000.fake_jbi.pio_size - 1), 1886121Snate@binkert.org AddrRange(self.t1000.fake_clk.pio_addr, 1898881Smarc.orr@gmail.com iob_man_addr - 1), 1906121Snate@binkert.org AddrRange(self.t1000.fake_l2_1.pio_addr, 1916121Snate@binkert.org self.t1000.fake_ssi.pio_addr + 1921533SN/A self.t1000.fake_ssi.pio_size - 1), 1936655Snate@binkert.org AddrRange(self.t1000.hvuart.pio_addr, 1946655Snate@binkert.org self.t1000.hvuart.pio_addr + uart_pio_size - 1) 1956655Snate@binkert.org ] 1966655Snate@binkert.org self.reset_bin = binary('reset_new.bin') 1975871Snate@binkert.org self.hypervisor_bin = binary('q_new.bin') 1985871Snate@binkert.org self.openboot_bin = binary('openboot_new.bin') 1995863Snate@binkert.org self.nvram_bin = binary('nvram1') 2005871Snate@binkert.org self.hypervisor_desc_bin = binary('1up-hv.bin') 2018878Ssteve.reinhardt@amd.com self.partition_desc_bin = binary('1up-md.bin') 2025871Snate@binkert.org 2035871Snate@binkert.org self.system_port = self.membus.slave 2045871Snate@binkert.org 2055863Snate@binkert.org return self 2066121Snate@binkert.org 2075863Snate@binkert.orgdef makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None, 2085871Snate@binkert.org dtb_filename=None, bare_metal=False, cmdline=None, 2098336Ssteve.reinhardt@amd.com external_memory="", ruby=False, security=False, 2108336Ssteve.reinhardt@amd.com ignore_dtb=False): 2118336Ssteve.reinhardt@amd.com assert machine_type 2128336Ssteve.reinhardt@amd.com 2134678Snate@binkert.org default_dtbs = { 2148336Ssteve.reinhardt@amd.com "RealViewEB": None, 2158336Ssteve.reinhardt@amd.com "RealViewPBX": None, 2168336Ssteve.reinhardt@amd.com "VExpress_EMM": "vexpress.aarch32.ll_20131205.0-gem5.%dcpu.dtb" % num_cpus, 2174678Snate@binkert.org "VExpress_EMM64": "vexpress.aarch64.20140821.dtb", 2184678Snate@binkert.org } 2194678Snate@binkert.org 2204678Snate@binkert.org default_kernels = { 2217827Snate@binkert.org "RealViewEB": "vmlinux.arm.smp.fb.2.6.38.8", 2227827Snate@binkert.org "RealViewPBX": "vmlinux.arm.smp.fb.2.6.38.8", 2238336Ssteve.reinhardt@amd.com "VExpress_EMM": "vmlinux.aarch32.ll_20131205.0-gem5", 2244678Snate@binkert.org "VExpress_EMM64": "vmlinux.aarch64.20140821", 2258336Ssteve.reinhardt@amd.com } 2268336Ssteve.reinhardt@amd.com 2278336Ssteve.reinhardt@amd.com pci_devices = [] 2288336Ssteve.reinhardt@amd.com 2298336Ssteve.reinhardt@amd.com if bare_metal: 2308336Ssteve.reinhardt@amd.com self = ArmSystem() 2315871Snate@binkert.org else: 2325871Snate@binkert.org self = LinuxArmSystem() 2338336Ssteve.reinhardt@amd.com 2348336Ssteve.reinhardt@amd.com if not mdesc: 2358336Ssteve.reinhardt@amd.com # generic system 2368336Ssteve.reinhardt@amd.com mdesc = SysConfig() 2378336Ssteve.reinhardt@amd.com 2385871Snate@binkert.org self.readfile = mdesc.script() 2398336Ssteve.reinhardt@amd.com self.iobus = IOXBar() 2408336Ssteve.reinhardt@amd.com if not ruby: 2418336Ssteve.reinhardt@amd.com self.bridge = Bridge(delay='50ns') 2428336Ssteve.reinhardt@amd.com self.bridge.master = self.iobus.slave 2438336Ssteve.reinhardt@amd.com self.membus = MemBus() 2444678Snate@binkert.org self.membus.badaddr_responder.warn_access = "warn" 2455871Snate@binkert.org self.bridge.slave = self.membus.master 2464678Snate@binkert.org 2478336Ssteve.reinhardt@amd.com self.mem_mode = mem_mode 2488336Ssteve.reinhardt@amd.com 2498336Ssteve.reinhardt@amd.com platform_class = PlatformConfig.get(machine_type) 2508336Ssteve.reinhardt@amd.com # Resolve the real platform name, the original machine_type 2518336Ssteve.reinhardt@amd.com # variable might have been an alias. 2528336Ssteve.reinhardt@amd.com machine_type = platform_class.__name__ 2538336Ssteve.reinhardt@amd.com self.realview = platform_class() 2548336Ssteve.reinhardt@amd.com 2558336Ssteve.reinhardt@amd.com if not dtb_filename and not (bare_metal or ignore_dtb): 2568336Ssteve.reinhardt@amd.com try: 2578336Ssteve.reinhardt@amd.com dtb_filename = default_dtbs[machine_type] 2588336Ssteve.reinhardt@amd.com except KeyError: 2598336Ssteve.reinhardt@amd.com fatal("No DTB specified and no default DTB known for '%s'" % \ 2608336Ssteve.reinhardt@amd.com machine_type) 2618336Ssteve.reinhardt@amd.com 2628336Ssteve.reinhardt@amd.com if isinstance(self.realview, VExpress_EMM64): 2638336Ssteve.reinhardt@amd.com if os.path.split(mdesc.disk())[-1] == 'linux-aarch32-ael.img': 2645871Snate@binkert.org print("Selected 64-bit ARM architecture, updating default " 2656121Snate@binkert.org "disk image...") 266955SN/A mdesc.diskname = 'linaro-minimal-aarch64.img' 267955SN/A 2682632Sstever@eecs.umich.edu 2692632Sstever@eecs.umich.edu # Attach any PCI devices this platform supports 270955SN/A self.realview.attachPciDevices() 271955SN/A 272955SN/A self.cf0 = CowIdeDisk(driveID='master') 273955SN/A self.cf0.childImage(mdesc.disk()) 2748878Ssteve.reinhardt@amd.com # Old platforms have a built-in IDE or CF controller. Default to 275955SN/A # the IDE controller if both exist. New platforms expect the 2762632Sstever@eecs.umich.edu # storage controller to be added from the config script. 2772632Sstever@eecs.umich.edu if hasattr(self.realview, "ide"): 2782632Sstever@eecs.umich.edu self.realview.ide.disks = [self.cf0] 2792632Sstever@eecs.umich.edu elif hasattr(self.realview, "cf_ctrl"): 2802632Sstever@eecs.umich.edu self.realview.cf_ctrl.disks = [self.cf0] 2812632Sstever@eecs.umich.edu else: 2822632Sstever@eecs.umich.edu self.pci_ide = IdeController(disks=[self.cf0]) 2838268Ssteve.reinhardt@amd.com pci_devices.append(self.pci_ide) 2848268Ssteve.reinhardt@amd.com 2858268Ssteve.reinhardt@amd.com self.mem_ranges = [] 2868268Ssteve.reinhardt@amd.com size_remain = long(Addr(mdesc.mem())) 2878268Ssteve.reinhardt@amd.com for region in self.realview._mem_regions: 2888268Ssteve.reinhardt@amd.com if size_remain > long(region[1]): 2898268Ssteve.reinhardt@amd.com self.mem_ranges.append(AddrRange(region[0], size=region[1])) 2902632Sstever@eecs.umich.edu size_remain = size_remain - long(region[1]) 2912632Sstever@eecs.umich.edu else: 2922632Sstever@eecs.umich.edu self.mem_ranges.append(AddrRange(region[0], size=size_remain)) 2932632Sstever@eecs.umich.edu size_remain = 0 2948268Ssteve.reinhardt@amd.com break 2952632Sstever@eecs.umich.edu warn("Memory size specified spans more than one region. Creating" \ 2968268Ssteve.reinhardt@amd.com " another memory controller for that range.") 2978268Ssteve.reinhardt@amd.com 2988268Ssteve.reinhardt@amd.com if size_remain > 0: 2998268Ssteve.reinhardt@amd.com fatal("The currently selected ARM platforms doesn't support" \ 3003718Sstever@eecs.umich.edu " the amount of DRAM you've selected. Please try" \ 3012634Sstever@eecs.umich.edu " another platform") 3022634Sstever@eecs.umich.edu 3035863Snate@binkert.org self.have_security = security 3042638Sstever@eecs.umich.edu 3058268Ssteve.reinhardt@amd.com if bare_metal: 3062632Sstever@eecs.umich.edu # EOT character on UART will end the simulation 3072632Sstever@eecs.umich.edu self.realview.uart.end_on_eot = True 3082632Sstever@eecs.umich.edu else: 3092632Sstever@eecs.umich.edu if machine_type in default_kernels: 3102632Sstever@eecs.umich.edu self.kernel = binary(default_kernels[machine_type]) 3111858SN/A 3123716Sstever@eecs.umich.edu if dtb_filename and not ignore_dtb: 3132638Sstever@eecs.umich.edu self.dtb_filename = binary(dtb_filename) 3142638Sstever@eecs.umich.edu 3152638Sstever@eecs.umich.edu self.machine_type = machine_type if machine_type in ArmMachineType.map \ 3162638Sstever@eecs.umich.edu else "DTOnly" 3172638Sstever@eecs.umich.edu 3182638Sstever@eecs.umich.edu # Ensure that writes to the UART actually go out early in the boot 3192638Sstever@eecs.umich.edu if not cmdline: 3205863Snate@binkert.org cmdline = 'earlyprintk=pl011,0x1c090000 console=ttyAMA0 ' + \ 3215863Snate@binkert.org 'lpj=19988480 norandmaps rw loglevel=8 ' + \ 3225863Snate@binkert.org 'mem=%(mem)s root=%(rootdev)s' 323955SN/A 3245341Sstever@gmail.com # When using external memory, gem5 writes the boot loader to nvmem 3255341Sstever@gmail.com # and then SST will read from it, but SST can only get to nvmem from 3265863Snate@binkert.org # iobus, as gem5's membus is only used for initialization and 3277756SAli.Saidi@ARM.com # SST doesn't use it. Attaching nvmem to iobus solves this issue. 3285341Sstever@gmail.com # During initialization, system_port -> membus -> iobus -> nvmem. 3296121Snate@binkert.org if external_memory or ruby: 3304494Ssaidi@eecs.umich.edu self.realview.setupBootLoader(self.iobus, self, binary) 3316121Snate@binkert.org else: 3321105SN/A self.realview.setupBootLoader(self.membus, self, binary) 3332667Sstever@eecs.umich.edu self.gic_cpu_addr = self.realview.gic.cpu_addr 3342667Sstever@eecs.umich.edu self.flags_addr = self.realview.realview_io.pio_addr + 0x30 3352667Sstever@eecs.umich.edu 3362667Sstever@eecs.umich.edu # This check is for users who have previously put 'android' in 3376121Snate@binkert.org # the disk image filename to tell the config scripts to 3382667Sstever@eecs.umich.edu # prepare the kernel with android-specific boot options. That 3395341Sstever@gmail.com # behavior has been replaced with a more explicit option per 3405863Snate@binkert.org # the error message below. The disk can have any name now and 3415341Sstever@gmail.com # doesn't need to include 'android' substring. 3425341Sstever@gmail.com if (os.path.split(mdesc.disk())[-1]).lower().count('android'): 3435341Sstever@gmail.com if 'android' not in mdesc.os_type(): 3448120Sgblack@eecs.umich.edu fatal("It looks like you are trying to boot an Android " \ 3455341Sstever@gmail.com "platform. To boot Android, you must specify " \ 3468120Sgblack@eecs.umich.edu "--os-type with an appropriate Android release on " \ 3475341Sstever@gmail.com "the command line.") 3488120Sgblack@eecs.umich.edu 3496121Snate@binkert.org # android-specific tweaks 3506121Snate@binkert.org if 'android' in mdesc.os_type(): 3518980Ssteve.reinhardt@amd.com # generic tweaks 3525397Ssaidi@eecs.umich.edu cmdline += " init=/init" 3535397Ssaidi@eecs.umich.edu 3547727SAli.Saidi@ARM.com # release-specific tweaks 3558268Ssteve.reinhardt@amd.com if 'kitkat' in mdesc.os_type(): 3566168Snate@binkert.org cmdline += " androidboot.hardware=gem5 qemu=1 qemu.gles=0 " + \ 3575341Sstever@gmail.com "android.bootanim=0 " 3588120Sgblack@eecs.umich.edu elif 'nougat' in mdesc.os_type(): 3598120Sgblack@eecs.umich.edu cmdline += " androidboot.hardware=gem5 qemu=1 qemu.gles=0 " + \ 3608120Sgblack@eecs.umich.edu "android.bootanim=0 " + \ 3616814Sgblack@eecs.umich.edu "vmalloc=640MB " + \ 3625863Snate@binkert.org "android.early.fstab=/fstab.gem5 " + \ 3638120Sgblack@eecs.umich.edu "androidboot.selinux=permissive " + \ 3645341Sstever@gmail.com "video=Virtual-1:1920x1080-16" 3655863Snate@binkert.org 3668268Ssteve.reinhardt@amd.com self.boot_osflags = fillInCmdline(mdesc, cmdline) 3676121Snate@binkert.org 3686121Snate@binkert.org if external_memory: 3698268Ssteve.reinhardt@amd.com # I/O traffic enters iobus 3705742Snate@binkert.org self.external_io = ExternalMaster(port_data="external_io", 3715742Snate@binkert.org port_type=external_memory) 3725341Sstever@gmail.com self.external_io.port = self.iobus.slave 3735742Snate@binkert.org 3745742Snate@binkert.org # Ensure iocache only receives traffic destined for (actual) memory. 3755341Sstever@gmail.com self.iocache = ExternalSlave(port_data="iocache", 3766017Snate@binkert.org port_type=external_memory, 3776121Snate@binkert.org addr_ranges=self.mem_ranges) 3786017Snate@binkert.org self.iocache.port = self.iobus.master 3797816Ssteve.reinhardt@amd.com 3807756SAli.Saidi@ARM.com # Let system_port get to nvmem and nothing else. 3817756SAli.Saidi@ARM.com self.bridge.ranges = [self.realview.nvmem.range] 3827756SAli.Saidi@ARM.com 3837756SAli.Saidi@ARM.com self.realview.attachOnChipIO(self.iobus) 3847756SAli.Saidi@ARM.com # Attach off-chip devices 3857756SAli.Saidi@ARM.com self.realview.attachIO(self.iobus) 3867756SAli.Saidi@ARM.com elif ruby: 3877756SAli.Saidi@ARM.com self._dma_ports = [ ] 3887816Ssteve.reinhardt@amd.com self.realview.attachOnChipIO(self.iobus, dma_ports=self._dma_ports) 3897816Ssteve.reinhardt@amd.com # Force Ruby to treat the boot ROM as an IO device. 3907816Ssteve.reinhardt@amd.com self.realview.nvmem.in_addr_map = False 3917816Ssteve.reinhardt@amd.com self.realview.attachIO(self.iobus, dma_ports=self._dma_ports) 3927816Ssteve.reinhardt@amd.com else: 3937816Ssteve.reinhardt@amd.com self.realview.attachOnChipIO(self.membus, self.bridge) 3947816Ssteve.reinhardt@amd.com # Attach off-chip devices 3957816Ssteve.reinhardt@amd.com self.realview.attachIO(self.iobus) 3967816Ssteve.reinhardt@amd.com 3977816Ssteve.reinhardt@amd.com for dev_id, dev in enumerate(pci_devices): 3987756SAli.Saidi@ARM.com dev.pci_bus, dev.pci_dev, dev.pci_func = (0, dev_id + 1, 0) 3997816Ssteve.reinhardt@amd.com self.realview.attachPciDevice( 4007816Ssteve.reinhardt@amd.com dev, self.iobus, 4017816Ssteve.reinhardt@amd.com dma_ports=self._dma_ports if ruby else None) 4027816Ssteve.reinhardt@amd.com 4037816Ssteve.reinhardt@amd.com self.intrctrl = IntrControl() 4047816Ssteve.reinhardt@amd.com self.terminal = Terminal() 4057816Ssteve.reinhardt@amd.com self.vncserver = VncServer() 4067816Ssteve.reinhardt@amd.com 4077816Ssteve.reinhardt@amd.com if not ruby: 4087816Ssteve.reinhardt@amd.com self.system_port = self.membus.slave 4097816Ssteve.reinhardt@amd.com 4107816Ssteve.reinhardt@amd.com if ruby: 4117816Ssteve.reinhardt@amd.com if buildEnv['PROTOCOL'] == 'MI_example' and num_cpus > 1: 4127816Ssteve.reinhardt@amd.com fatal("The MI_example protocol cannot implement Load/Store " 4137816Ssteve.reinhardt@amd.com "Exclusive operations. Multicore ARM systems configured " 4147816Ssteve.reinhardt@amd.com "with the MI_example protocol will not work properly.") 4157816Ssteve.reinhardt@amd.com warn("You are trying to use Ruby on ARM, which is not working " 4167816Ssteve.reinhardt@amd.com "properly yet.") 4177816Ssteve.reinhardt@amd.com 4187816Ssteve.reinhardt@amd.com return self 4197816Ssteve.reinhardt@amd.com 4207816Ssteve.reinhardt@amd.com 4217816Ssteve.reinhardt@amd.comdef makeLinuxMipsSystem(mem_mode, mdesc=None, cmdline=None): 4227816Ssteve.reinhardt@amd.com class BaseMalta(Malta): 4237816Ssteve.reinhardt@amd.com ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 4247816Ssteve.reinhardt@amd.com ide = IdeController(disks=[Parent.disk0, Parent.disk2], 4257816Ssteve.reinhardt@amd.com pci_func=0, pci_dev=0, pci_bus=0) 4267816Ssteve.reinhardt@amd.com 4277816Ssteve.reinhardt@amd.com self = LinuxMipsSystem() 4287816Ssteve.reinhardt@amd.com if not mdesc: 4297816Ssteve.reinhardt@amd.com # generic system 4307816Ssteve.reinhardt@amd.com mdesc = SysConfig() 4317816Ssteve.reinhardt@amd.com self.readfile = mdesc.script() 4327816Ssteve.reinhardt@amd.com self.iobus = IOXBar() 4337816Ssteve.reinhardt@amd.com self.membus = MemBus() 4347816Ssteve.reinhardt@amd.com self.bridge = Bridge(delay='50ns') 4357816Ssteve.reinhardt@amd.com self.mem_ranges = [AddrRange('1GB')] 4367816Ssteve.reinhardt@amd.com self.bridge.master = self.iobus.slave 4377816Ssteve.reinhardt@amd.com self.bridge.slave = self.membus.master 4387816Ssteve.reinhardt@amd.com self.disk0 = CowIdeDisk(driveID='master') 4397816Ssteve.reinhardt@amd.com self.disk2 = CowIdeDisk(driveID='master') 4407816Ssteve.reinhardt@amd.com self.disk0.childImage(mdesc.disk()) 4417816Ssteve.reinhardt@amd.com self.disk2.childImage(disk('linux-bigswap2.img')) 4427816Ssteve.reinhardt@amd.com self.malta = BaseMalta() 4437816Ssteve.reinhardt@amd.com self.malta.attachIO(self.iobus) 4447816Ssteve.reinhardt@amd.com self.malta.ide.pio = self.iobus.master 4457816Ssteve.reinhardt@amd.com self.malta.ide.dma = self.iobus.slave 4467816Ssteve.reinhardt@amd.com self.malta.ethernet.pio = self.iobus.master 4477816Ssteve.reinhardt@amd.com self.malta.ethernet.dma = self.iobus.slave 4487816Ssteve.reinhardt@amd.com self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 4497816Ssteve.reinhardt@amd.com read_only = True)) 4507816Ssteve.reinhardt@amd.com self.intrctrl = IntrControl() 4517816Ssteve.reinhardt@amd.com self.mem_mode = mem_mode 4527816Ssteve.reinhardt@amd.com self.terminal = Terminal() 4537816Ssteve.reinhardt@amd.com self.kernel = binary('mips/vmlinux') 4547816Ssteve.reinhardt@amd.com self.console = binary('mips/console') 4557816Ssteve.reinhardt@amd.com if not cmdline: 4567816Ssteve.reinhardt@amd.com cmdline = 'root=/dev/hda1 console=ttyS0' 4577816Ssteve.reinhardt@amd.com self.boot_osflags = fillInCmdline(mdesc, cmdline) 4587816Ssteve.reinhardt@amd.com 4597816Ssteve.reinhardt@amd.com self.system_port = self.membus.slave 4608947Sandreas.hansson@arm.com 4618947Sandreas.hansson@arm.com return self 4627756SAli.Saidi@ARM.com 4638120Sgblack@eecs.umich.edudef x86IOAddress(port): 4647756SAli.Saidi@ARM.com IO_address_space_base = 0x8000000000000000 4657756SAli.Saidi@ARM.com return IO_address_space_base + port 4667756SAli.Saidi@ARM.com 4677756SAli.Saidi@ARM.comdef connectX86ClassicSystem(x86_sys, numCPUs): 4687816Ssteve.reinhardt@amd.com # Constants similar to x86_traits.hh 4697816Ssteve.reinhardt@amd.com IO_address_space_base = 0x8000000000000000 4707816Ssteve.reinhardt@amd.com pci_config_address_space_base = 0xc000000000000000 4717816Ssteve.reinhardt@amd.com interrupts_address_space_base = 0xa000000000000000 4727816Ssteve.reinhardt@amd.com APIC_range_size = 1 << 12; 4737816Ssteve.reinhardt@amd.com 4747816Ssteve.reinhardt@amd.com x86_sys.membus = MemBus() 4757816Ssteve.reinhardt@amd.com 4767816Ssteve.reinhardt@amd.com # North Bridge 4777816Ssteve.reinhardt@amd.com x86_sys.iobus = IOXBar() 4787756SAli.Saidi@ARM.com x86_sys.bridge = Bridge(delay='50ns') 4797756SAli.Saidi@ARM.com x86_sys.bridge.master = x86_sys.iobus.slave 4806654Snate@binkert.org x86_sys.bridge.slave = x86_sys.membus.master 4816654Snate@binkert.org # Allow the bridge to pass through: 4825871Snate@binkert.org # 1) kernel configured PCI device memory map address: address range 4836121Snate@binkert.org # [0xC0000000, 0xFFFF0000). (The upper 64kB are reserved for m5ops.) 4846121Snate@binkert.org # 2) the bridge to pass through the IO APIC (two pages, already contained in 1), 4856121Snate@binkert.org # 3) everything in the IO address range up to the local APIC, and 4868946Sandreas.hansson@arm.com # 4) then the entire PCI address space and beyond. 4878737Skoansin.tan@gmail.com x86_sys.bridge.ranges = \ 4883940Ssaidi@eecs.umich.edu [ 4893918Ssaidi@eecs.umich.edu AddrRange(0xC0000000, 0xFFFF0000), 4903918Ssaidi@eecs.umich.edu AddrRange(IO_address_space_base, 4911858SN/A interrupts_address_space_base - 1), 4926121Snate@binkert.org AddrRange(pci_config_address_space_base, 4937739Sgblack@eecs.umich.edu Addr.max) 4947739Sgblack@eecs.umich.edu ] 4956143Snate@binkert.org 4967618SAli.Saidi@arm.com # Create a bridge from the IO bus to the memory bus to allow access to 4977618SAli.Saidi@arm.com # the local APIC (two pages) 4987618SAli.Saidi@arm.com x86_sys.apicbridge = Bridge(delay='50ns') 4997618SAli.Saidi@arm.com x86_sys.apicbridge.slave = x86_sys.iobus.master 5008614Sgblack@eecs.umich.edu x86_sys.apicbridge.master = x86_sys.membus.slave 5017618SAli.Saidi@arm.com x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base, 5027618SAli.Saidi@arm.com interrupts_address_space_base + 5037618SAli.Saidi@arm.com numCPUs * APIC_range_size 5047739Sgblack@eecs.umich.edu - 1)] 5058946Sandreas.hansson@arm.com 5068946Sandreas.hansson@arm.com # connect the io bus 5076121Snate@binkert.org x86_sys.pc.attachIO(x86_sys.iobus) 5083940Ssaidi@eecs.umich.edu 5096121Snate@binkert.org x86_sys.system_port = x86_sys.membus.slave 5107739Sgblack@eecs.umich.edu 5117739Sgblack@eecs.umich.edudef connectX86RubySystem(x86_sys): 5127739Sgblack@eecs.umich.edu # North Bridge 5137739Sgblack@eecs.umich.edu x86_sys.iobus = IOXBar() 5147739Sgblack@eecs.umich.edu 5157739Sgblack@eecs.umich.edu # add the ide to the list of dma devices that later need to attach to 5168737Skoansin.tan@gmail.com # dma controllers 5178737Skoansin.tan@gmail.com x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma] 5188737Skoansin.tan@gmail.com x86_sys.pc.attachIO(x86_sys.iobus, x86_sys._dma_ports) 5198737Skoansin.tan@gmail.com 5208737Skoansin.tan@gmail.com 5218737Skoansin.tan@gmail.comdef makeX86System(mem_mode, numCPUs=1, mdesc=None, self=None, Ruby=False): 5228737Skoansin.tan@gmail.com if self == None: 5238737Skoansin.tan@gmail.com self = X86System() 5248737Skoansin.tan@gmail.com 5258737Skoansin.tan@gmail.com if not mdesc: 5268737Skoansin.tan@gmail.com # generic system 5278737Skoansin.tan@gmail.com mdesc = SysConfig() 5288737Skoansin.tan@gmail.com self.readfile = mdesc.script() 5298737Skoansin.tan@gmail.com 5308737Skoansin.tan@gmail.com self.mem_mode = mem_mode 5318737Skoansin.tan@gmail.com 5328737Skoansin.tan@gmail.com # Physical memory 5338737Skoansin.tan@gmail.com # On the PC platform, the memory region 0xC0000000-0xFFFFFFFF is reserved 5348946Sandreas.hansson@arm.com # for various devices. Hence, if the physical memory size is greater than 5358946Sandreas.hansson@arm.com # 3GB, we need to split it into two parts. 5368946Sandreas.hansson@arm.com excess_mem_size = \ 5378946Sandreas.hansson@arm.com convert.toMemorySize(mdesc.mem()) - convert.toMemorySize('3GB') 5388946Sandreas.hansson@arm.com if excess_mem_size <= 0: 5398946Sandreas.hansson@arm.com self.mem_ranges = [AddrRange(mdesc.mem())] 5403918Ssaidi@eecs.umich.edu else: 5413918Ssaidi@eecs.umich.edu warn("Physical memory size specified is %s which is greater than " \ 5423940Ssaidi@eecs.umich.edu "3GB. Twice the number of memory controllers would be " \ 5433918Ssaidi@eecs.umich.edu "created." % (mdesc.mem())) 5443918Ssaidi@eecs.umich.edu 5456157Snate@binkert.org self.mem_ranges = [AddrRange('3GB'), 5466157Snate@binkert.org AddrRange(Addr('4GB'), size = excess_mem_size)] 5476157Snate@binkert.org 5486157Snate@binkert.org # Platform 5495397Ssaidi@eecs.umich.edu self.pc = Pc() 5505397Ssaidi@eecs.umich.edu 5516121Snate@binkert.org # Create and connect the busses required by each memory system 5526121Snate@binkert.org if Ruby: 5536121Snate@binkert.org connectX86RubySystem(self) 5546121Snate@binkert.org else: 5556121Snate@binkert.org connectX86ClassicSystem(self, numCPUs) 5566121Snate@binkert.org 5575397Ssaidi@eecs.umich.edu self.intrctrl = IntrControl() 5581851SN/A 5591851SN/A # Disks 5607739Sgblack@eecs.umich.edu disk0 = CowIdeDisk(driveID='master') 561955SN/A disk2 = CowIdeDisk(driveID='master') 5623053Sstever@eecs.umich.edu disk0.childImage(mdesc.disk()) 5636121Snate@binkert.org disk2.childImage(disk('linux-bigswap2.img')) 5643053Sstever@eecs.umich.edu self.pc.south_bridge.ide.disks = [disk0, disk2] 5653053Sstever@eecs.umich.edu 5663053Sstever@eecs.umich.edu # Add in a Bios information structure. 5673053Sstever@eecs.umich.edu structures = [X86SMBiosBiosInformation()] 5683053Sstever@eecs.umich.edu self.smbios_table.structures = structures 5696654Snate@binkert.org 5703053Sstever@eecs.umich.edu # Set up the Intel MP table 5714742Sstever@eecs.umich.edu base_entries = [] 5724742Sstever@eecs.umich.edu ext_entries = [] 5733053Sstever@eecs.umich.edu for i in xrange(numCPUs): 5743053Sstever@eecs.umich.edu bp = X86IntelMPProcessor( 5753053Sstever@eecs.umich.edu local_apic_id = i, 5768960Ssteve.reinhardt@amd.com local_apic_version = 0x14, 5776654Snate@binkert.org enable = True, 5783053Sstever@eecs.umich.edu bootstrap = (i == 0)) 5793053Sstever@eecs.umich.edu base_entries.append(bp) 5803053Sstever@eecs.umich.edu io_apic = X86IntelMPIOAPIC( 5813053Sstever@eecs.umich.edu id = numCPUs, 5822667Sstever@eecs.umich.edu version = 0x11, 5834554Sbinkertn@umich.edu enable = True, 5846121Snate@binkert.org address = 0xfec00000) 5852667Sstever@eecs.umich.edu self.pc.south_bridge.io_apic.apic_id = io_apic.id 5864554Sbinkertn@umich.edu base_entries.append(io_apic) 5874554Sbinkertn@umich.edu # In gem5 Pc::calcPciConfigAddr(), it required "assert(bus==0)", 5884554Sbinkertn@umich.edu # but linux kernel cannot config PCI device if it was not connected to PCI bus, 5896121Snate@binkert.org # so we fix PCI bus id to 0, and ISA bus id to 1. 5904554Sbinkertn@umich.edu pci_bus = X86IntelMPBus(bus_id = 0, bus_type='PCI ') 5914554Sbinkertn@umich.edu base_entries.append(pci_bus) 5924554Sbinkertn@umich.edu isa_bus = X86IntelMPBus(bus_id = 1, bus_type='ISA ') 5934781Snate@binkert.org base_entries.append(isa_bus) 5944554Sbinkertn@umich.edu connect_busses = X86IntelMPBusHierarchy(bus_id=1, 5954554Sbinkertn@umich.edu subtractive_decode=True, parent_bus=0) 5962667Sstever@eecs.umich.edu ext_entries.append(connect_busses) 5974554Sbinkertn@umich.edu pci_dev4_inta = X86IntelMPIOIntAssignment( 5984554Sbinkertn@umich.edu interrupt_type = 'INT', 5994554Sbinkertn@umich.edu polarity = 'ConformPolarity', 6004554Sbinkertn@umich.edu trigger = 'ConformTrigger', 6012667Sstever@eecs.umich.edu source_bus_id = 0, 6024554Sbinkertn@umich.edu source_bus_irq = 0 + (4 << 2), 6032667Sstever@eecs.umich.edu dest_io_apic_id = io_apic.id, 6044554Sbinkertn@umich.edu dest_io_apic_intin = 16) 6056121Snate@binkert.org base_entries.append(pci_dev4_inta) 6062667Sstever@eecs.umich.edu def assignISAInt(irq, apicPin): 6075522Snate@binkert.org assign_8259_to_apic = X86IntelMPIOIntAssignment( 6085522Snate@binkert.org interrupt_type = 'ExtInt', 6095522Snate@binkert.org polarity = 'ConformPolarity', 6105522Snate@binkert.org trigger = 'ConformTrigger', 6115522Snate@binkert.org source_bus_id = 1, 6125522Snate@binkert.org source_bus_irq = irq, 6135522Snate@binkert.org dest_io_apic_id = io_apic.id, 6145522Snate@binkert.org dest_io_apic_intin = 0) 6155522Snate@binkert.org base_entries.append(assign_8259_to_apic) 6165522Snate@binkert.org assign_to_apic = X86IntelMPIOIntAssignment( 6175522Snate@binkert.org interrupt_type = 'INT', 6185522Snate@binkert.org polarity = 'ConformPolarity', 6195522Snate@binkert.org trigger = 'ConformTrigger', 6205522Snate@binkert.org source_bus_id = 1, 6215522Snate@binkert.org source_bus_irq = irq, 6225522Snate@binkert.org dest_io_apic_id = io_apic.id, 6235522Snate@binkert.org dest_io_apic_intin = apicPin) 6245522Snate@binkert.org base_entries.append(assign_to_apic) 6255522Snate@binkert.org assignISAInt(0, 2) 6265522Snate@binkert.org assignISAInt(1, 1) 6275522Snate@binkert.org for i in range(3, 15): 6285522Snate@binkert.org assignISAInt(i, i) 6295522Snate@binkert.org self.intel_mp_table.base_entries = base_entries 6305522Snate@binkert.org self.intel_mp_table.ext_entries = ext_entries 6315522Snate@binkert.org 6325522Snate@binkert.orgdef makeLinuxX86System(mem_mode, numCPUs=1, mdesc=None, Ruby=False, 6332638Sstever@eecs.umich.edu cmdline=None): 6342638Sstever@eecs.umich.edu self = LinuxX86System() 6356121Snate@binkert.org 6363716Sstever@eecs.umich.edu # Build up the x86 system and then specialize it for Linux 6375522Snate@binkert.org makeX86System(mem_mode, numCPUs, mdesc, self, Ruby) 6385522Snate@binkert.org 6395522Snate@binkert.org # We assume below that there's at least 1MB of memory. We'll require 2 6405522Snate@binkert.org # just to avoid corner cases. 6415522Snate@binkert.org phys_mem_size = sum(map(lambda r: r.size(), self.mem_ranges)) 6425522Snate@binkert.org assert(phys_mem_size >= 0x200000) 6431858SN/A assert(len(self.mem_ranges) <= 2) 6445227Ssaidi@eecs.umich.edu 6455227Ssaidi@eecs.umich.edu entries = \ 6465227Ssaidi@eecs.umich.edu [ 6475227Ssaidi@eecs.umich.edu # Mark the first megabyte of memory as reserved 6486654Snate@binkert.org X86E820Entry(addr = 0, size = '639kB', range_type = 1), 6496654Snate@binkert.org X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2), 6507769SAli.Saidi@ARM.com # Mark the rest of physical memory as available 6517769SAli.Saidi@ARM.com X86E820Entry(addr = 0x100000, 6527769SAli.Saidi@ARM.com size = '%dB' % (self.mem_ranges[0].size() - 0x100000), 6537769SAli.Saidi@ARM.com range_type = 1), 6545227Ssaidi@eecs.umich.edu ] 6555227Ssaidi@eecs.umich.edu 6565227Ssaidi@eecs.umich.edu # Mark [mem_size, 3GB) as reserved if memory less than 3GB, which force 6575204Sstever@gmail.com # IO devices to be mapped to [0xC0000000, 0xFFFF0000). Requests to this 6585204Sstever@gmail.com # specific range can pass though bridge to iobus. 6595204Sstever@gmail.com if len(self.mem_ranges) == 1: 6605204Sstever@gmail.com entries.append(X86E820Entry(addr = self.mem_ranges[0].size(), 6615204Sstever@gmail.com size='%dB' % (0xC0000000 - self.mem_ranges[0].size()), 6625204Sstever@gmail.com range_type=2)) 6635204Sstever@gmail.com 6645204Sstever@gmail.com # Reserve the last 16kB of the 32-bit address space for the m5op interface 6655204Sstever@gmail.com entries.append(X86E820Entry(addr=0xFFFF0000, size='64kB', range_type=2)) 6665204Sstever@gmail.com 6675204Sstever@gmail.com # In case the physical memory is greater than 3GB, we split it into two 6685204Sstever@gmail.com # parts and add a separate e820 entry for the second part. This entry 6695204Sstever@gmail.com # starts at 0x100000000, which is the first address after the space 6705204Sstever@gmail.com # reserved for devices. 6715204Sstever@gmail.com if len(self.mem_ranges) == 2: 6725204Sstever@gmail.com entries.append(X86E820Entry(addr = 0x100000000, 6735204Sstever@gmail.com size = '%dB' % (self.mem_ranges[1].size()), range_type = 1)) 6746121Snate@binkert.org 6755204Sstever@gmail.com self.e820_table.entries = entries 6763118Sstever@eecs.umich.edu 6773118Sstever@eecs.umich.edu # Command line 6783118Sstever@eecs.umich.edu if not cmdline: 6793118Sstever@eecs.umich.edu cmdline = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1' 6803118Sstever@eecs.umich.edu self.boot_osflags = fillInCmdline(mdesc, cmdline) 6815863Snate@binkert.org self.kernel = binary('x86_64-vmlinux-2.6.22.9') 6823118Sstever@eecs.umich.edu return self 6835863Snate@binkert.org 6843118Sstever@eecs.umich.edu 6857457Snate@binkert.orgdef makeDualRoot(full_system, testSystem, driveSystem, dumpfile): 6867457Snate@binkert.org self = Root(full_system = full_system) 6875863Snate@binkert.org self.testsys = testSystem 6885863Snate@binkert.org self.drivesys = driveSystem 6895863Snate@binkert.org self.etherlink = EtherLink() 6905863Snate@binkert.org 6915863Snate@binkert.org if hasattr(testSystem, 'realview'): 6925863Snate@binkert.org self.etherlink.int0 = Parent.testsys.realview.ethernet.interface 6935863Snate@binkert.org self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface 6946003Snate@binkert.org elif hasattr(testSystem, 'tsunami'): 6955863Snate@binkert.org self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 6965863Snate@binkert.org self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 6975863Snate@binkert.org else: 6986120Snate@binkert.org fatal("Don't know how to connect these system together") 6995863Snate@binkert.org 7005863Snate@binkert.org if dumpfile: 7015863Snate@binkert.org self.etherdump = EtherDump(file=dumpfile) 7028655Sandreas.hansson@arm.com self.etherlink.dump = Parent.etherdump 7038655Sandreas.hansson@arm.com 7048655Sandreas.hansson@arm.com return self 7058655Sandreas.hansson@arm.com 7068655Sandreas.hansson@arm.com 7078655Sandreas.hansson@arm.comdef makeDistRoot(testSystem, 7088655Sandreas.hansson@arm.com rank, 7098655Sandreas.hansson@arm.com size, 7106120Snate@binkert.org server_name, 7115863Snate@binkert.org server_port, 7126121Snate@binkert.org sync_repeat, 7136121Snate@binkert.org sync_start, 7145863Snate@binkert.org linkspeed, 7157727SAli.Saidi@ARM.com linkdelay, 7167727SAli.Saidi@ARM.com dumpfile): 7177727SAli.Saidi@ARM.com self = Root(full_system = True) 7187727SAli.Saidi@ARM.com self.testsys = testSystem 7197727SAli.Saidi@ARM.com 7207727SAli.Saidi@ARM.com self.etherlink = DistEtherLink(speed = linkspeed, 7215863Snate@binkert.org delay = linkdelay, 7223118Sstever@eecs.umich.edu dist_rank = rank, 7235863Snate@binkert.org dist_size = size, 7243118Sstever@eecs.umich.edu server_name = server_name, 7253118Sstever@eecs.umich.edu server_port = server_port, 7265863Snate@binkert.org sync_start = sync_start, 7275863Snate@binkert.org sync_repeat = sync_repeat) 7285863Snate@binkert.org 7295863Snate@binkert.org if hasattr(testSystem, 'realview'): 7303118Sstever@eecs.umich.edu self.etherlink.int0 = Parent.testsys.realview.ethernet.interface 7313483Ssaidi@eecs.umich.edu elif hasattr(testSystem, 'tsunami'): 7323494Ssaidi@eecs.umich.edu self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 7333494Ssaidi@eecs.umich.edu else: 7343483Ssaidi@eecs.umich.edu fatal("Don't know how to connect DistEtherLink to this system") 7353483Ssaidi@eecs.umich.edu 7363483Ssaidi@eecs.umich.edu if dumpfile: 7373053Sstever@eecs.umich.edu self.etherdump = EtherDump(file=dumpfile) 7383053Sstever@eecs.umich.edu self.etherlink.dump = Parent.etherdump 7393918Ssaidi@eecs.umich.edu 7403053Sstever@eecs.umich.edu return self 7413053Sstever@eecs.umich.edu