FSConfig.py revision 11238:627dd43a5846
1# Copyright (c) 2010-2012, 2015 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2010-2011 Advanced Micro Devices, Inc. 14# Copyright (c) 2006-2008 The Regents of The University of Michigan 15# All rights reserved. 16# 17# Redistribution and use in source and binary forms, with or without 18# modification, are permitted provided that the following conditions are 19# met: redistributions of source code must retain the above copyright 20# notice, this list of conditions and the following disclaimer; 21# redistributions in binary form must reproduce the above copyright 22# notice, this list of conditions and the following disclaimer in the 23# documentation and/or other materials provided with the distribution; 24# neither the name of the copyright holders nor the names of its 25# contributors may be used to endorse or promote products derived from 26# this software without specific prior written permission. 27# 28# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39# 40# Authors: Kevin Lim 41 42from m5.objects import * 43from Benchmarks import * 44from m5.util import * 45import PlatformConfig 46 47# Populate to reflect supported os types per target ISA 48os_types = { 'alpha' : [ 'linux' ], 49 'mips' : [ 'linux' ], 50 'sparc' : [ 'linux' ], 51 'x86' : [ 'linux' ], 52 'arm' : [ 'linux', 53 'android-gingerbread', 54 'android-ics', 55 'android-jellybean', 56 'android-kitkat' ], 57 } 58 59class CowIdeDisk(IdeDisk): 60 image = CowDiskImage(child=RawDiskImage(read_only=True), 61 read_only=False) 62 63 def childImage(self, ci): 64 self.image.child.image_file = ci 65 66class MemBus(SystemXBar): 67 badaddr_responder = BadAddr() 68 default = Self.badaddr_responder.pio 69 70def fillInCmdline(mdesc, template, **kwargs): 71 kwargs.setdefault('disk', mdesc.disk()) 72 kwargs.setdefault('rootdev', mdesc.rootdev()) 73 kwargs.setdefault('mem', mdesc.mem()) 74 kwargs.setdefault('script', mdesc.script()) 75 return template % kwargs 76 77def makeLinuxAlphaSystem(mem_mode, mdesc=None, ruby=False, cmdline=None): 78 79 class BaseTsunami(Tsunami): 80 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 81 ide = IdeController(disks=[Parent.disk0, Parent.disk2], 82 pci_func=0, pci_dev=0, pci_bus=0) 83 84 self = LinuxAlphaSystem() 85 if not mdesc: 86 # generic system 87 mdesc = SysConfig() 88 self.readfile = mdesc.script() 89 90 self.tsunami = BaseTsunami() 91 92 # Create the io bus to connect all device ports 93 self.iobus = IOXBar() 94 self.tsunami.attachIO(self.iobus) 95 96 self.tsunami.ide.pio = self.iobus.master 97 self.tsunami.ide.config = self.iobus.master 98 99 self.tsunami.ethernet.pio = self.iobus.master 100 self.tsunami.ethernet.config = self.iobus.master 101 102 if ruby: 103 # Store the dma devices for later connection to dma ruby ports. 104 # Append an underscore to dma_ports to avoid the SimObjectVector check. 105 self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma] 106 else: 107 self.membus = MemBus() 108 109 # By default the bridge responds to all addresses above the I/O 110 # base address (including the PCI config space) 111 IO_address_space_base = 0x80000000000 112 self.bridge = Bridge(delay='50ns', 113 ranges = [AddrRange(IO_address_space_base, Addr.max)]) 114 self.bridge.master = self.iobus.slave 115 self.bridge.slave = self.membus.master 116 117 self.tsunami.ide.dma = self.iobus.slave 118 self.tsunami.ethernet.dma = self.iobus.slave 119 120 self.system_port = self.membus.slave 121 122 self.mem_ranges = [AddrRange(mdesc.mem())] 123 self.disk0 = CowIdeDisk(driveID='master') 124 self.disk2 = CowIdeDisk(driveID='master') 125 self.disk0.childImage(mdesc.disk()) 126 self.disk2.childImage(disk('linux-bigswap2.img')) 127 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 128 read_only = True)) 129 self.intrctrl = IntrControl() 130 self.mem_mode = mem_mode 131 self.terminal = Terminal() 132 self.kernel = binary('vmlinux') 133 self.pal = binary('ts_osfpal') 134 self.console = binary('console') 135 if not cmdline: 136 cmdline = 'root=/dev/hda1 console=ttyS0' 137 self.boot_osflags = fillInCmdline(mdesc, cmdline) 138 139 return self 140 141def makeSparcSystem(mem_mode, mdesc=None, cmdline=None): 142 # Constants from iob.cc and uart8250.cc 143 iob_man_addr = 0x9800000000 144 uart_pio_size = 8 145 146 class CowMmDisk(MmDisk): 147 image = CowDiskImage(child=RawDiskImage(read_only=True), 148 read_only=False) 149 150 def childImage(self, ci): 151 self.image.child.image_file = ci 152 153 self = SparcSystem() 154 if not mdesc: 155 # generic system 156 mdesc = SysConfig() 157 self.readfile = mdesc.script() 158 self.iobus = IOXBar() 159 self.membus = MemBus() 160 self.bridge = Bridge(delay='50ns') 161 self.t1000 = T1000() 162 self.t1000.attachOnChipIO(self.membus) 163 self.t1000.attachIO(self.iobus) 164 self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'), 165 AddrRange(Addr('2GB'), size ='256MB')] 166 self.bridge.master = self.iobus.slave 167 self.bridge.slave = self.membus.master 168 self.rom.port = self.membus.master 169 self.nvram.port = self.membus.master 170 self.hypervisor_desc.port = self.membus.master 171 self.partition_desc.port = self.membus.master 172 self.intrctrl = IntrControl() 173 self.disk0 = CowMmDisk() 174 self.disk0.childImage(disk('disk.s10hw2')) 175 self.disk0.pio = self.iobus.master 176 177 # The puart0 and hvuart are placed on the IO bus, so create ranges 178 # for them. The remaining IO range is rather fragmented, so poke 179 # holes for the iob and partition descriptors etc. 180 self.bridge.ranges = \ 181 [ 182 AddrRange(self.t1000.puart0.pio_addr, 183 self.t1000.puart0.pio_addr + uart_pio_size - 1), 184 AddrRange(self.disk0.pio_addr, 185 self.t1000.fake_jbi.pio_addr + 186 self.t1000.fake_jbi.pio_size - 1), 187 AddrRange(self.t1000.fake_clk.pio_addr, 188 iob_man_addr - 1), 189 AddrRange(self.t1000.fake_l2_1.pio_addr, 190 self.t1000.fake_ssi.pio_addr + 191 self.t1000.fake_ssi.pio_size - 1), 192 AddrRange(self.t1000.hvuart.pio_addr, 193 self.t1000.hvuart.pio_addr + uart_pio_size - 1) 194 ] 195 self.reset_bin = binary('reset_new.bin') 196 self.hypervisor_bin = binary('q_new.bin') 197 self.openboot_bin = binary('openboot_new.bin') 198 self.nvram_bin = binary('nvram1') 199 self.hypervisor_desc_bin = binary('1up-hv.bin') 200 self.partition_desc_bin = binary('1up-md.bin') 201 202 self.system_port = self.membus.slave 203 204 return self 205 206def makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None, 207 dtb_filename=None, bare_metal=False, cmdline=None, 208 external_memory=""): 209 assert machine_type 210 211 default_dtbs = { 212 "RealViewEB": None, 213 "RealViewPBX": None, 214 "VExpress_EMM": "vexpress.aarch32.ll_20131205.0-gem5.%dcpu.dtb" % num_cpus, 215 "VExpress_EMM64": "vexpress.aarch64.20140821.dtb", 216 } 217 218 default_kernels = { 219 "RealViewEB": "vmlinux.arm.smp.fb.2.6.38.8", 220 "RealViewPBX": "vmlinux.arm.smp.fb.2.6.38.8", 221 "VExpress_EMM": "vmlinux.aarch32.ll_20131205.0-gem5", 222 "VExpress_EMM64": "vmlinux.aarch64.20140821", 223 } 224 225 if bare_metal: 226 self = ArmSystem() 227 else: 228 self = LinuxArmSystem() 229 230 if not mdesc: 231 # generic system 232 mdesc = SysConfig() 233 234 self.readfile = mdesc.script() 235 self.iobus = IOXBar() 236 self.membus = MemBus() 237 self.membus.badaddr_responder.warn_access = "warn" 238 self.bridge = Bridge(delay='50ns') 239 self.bridge.master = self.iobus.slave 240 self.bridge.slave = self.membus.master 241 242 self.mem_mode = mem_mode 243 244 platform_class = PlatformConfig.get(machine_type) 245 # Resolve the real platform name, the original machine_type 246 # variable might have been an alias. 247 machine_type = platform_class.__name__ 248 self.realview = platform_class() 249 250 if not dtb_filename and not bare_metal: 251 try: 252 dtb_filename = default_dtbs[machine_type] 253 except KeyError: 254 fatal("No DTB specified and no default DTB known for '%s'" % \ 255 machine_type) 256 257 if isinstance(self.realview, VExpress_EMM64): 258 if os.path.split(mdesc.disk())[-1] == 'linux-aarch32-ael.img': 259 print "Selected 64-bit ARM architecture, updating default disk image..." 260 mdesc.diskname = 'linaro-minimal-aarch64.img' 261 262 self.cf0 = CowIdeDisk(driveID='master') 263 self.cf0.childImage(mdesc.disk()) 264 265 # Attach any PCI devices this platform supports 266 self.realview.attachPciDevices() 267 # default to an IDE controller rather than a CF one 268 try: 269 self.realview.ide.disks = [self.cf0] 270 except: 271 self.realview.cf_ctrl.disks = [self.cf0] 272 273 self.mem_ranges = [] 274 size_remain = long(Addr(mdesc.mem())) 275 for region in self.realview._mem_regions: 276 if size_remain > long(region[1]): 277 self.mem_ranges.append(AddrRange(region[0], size=region[1])) 278 size_remain = size_remain - long(region[1]) 279 else: 280 self.mem_ranges.append(AddrRange(region[0], size=size_remain)) 281 size_remain = 0 282 break 283 warn("Memory size specified spans more than one region. Creating" \ 284 " another memory controller for that range.") 285 286 if size_remain > 0: 287 fatal("The currently selected ARM platforms doesn't support" \ 288 " the amount of DRAM you've selected. Please try" \ 289 " another platform") 290 291 if bare_metal: 292 # EOT character on UART will end the simulation 293 self.realview.uart.end_on_eot = True 294 else: 295 if machine_type in default_kernels: 296 self.kernel = binary(default_kernels[machine_type]) 297 298 if dtb_filename: 299 self.dtb_filename = binary(dtb_filename) 300 301 self.machine_type = machine_type if machine_type in ArmMachineType.map \ 302 else "DTOnly" 303 304 # Ensure that writes to the UART actually go out early in the boot 305 if not cmdline: 306 cmdline = 'earlyprintk=pl011,0x1c090000 console=ttyAMA0 ' + \ 307 'lpj=19988480 norandmaps rw loglevel=8 ' + \ 308 'mem=%(mem)s root=%(rootdev)s' 309 310 # When using external memory, gem5 writes the boot loader to nvmem 311 # and then SST will read from it, but SST can only get to nvmem from 312 # iobus, as gem5's membus is only used for initialization and 313 # SST doesn't use it. Attaching nvmem to iobus solves this issue. 314 # During initialization, system_port -> membus -> iobus -> nvmem. 315 if external_memory: 316 self.realview.setupBootLoader(self.iobus, self, binary) 317 else: 318 self.realview.setupBootLoader(self.membus, self, binary) 319 self.gic_cpu_addr = self.realview.gic.cpu_addr 320 self.flags_addr = self.realview.realview_io.pio_addr + 0x30 321 322 # This check is for users who have previously put 'android' in 323 # the disk image filename to tell the config scripts to 324 # prepare the kernel with android-specific boot options. That 325 # behavior has been replaced with a more explicit option per 326 # the error message below. The disk can have any name now and 327 # doesn't need to include 'android' substring. 328 if (os.path.split(mdesc.disk())[-1]).lower().count('android'): 329 if 'android' not in mdesc.os_type(): 330 fatal("It looks like you are trying to boot an Android " \ 331 "platform. To boot Android, you must specify " \ 332 "--os-type with an appropriate Android release on " \ 333 "the command line.") 334 335 # android-specific tweaks 336 if 'android' in mdesc.os_type(): 337 # generic tweaks 338 cmdline += " init=/init" 339 340 # release-specific tweaks 341 if 'kitkat' in mdesc.os_type(): 342 cmdline += " androidboot.hardware=gem5 qemu=1 qemu.gles=0 " + \ 343 "android.bootanim=0" 344 345 self.boot_osflags = fillInCmdline(mdesc, cmdline) 346 347 if external_memory: 348 # I/O traffic enters iobus 349 self.external_io = ExternalMaster(port_data="external_io", 350 port_type=external_memory) 351 self.external_io.port = self.iobus.slave 352 353 # Ensure iocache only receives traffic destined for (actual) memory. 354 self.iocache = ExternalSlave(port_data="iocache", 355 port_type=external_memory, 356 addr_ranges=self.mem_ranges) 357 self.iocache.port = self.iobus.master 358 359 # Let system_port get to nvmem and nothing else. 360 self.bridge.ranges = [self.realview.nvmem.range] 361 362 self.realview.attachOnChipIO(self.iobus) 363 else: 364 self.realview.attachOnChipIO(self.membus, self.bridge) 365 self.realview.attachIO(self.iobus) 366 self.intrctrl = IntrControl() 367 self.terminal = Terminal() 368 self.vncserver = VncServer() 369 370 self.system_port = self.membus.slave 371 372 return self 373 374 375def makeLinuxMipsSystem(mem_mode, mdesc=None, cmdline=None): 376 class BaseMalta(Malta): 377 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 378 ide = IdeController(disks=[Parent.disk0, Parent.disk2], 379 pci_func=0, pci_dev=0, pci_bus=0) 380 381 self = LinuxMipsSystem() 382 if not mdesc: 383 # generic system 384 mdesc = SysConfig() 385 self.readfile = mdesc.script() 386 self.iobus = IOXBar() 387 self.membus = MemBus() 388 self.bridge = Bridge(delay='50ns') 389 self.mem_ranges = [AddrRange('1GB')] 390 self.bridge.master = self.iobus.slave 391 self.bridge.slave = self.membus.master 392 self.disk0 = CowIdeDisk(driveID='master') 393 self.disk2 = CowIdeDisk(driveID='master') 394 self.disk0.childImage(mdesc.disk()) 395 self.disk2.childImage(disk('linux-bigswap2.img')) 396 self.malta = BaseMalta() 397 self.malta.attachIO(self.iobus) 398 self.malta.ide.pio = self.iobus.master 399 self.malta.ide.config = self.iobus.master 400 self.malta.ide.dma = self.iobus.slave 401 self.malta.ethernet.pio = self.iobus.master 402 self.malta.ethernet.config = self.iobus.master 403 self.malta.ethernet.dma = self.iobus.slave 404 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 405 read_only = True)) 406 self.intrctrl = IntrControl() 407 self.mem_mode = mem_mode 408 self.terminal = Terminal() 409 self.kernel = binary('mips/vmlinux') 410 self.console = binary('mips/console') 411 if not cmdline: 412 cmdline = 'root=/dev/hda1 console=ttyS0' 413 self.boot_osflags = fillInCmdline(mdesc, cmdline) 414 415 self.system_port = self.membus.slave 416 417 return self 418 419def x86IOAddress(port): 420 IO_address_space_base = 0x8000000000000000 421 return IO_address_space_base + port 422 423def connectX86ClassicSystem(x86_sys, numCPUs): 424 # Constants similar to x86_traits.hh 425 IO_address_space_base = 0x8000000000000000 426 pci_config_address_space_base = 0xc000000000000000 427 interrupts_address_space_base = 0xa000000000000000 428 APIC_range_size = 1 << 12; 429 430 x86_sys.membus = MemBus() 431 432 # North Bridge 433 x86_sys.iobus = IOXBar() 434 x86_sys.bridge = Bridge(delay='50ns') 435 x86_sys.bridge.master = x86_sys.iobus.slave 436 x86_sys.bridge.slave = x86_sys.membus.master 437 # Allow the bridge to pass through: 438 # 1) kernel configured PCI device memory map address: address range 439 # [0xC0000000, 0xFFFF0000). (The upper 64kB are reserved for m5ops.) 440 # 2) the bridge to pass through the IO APIC (two pages, already contained in 1), 441 # 3) everything in the IO address range up to the local APIC, and 442 # 4) then the entire PCI address space and beyond. 443 x86_sys.bridge.ranges = \ 444 [ 445 AddrRange(0xC0000000, 0xFFFF0000), 446 AddrRange(IO_address_space_base, 447 interrupts_address_space_base - 1), 448 AddrRange(pci_config_address_space_base, 449 Addr.max) 450 ] 451 452 # Create a bridge from the IO bus to the memory bus to allow access to 453 # the local APIC (two pages) 454 x86_sys.apicbridge = Bridge(delay='50ns') 455 x86_sys.apicbridge.slave = x86_sys.iobus.master 456 x86_sys.apicbridge.master = x86_sys.membus.slave 457 x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base, 458 interrupts_address_space_base + 459 numCPUs * APIC_range_size 460 - 1)] 461 462 # connect the io bus 463 x86_sys.pc.attachIO(x86_sys.iobus) 464 465 x86_sys.system_port = x86_sys.membus.slave 466 467def connectX86RubySystem(x86_sys): 468 # North Bridge 469 x86_sys.iobus = IOXBar() 470 471 # add the ide to the list of dma devices that later need to attach to 472 # dma controllers 473 x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma] 474 x86_sys.pc.attachIO(x86_sys.iobus, x86_sys._dma_ports) 475 476 477def makeX86System(mem_mode, numCPUs=1, mdesc=None, self=None, Ruby=False): 478 if self == None: 479 self = X86System() 480 481 if not mdesc: 482 # generic system 483 mdesc = SysConfig() 484 self.readfile = mdesc.script() 485 486 self.mem_mode = mem_mode 487 488 # Physical memory 489 # On the PC platform, the memory region 0xC0000000-0xFFFFFFFF is reserved 490 # for various devices. Hence, if the physical memory size is greater than 491 # 3GB, we need to split it into two parts. 492 excess_mem_size = \ 493 convert.toMemorySize(mdesc.mem()) - convert.toMemorySize('3GB') 494 if excess_mem_size <= 0: 495 self.mem_ranges = [AddrRange(mdesc.mem())] 496 else: 497 warn("Physical memory size specified is %s which is greater than " \ 498 "3GB. Twice the number of memory controllers would be " \ 499 "created." % (mdesc.mem())) 500 501 self.mem_ranges = [AddrRange('3GB'), 502 AddrRange(Addr('4GB'), size = excess_mem_size)] 503 504 # Platform 505 self.pc = Pc() 506 507 # Create and connect the busses required by each memory system 508 if Ruby: 509 connectX86RubySystem(self) 510 else: 511 connectX86ClassicSystem(self, numCPUs) 512 513 self.intrctrl = IntrControl() 514 515 # Disks 516 disk0 = CowIdeDisk(driveID='master') 517 disk2 = CowIdeDisk(driveID='master') 518 disk0.childImage(mdesc.disk()) 519 disk2.childImage(disk('linux-bigswap2.img')) 520 self.pc.south_bridge.ide.disks = [disk0, disk2] 521 522 # Add in a Bios information structure. 523 structures = [X86SMBiosBiosInformation()] 524 self.smbios_table.structures = structures 525 526 # Set up the Intel MP table 527 base_entries = [] 528 ext_entries = [] 529 for i in xrange(numCPUs): 530 bp = X86IntelMPProcessor( 531 local_apic_id = i, 532 local_apic_version = 0x14, 533 enable = True, 534 bootstrap = (i == 0)) 535 base_entries.append(bp) 536 io_apic = X86IntelMPIOAPIC( 537 id = numCPUs, 538 version = 0x11, 539 enable = True, 540 address = 0xfec00000) 541 self.pc.south_bridge.io_apic.apic_id = io_apic.id 542 base_entries.append(io_apic) 543 # In gem5 Pc::calcPciConfigAddr(), it required "assert(bus==0)", 544 # but linux kernel cannot config PCI device if it was not connected to PCI bus, 545 # so we fix PCI bus id to 0, and ISA bus id to 1. 546 pci_bus = X86IntelMPBus(bus_id = 0, bus_type='PCI') 547 base_entries.append(pci_bus) 548 isa_bus = X86IntelMPBus(bus_id = 1, bus_type='ISA') 549 base_entries.append(isa_bus) 550 connect_busses = X86IntelMPBusHierarchy(bus_id=1, 551 subtractive_decode=True, parent_bus=0) 552 ext_entries.append(connect_busses) 553 pci_dev4_inta = X86IntelMPIOIntAssignment( 554 interrupt_type = 'INT', 555 polarity = 'ConformPolarity', 556 trigger = 'ConformTrigger', 557 source_bus_id = 0, 558 source_bus_irq = 0 + (4 << 2), 559 dest_io_apic_id = io_apic.id, 560 dest_io_apic_intin = 16) 561 base_entries.append(pci_dev4_inta) 562 def assignISAInt(irq, apicPin): 563 assign_8259_to_apic = X86IntelMPIOIntAssignment( 564 interrupt_type = 'ExtInt', 565 polarity = 'ConformPolarity', 566 trigger = 'ConformTrigger', 567 source_bus_id = 1, 568 source_bus_irq = irq, 569 dest_io_apic_id = io_apic.id, 570 dest_io_apic_intin = 0) 571 base_entries.append(assign_8259_to_apic) 572 assign_to_apic = X86IntelMPIOIntAssignment( 573 interrupt_type = 'INT', 574 polarity = 'ConformPolarity', 575 trigger = 'ConformTrigger', 576 source_bus_id = 1, 577 source_bus_irq = irq, 578 dest_io_apic_id = io_apic.id, 579 dest_io_apic_intin = apicPin) 580 base_entries.append(assign_to_apic) 581 assignISAInt(0, 2) 582 assignISAInt(1, 1) 583 for i in range(3, 15): 584 assignISAInt(i, i) 585 self.intel_mp_table.base_entries = base_entries 586 self.intel_mp_table.ext_entries = ext_entries 587 588def makeLinuxX86System(mem_mode, numCPUs=1, mdesc=None, Ruby=False, 589 cmdline=None): 590 self = LinuxX86System() 591 592 # Build up the x86 system and then specialize it for Linux 593 makeX86System(mem_mode, numCPUs, mdesc, self, Ruby) 594 595 # We assume below that there's at least 1MB of memory. We'll require 2 596 # just to avoid corner cases. 597 phys_mem_size = sum(map(lambda r: r.size(), self.mem_ranges)) 598 assert(phys_mem_size >= 0x200000) 599 assert(len(self.mem_ranges) <= 2) 600 601 entries = \ 602 [ 603 # Mark the first megabyte of memory as reserved 604 X86E820Entry(addr = 0, size = '639kB', range_type = 1), 605 X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2), 606 # Mark the rest of physical memory as available 607 X86E820Entry(addr = 0x100000, 608 size = '%dB' % (self.mem_ranges[0].size() - 0x100000), 609 range_type = 1), 610 ] 611 612 # Mark [mem_size, 3GB) as reserved if memory less than 3GB, which force 613 # IO devices to be mapped to [0xC0000000, 0xFFFF0000). Requests to this 614 # specific range can pass though bridge to iobus. 615 if len(self.mem_ranges) == 1: 616 entries.append(X86E820Entry(addr = self.mem_ranges[0].size(), 617 size='%dB' % (0xC0000000 - self.mem_ranges[0].size()), 618 range_type=2)) 619 620 # Reserve the last 16kB of the 32-bit address space for the m5op interface 621 entries.append(X86E820Entry(addr=0xFFFF0000, size='64kB', range_type=2)) 622 623 # In case the physical memory is greater than 3GB, we split it into two 624 # parts and add a separate e820 entry for the second part. This entry 625 # starts at 0x100000000, which is the first address after the space 626 # reserved for devices. 627 if len(self.mem_ranges) == 2: 628 entries.append(X86E820Entry(addr = 0x100000000, 629 size = '%dB' % (self.mem_ranges[1].size()), range_type = 1)) 630 631 self.e820_table.entries = entries 632 633 # Command line 634 if not cmdline: 635 cmdline = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1' 636 self.boot_osflags = fillInCmdline(mdesc, cmdline) 637 self.kernel = binary('x86_64-vmlinux-2.6.22.9') 638 return self 639 640 641def makeDualRoot(full_system, testSystem, driveSystem, dumpfile): 642 self = Root(full_system = full_system) 643 self.testsys = testSystem 644 self.drivesys = driveSystem 645 self.etherlink = EtherLink() 646 647 if hasattr(testSystem, 'realview'): 648 self.etherlink.int0 = Parent.testsys.realview.ethernet.interface 649 self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface 650 elif hasattr(testSystem, 'tsunami'): 651 self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 652 self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 653 else: 654 fatal("Don't know how to connect these system together") 655 656 if dumpfile: 657 self.etherdump = EtherDump(file=dumpfile) 658 self.etherlink.dump = Parent.etherdump 659 660 return self 661