FSConfig.py revision 11182 
1# Copyright (c) 2010-2012, 2015 ARM Limited
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3#
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13# Copyright (c) 2010-2011 Advanced Micro Devices, Inc.
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34# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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39#
40# Authors: Kevin Lim
41
42from m5.objects import *
43from Benchmarks import *
44from m5.util import *
45
46# Populate to reflect supported os types per target ISA
47os_types = { 'alpha' : [ 'linux' ],
48             'mips'  : [ 'linux' ],
49             'sparc' : [ 'linux' ],
50             'x86'   : [ 'linux' ],
51             'arm'   : [ 'linux',
52                         'android-gingerbread',
53                         'android-ics',
54                         'android-jellybean',
55                         'android-kitkat' ],
56           }
57
58class CowIdeDisk(IdeDisk):
59    image = CowDiskImage(child=RawDiskImage(read_only=True),
60                         read_only=False)
61
62    def childImage(self, ci):
63        self.image.child.image_file = ci
64
65class MemBus(SystemXBar):
66    badaddr_responder = BadAddr()
67    default = Self.badaddr_responder.pio
68
69def fillInCmdline(mdesc, template, **kwargs):
70    kwargs.setdefault('disk', mdesc.disk())
71    kwargs.setdefault('rootdev', mdesc.rootdev())
72    kwargs.setdefault('mem', mdesc.mem())
73    kwargs.setdefault('script', mdesc.script())
74    return template % kwargs
75
76def makeLinuxAlphaSystem(mem_mode, mdesc=None, ruby=False, cmdline=None):
77
78    class BaseTsunami(Tsunami):
79        ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
80        ide = IdeController(disks=[Parent.disk0, Parent.disk2],
81                            pci_func=0, pci_dev=0, pci_bus=0)
82
83    self = LinuxAlphaSystem()
84    if not mdesc:
85        # generic system
86        mdesc = SysConfig()
87    self.readfile = mdesc.script()
88
89    self.tsunami = BaseTsunami()
90
91    # Create the io bus to connect all device ports
92    self.iobus = IOXBar()
93    self.tsunami.attachIO(self.iobus)
94
95    self.tsunami.ide.pio = self.iobus.master
96    self.tsunami.ide.config = self.iobus.master
97
98    self.tsunami.ethernet.pio = self.iobus.master
99    self.tsunami.ethernet.config = self.iobus.master
100
101    if ruby:
102        # Store the dma devices for later connection to dma ruby ports.
103        # Append an underscore to dma_ports to avoid the SimObjectVector check.
104        self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma]
105    else:
106        self.membus = MemBus()
107
108        # By default the bridge responds to all addresses above the I/O
109        # base address (including the PCI config space)
110        IO_address_space_base = 0x80000000000
111        self.bridge = Bridge(delay='50ns',
112                         ranges = [AddrRange(IO_address_space_base, Addr.max)])
113        self.bridge.master = self.iobus.slave
114        self.bridge.slave = self.membus.master
115
116        self.tsunami.ide.dma = self.iobus.slave
117        self.tsunami.ethernet.dma = self.iobus.slave
118
119        self.system_port = self.membus.slave
120
121    self.mem_ranges = [AddrRange(mdesc.mem())]
122    self.disk0 = CowIdeDisk(driveID='master')
123    self.disk2 = CowIdeDisk(driveID='master')
124    self.disk0.childImage(mdesc.disk())
125    self.disk2.childImage(disk('linux-bigswap2.img'))
126    self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
127                                               read_only = True))
128    self.intrctrl = IntrControl()
129    self.mem_mode = mem_mode
130    self.terminal = Terminal()
131    self.kernel = binary('vmlinux')
132    self.pal = binary('ts_osfpal')
133    self.console = binary('console')
134    if not cmdline:
135        cmdline = 'root=/dev/hda1 console=ttyS0'
136    self.boot_osflags = fillInCmdline(mdesc, cmdline)
137
138    return self
139
140def makeSparcSystem(mem_mode, mdesc=None, cmdline=None):
141    # Constants from iob.cc and uart8250.cc
142    iob_man_addr = 0x9800000000
143    uart_pio_size = 8
144
145    class CowMmDisk(MmDisk):
146        image = CowDiskImage(child=RawDiskImage(read_only=True),
147                             read_only=False)
148
149        def childImage(self, ci):
150            self.image.child.image_file = ci
151
152    self = SparcSystem()
153    if not mdesc:
154        # generic system
155        mdesc = SysConfig()
156    self.readfile = mdesc.script()
157    self.iobus = IOXBar()
158    self.membus = MemBus()
159    self.bridge = Bridge(delay='50ns')
160    self.t1000 = T1000()
161    self.t1000.attachOnChipIO(self.membus)
162    self.t1000.attachIO(self.iobus)
163    self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'),
164                       AddrRange(Addr('2GB'), size ='256MB')]
165    self.bridge.master = self.iobus.slave
166    self.bridge.slave = self.membus.master
167    self.rom.port = self.membus.master
168    self.nvram.port = self.membus.master
169    self.hypervisor_desc.port = self.membus.master
170    self.partition_desc.port = self.membus.master
171    self.intrctrl = IntrControl()
172    self.disk0 = CowMmDisk()
173    self.disk0.childImage(disk('disk.s10hw2'))
174    self.disk0.pio = self.iobus.master
175
176    # The puart0 and hvuart are placed on the IO bus, so create ranges
177    # for them. The remaining IO range is rather fragmented, so poke
178    # holes for the iob and partition descriptors etc.
179    self.bridge.ranges = \
180        [
181        AddrRange(self.t1000.puart0.pio_addr,
182                  self.t1000.puart0.pio_addr + uart_pio_size - 1),
183        AddrRange(self.disk0.pio_addr,
184                  self.t1000.fake_jbi.pio_addr +
185                  self.t1000.fake_jbi.pio_size - 1),
186        AddrRange(self.t1000.fake_clk.pio_addr,
187                  iob_man_addr - 1),
188        AddrRange(self.t1000.fake_l2_1.pio_addr,
189                  self.t1000.fake_ssi.pio_addr +
190                  self.t1000.fake_ssi.pio_size - 1),
191        AddrRange(self.t1000.hvuart.pio_addr,
192                  self.t1000.hvuart.pio_addr + uart_pio_size - 1)
193        ]
194    self.reset_bin = binary('reset_new.bin')
195    self.hypervisor_bin = binary('q_new.bin')
196    self.openboot_bin = binary('openboot_new.bin')
197    self.nvram_bin = binary('nvram1')
198    self.hypervisor_desc_bin = binary('1up-hv.bin')
199    self.partition_desc_bin = binary('1up-md.bin')
200
201    self.system_port = self.membus.slave
202
203    return self
204
205def makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None,
206                  dtb_filename=None, bare_metal=False, cmdline=None,
207                  external_memory=""):
208    assert machine_type
209
210    if bare_metal:
211        self = ArmSystem()
212    else:
213        self = LinuxArmSystem()
214
215    if not mdesc:
216        # generic system
217        mdesc = SysConfig()
218
219    self.readfile = mdesc.script()
220    self.iobus = IOXBar()
221    self.membus = MemBus()
222    self.membus.badaddr_responder.warn_access = "warn"
223    self.bridge = Bridge(delay='50ns')
224    self.bridge.master = self.iobus.slave
225    self.bridge.slave = self.membus.master
226
227    self.mem_mode = mem_mode
228
229    if machine_type == "RealView_PBX":
230        self.realview = RealViewPBX()
231    elif machine_type == "RealView_EB":
232        self.realview = RealViewEB()
233    elif machine_type == "VExpress_EMM":
234        self.realview = VExpress_EMM()
235        if not dtb_filename:
236            dtb_filename = 'vexpress.aarch32.ll_20131205.0-gem5.%dcpu.dtb' % num_cpus
237    elif machine_type == "VExpress_EMM64":
238        self.realview = VExpress_EMM64()
239        if os.path.split(mdesc.disk())[-1] == 'linux-aarch32-ael.img':
240            print "Selected 64-bit ARM architecture, updating default disk image..."
241            mdesc.diskname = 'linaro-minimal-aarch64.img'
242        if not dtb_filename:
243            dtb_filename = 'vexpress.aarch64.20140821.dtb'
244    else:
245        print "Unknown Machine Type"
246        sys.exit(1)
247
248    self.cf0 = CowIdeDisk(driveID='master')
249    self.cf0.childImage(mdesc.disk())
250
251    # Attach any PCI devices this platform supports
252    self.realview.attachPciDevices()
253    # default to an IDE controller rather than a CF one
254    try:
255        self.realview.ide.disks = [self.cf0]
256    except:
257        self.realview.cf_ctrl.disks = [self.cf0]
258
259    self.mem_ranges = []
260    size_remain = long(Addr(mdesc.mem()))
261    for region in self.realview._mem_regions:
262        if size_remain > long(region[1]):
263            self.mem_ranges.append(AddrRange(region[0], size=region[1]))
264            size_remain = size_remain - long(region[1])
265        else:
266            self.mem_ranges.append(AddrRange(region[0], size=size_remain))
267            size_remain = 0
268            break
269        warn("Memory size specified spans more than one region. Creating" \
270             " another memory controller for that range.")
271
272    if size_remain > 0:
273        fatal("The currently selected ARM platforms doesn't support" \
274              " the amount of DRAM you've selected. Please try" \
275              " another platform")
276
277    if bare_metal:
278        # EOT character on UART will end the simulation
279        self.realview.uart.end_on_eot = True
280    else:
281        if machine_type == "VExpress_EMM64":
282            self.kernel = binary('vmlinux.aarch64.20140821')
283        elif machine_type == "VExpress_EMM":
284            self.kernel = binary('vmlinux.aarch32.ll_20131205.0-gem5')
285        else:
286            self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8')
287
288        if dtb_filename:
289            self.dtb_filename = binary(dtb_filename)
290        self.machine_type = machine_type
291        # Ensure that writes to the UART actually go out early in the boot
292        if not cmdline:
293            cmdline = 'earlyprintk=pl011,0x1c090000 console=ttyAMA0 ' + \
294                      'lpj=19988480 norandmaps rw loglevel=8 ' + \
295                      'mem=%(mem)s root=%(rootdev)s'
296
297        # When using external memory, gem5 writes the boot loader to nvmem
298        # and then SST will read from it, but SST can only get to nvmem from
299        # iobus, as gem5's membus is only used for initialization and
300        # SST doesn't use it.  Attaching nvmem to iobus solves this issue.
301        # During initialization, system_port -> membus -> iobus -> nvmem.
302        if external_memory:
303            self.realview.setupBootLoader(self.iobus,  self, binary)
304        else:
305            self.realview.setupBootLoader(self.membus, self, binary)
306        self.gic_cpu_addr = self.realview.gic.cpu_addr
307        self.flags_addr = self.realview.realview_io.pio_addr + 0x30
308
309        # This check is for users who have previously put 'android' in
310        # the disk image filename to tell the config scripts to
311        # prepare the kernel with android-specific boot options. That
312        # behavior has been replaced with a more explicit option per
313        # the error message below. The disk can have any name now and
314        # doesn't need to include 'android' substring.
315        if (os.path.split(mdesc.disk())[-1]).lower().count('android'):
316            if 'android' not in mdesc.os_type():
317                fatal("It looks like you are trying to boot an Android " \
318                      "platform.  To boot Android, you must specify " \
319                      "--os-type with an appropriate Android release on " \
320                      "the command line.")
321
322        # android-specific tweaks
323        if 'android' in mdesc.os_type():
324            # generic tweaks
325            cmdline += " init=/init"
326
327            # release-specific tweaks
328            if 'kitkat' in mdesc.os_type():
329                cmdline += " androidboot.hardware=gem5 qemu=1 qemu.gles=0 " + \
330                           "android.bootanim=0"
331
332        self.boot_osflags = fillInCmdline(mdesc, cmdline)
333
334    if external_memory:
335        # I/O traffic enters iobus
336        self.external_io = ExternalMaster(port_data="external_io",
337                                          port_type=external_memory)
338        self.external_io.port = self.iobus.slave
339
340        # Ensure iocache only receives traffic destined for (actual) memory.
341        self.iocache = ExternalSlave(port_data="iocache",
342                                     port_type=external_memory,
343                                     addr_ranges=self.mem_ranges)
344        self.iocache.port = self.iobus.master
345
346        # Let system_port get to nvmem and nothing else.
347        self.bridge.ranges = [self.realview.nvmem.range]
348
349        self.realview.attachOnChipIO(self.iobus)
350    else:
351        self.realview.attachOnChipIO(self.membus, self.bridge)
352    self.realview.attachIO(self.iobus)
353    self.intrctrl = IntrControl()
354    self.terminal = Terminal()
355    self.vncserver = VncServer()
356
357    self.system_port = self.membus.slave
358
359    return self
360
361
362def makeLinuxMipsSystem(mem_mode, mdesc=None, cmdline=None):
363    class BaseMalta(Malta):
364        ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
365        ide = IdeController(disks=[Parent.disk0, Parent.disk2],
366                            pci_func=0, pci_dev=0, pci_bus=0)
367
368    self = LinuxMipsSystem()
369    if not mdesc:
370        # generic system
371        mdesc = SysConfig()
372    self.readfile = mdesc.script()
373    self.iobus = IOXBar()
374    self.membus = MemBus()
375    self.bridge = Bridge(delay='50ns')
376    self.mem_ranges = [AddrRange('1GB')]
377    self.bridge.master = self.iobus.slave
378    self.bridge.slave = self.membus.master
379    self.disk0 = CowIdeDisk(driveID='master')
380    self.disk2 = CowIdeDisk(driveID='master')
381    self.disk0.childImage(mdesc.disk())
382    self.disk2.childImage(disk('linux-bigswap2.img'))
383    self.malta = BaseMalta()
384    self.malta.attachIO(self.iobus)
385    self.malta.ide.pio = self.iobus.master
386    self.malta.ide.config = self.iobus.master
387    self.malta.ide.dma = self.iobus.slave
388    self.malta.ethernet.pio = self.iobus.master
389    self.malta.ethernet.config = self.iobus.master
390    self.malta.ethernet.dma = self.iobus.slave
391    self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
392                                               read_only = True))
393    self.intrctrl = IntrControl()
394    self.mem_mode = mem_mode
395    self.terminal = Terminal()
396    self.kernel = binary('mips/vmlinux')
397    self.console = binary('mips/console')
398    if not cmdline:
399        cmdline = 'root=/dev/hda1 console=ttyS0'
400    self.boot_osflags = fillInCmdline(mdesc, cmdline)
401
402    self.system_port = self.membus.slave
403
404    return self
405
406def x86IOAddress(port):
407    IO_address_space_base = 0x8000000000000000
408    return IO_address_space_base + port
409
410def connectX86ClassicSystem(x86_sys, numCPUs):
411    # Constants similar to x86_traits.hh
412    IO_address_space_base = 0x8000000000000000
413    pci_config_address_space_base = 0xc000000000000000
414    interrupts_address_space_base = 0xa000000000000000
415    APIC_range_size = 1 << 12;
416
417    x86_sys.membus = MemBus()
418
419    # North Bridge
420    x86_sys.iobus = IOXBar()
421    x86_sys.bridge = Bridge(delay='50ns')
422    x86_sys.bridge.master = x86_sys.iobus.slave
423    x86_sys.bridge.slave = x86_sys.membus.master
424    # Allow the bridge to pass through:
425    #  1) kernel configured PCI device memory map address: address range
426    #     [0xC0000000, 0xFFFF0000). (The upper 64kB are reserved for m5ops.)
427    #  2) the bridge to pass through the IO APIC (two pages, already contained in 1),
428    #  3) everything in the IO address range up to the local APIC, and
429    #  4) then the entire PCI address space and beyond.
430    x86_sys.bridge.ranges = \
431        [
432        AddrRange(0xC0000000, 0xFFFF0000),
433        AddrRange(IO_address_space_base,
434                  interrupts_address_space_base - 1),
435        AddrRange(pci_config_address_space_base,
436                  Addr.max)
437        ]
438
439    # Create a bridge from the IO bus to the memory bus to allow access to
440    # the local APIC (two pages)
441    x86_sys.apicbridge = Bridge(delay='50ns')
442    x86_sys.apicbridge.slave = x86_sys.iobus.master
443    x86_sys.apicbridge.master = x86_sys.membus.slave
444    x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
445                                           interrupts_address_space_base +
446                                           numCPUs * APIC_range_size
447                                           - 1)]
448
449    # connect the io bus
450    x86_sys.pc.attachIO(x86_sys.iobus)
451
452    x86_sys.system_port = x86_sys.membus.slave
453
454def connectX86RubySystem(x86_sys):
455    # North Bridge
456    x86_sys.iobus = IOXBar()
457
458    # add the ide to the list of dma devices that later need to attach to
459    # dma controllers
460    x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma]
461    x86_sys.pc.attachIO(x86_sys.iobus, x86_sys._dma_ports)
462
463
464def makeX86System(mem_mode, numCPUs=1, mdesc=None, self=None, Ruby=False):
465    if self == None:
466        self = X86System()
467
468    if not mdesc:
469        # generic system
470        mdesc = SysConfig()
471    self.readfile = mdesc.script()
472
473    self.mem_mode = mem_mode
474
475    # Physical memory
476    # On the PC platform, the memory region 0xC0000000-0xFFFFFFFF is reserved
477    # for various devices.  Hence, if the physical memory size is greater than
478    # 3GB, we need to split it into two parts.
479    excess_mem_size = \
480        convert.toMemorySize(mdesc.mem()) - convert.toMemorySize('3GB')
481    if excess_mem_size <= 0:
482        self.mem_ranges = [AddrRange(mdesc.mem())]
483    else:
484        warn("Physical memory size specified is %s which is greater than " \
485             "3GB.  Twice the number of memory controllers would be " \
486             "created."  % (mdesc.mem()))
487
488        self.mem_ranges = [AddrRange('3GB'),
489            AddrRange(Addr('4GB'), size = excess_mem_size)]
490
491    # Platform
492    self.pc = Pc()
493
494    # Create and connect the busses required by each memory system
495    if Ruby:
496        connectX86RubySystem(self)
497    else:
498        connectX86ClassicSystem(self, numCPUs)
499
500    self.intrctrl = IntrControl()
501
502    # Disks
503    disk0 = CowIdeDisk(driveID='master')
504    disk2 = CowIdeDisk(driveID='master')
505    disk0.childImage(mdesc.disk())
506    disk2.childImage(disk('linux-bigswap2.img'))
507    self.pc.south_bridge.ide.disks = [disk0, disk2]
508
509    # Add in a Bios information structure.
510    structures = [X86SMBiosBiosInformation()]
511    self.smbios_table.structures = structures
512
513    # Set up the Intel MP table
514    base_entries = []
515    ext_entries = []
516    for i in xrange(numCPUs):
517        bp = X86IntelMPProcessor(
518                local_apic_id = i,
519                local_apic_version = 0x14,
520                enable = True,
521                bootstrap = (i == 0))
522        base_entries.append(bp)
523    io_apic = X86IntelMPIOAPIC(
524            id = numCPUs,
525            version = 0x11,
526            enable = True,
527            address = 0xfec00000)
528    self.pc.south_bridge.io_apic.apic_id = io_apic.id
529    base_entries.append(io_apic)
530    # In gem5 Pc::calcPciConfigAddr(), it required "assert(bus==0)",
531    # but linux kernel cannot config PCI device if it was not connected to PCI bus,
532    # so we fix PCI bus id to 0, and ISA bus id to 1.
533    pci_bus = X86IntelMPBus(bus_id = 0, bus_type='PCI')
534    base_entries.append(pci_bus)
535    isa_bus = X86IntelMPBus(bus_id = 1, bus_type='ISA')
536    base_entries.append(isa_bus)
537    connect_busses = X86IntelMPBusHierarchy(bus_id=1,
538            subtractive_decode=True, parent_bus=0)
539    ext_entries.append(connect_busses)
540    pci_dev4_inta = X86IntelMPIOIntAssignment(
541            interrupt_type = 'INT',
542            polarity = 'ConformPolarity',
543            trigger = 'ConformTrigger',
544            source_bus_id = 0,
545            source_bus_irq = 0 + (4 << 2),
546            dest_io_apic_id = io_apic.id,
547            dest_io_apic_intin = 16)
548    base_entries.append(pci_dev4_inta)
549    def assignISAInt(irq, apicPin):
550        assign_8259_to_apic = X86IntelMPIOIntAssignment(
551                interrupt_type = 'ExtInt',
552                polarity = 'ConformPolarity',
553                trigger = 'ConformTrigger',
554                source_bus_id = 1,
555                source_bus_irq = irq,
556                dest_io_apic_id = io_apic.id,
557                dest_io_apic_intin = 0)
558        base_entries.append(assign_8259_to_apic)
559        assign_to_apic = X86IntelMPIOIntAssignment(
560                interrupt_type = 'INT',
561                polarity = 'ConformPolarity',
562                trigger = 'ConformTrigger',
563                source_bus_id = 1,
564                source_bus_irq = irq,
565                dest_io_apic_id = io_apic.id,
566                dest_io_apic_intin = apicPin)
567        base_entries.append(assign_to_apic)
568    assignISAInt(0, 2)
569    assignISAInt(1, 1)
570    for i in range(3, 15):
571        assignISAInt(i, i)
572    self.intel_mp_table.base_entries = base_entries
573    self.intel_mp_table.ext_entries = ext_entries
574
575def makeLinuxX86System(mem_mode, numCPUs=1, mdesc=None, Ruby=False,
576                       cmdline=None):
577    self = LinuxX86System()
578
579    # Build up the x86 system and then specialize it for Linux
580    makeX86System(mem_mode, numCPUs, mdesc, self, Ruby)
581
582    # We assume below that there's at least 1MB of memory. We'll require 2
583    # just to avoid corner cases.
584    phys_mem_size = sum(map(lambda r: r.size(), self.mem_ranges))
585    assert(phys_mem_size >= 0x200000)
586    assert(len(self.mem_ranges) <= 2)
587
588    entries = \
589       [
590        # Mark the first megabyte of memory as reserved
591        X86E820Entry(addr = 0, size = '639kB', range_type = 1),
592        X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2),
593        # Mark the rest of physical memory as available
594        X86E820Entry(addr = 0x100000,
595                size = '%dB' % (self.mem_ranges[0].size() - 0x100000),
596                range_type = 1),
597        ]
598
599    # Mark [mem_size, 3GB) as reserved if memory less than 3GB, which force
600    # IO devices to be mapped to [0xC0000000, 0xFFFF0000). Requests to this
601    # specific range can pass though bridge to iobus.
602    if len(self.mem_ranges) == 1:
603        entries.append(X86E820Entry(addr = self.mem_ranges[0].size(),
604            size='%dB' % (0xC0000000 - self.mem_ranges[0].size()),
605            range_type=2))
606
607    # Reserve the last 16kB of the 32-bit address space for the m5op interface
608    entries.append(X86E820Entry(addr=0xFFFF0000, size='64kB', range_type=2))
609
610    # In case the physical memory is greater than 3GB, we split it into two
611    # parts and add a separate e820 entry for the second part.  This entry
612    # starts at 0x100000000,  which is the first address after the space
613    # reserved for devices.
614    if len(self.mem_ranges) == 2:
615        entries.append(X86E820Entry(addr = 0x100000000,
616            size = '%dB' % (self.mem_ranges[1].size()), range_type = 1))
617
618    self.e820_table.entries = entries
619
620    # Command line
621    if not cmdline:
622        cmdline = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1'
623    self.boot_osflags = fillInCmdline(mdesc, cmdline)
624    self.kernel = binary('x86_64-vmlinux-2.6.22.9')
625    return self
626
627
628def makeDualRoot(full_system, testSystem, driveSystem, dumpfile):
629    self = Root(full_system = full_system)
630    self.testsys = testSystem
631    self.drivesys = driveSystem
632    self.etherlink = EtherLink()
633
634    if hasattr(testSystem, 'realview'):
635        self.etherlink.int0 = Parent.testsys.realview.ethernet.interface
636        self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface
637    elif hasattr(testSystem, 'tsunami'):
638        self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
639        self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
640    else:
641        fatal("Don't know how to connect these system together")
642
643    if dumpfile:
644        self.etherdump = EtherDump(file=dumpfile)
645        self.etherlink.dump = Parent.etherdump
646
647    return self
648