FSConfig.py revision 10353:dfebd39c48a7
1955SN/A# Copyright (c) 2010-2012 ARM Limited 2955SN/A# All rights reserved. 311408Sandreas.sandberg@arm.com# 49812Sandreas.hansson@arm.com# The license below extends only to copyright in the software and shall 59812Sandreas.hansson@arm.com# not be construed as granting a license to any other intellectual 69812Sandreas.hansson@arm.com# property including but not limited to intellectual property relating 79812Sandreas.hansson@arm.com# to a hardware implementation of the functionality of the software 89812Sandreas.hansson@arm.com# licensed hereunder. You may use the software subject to the license 99812Sandreas.hansson@arm.com# terms below provided that you ensure that this notice is replicated 109812Sandreas.hansson@arm.com# unmodified and in its entirety in all distributions of the software, 119812Sandreas.hansson@arm.com# modified or unmodified, in source code or in binary form. 129812Sandreas.hansson@arm.com# 139812Sandreas.hansson@arm.com# Copyright (c) 2010-2011 Advanced Micro Devices, Inc. 149812Sandreas.hansson@arm.com# Copyright (c) 2006-2008 The Regents of The University of Michigan 157816Ssteve.reinhardt@amd.com# All rights reserved. 165871Snate@binkert.org# 171762SN/A# Redistribution and use in source and binary forms, with or without 18955SN/A# modification, are permitted provided that the following conditions are 19955SN/A# met: redistributions of source code must retain the above copyright 20955SN/A# notice, this list of conditions and the following disclaimer; 21955SN/A# redistributions in binary form must reproduce the above copyright 22955SN/A# notice, this list of conditions and the following disclaimer in the 23955SN/A# documentation and/or other materials provided with the distribution; 24955SN/A# neither the name of the copyright holders nor the names of its 25955SN/A# contributors may be used to endorse or promote products derived from 26955SN/A# this software without specific prior written permission. 27955SN/A# 28955SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29955SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30955SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31955SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32955SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33955SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34955SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35955SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36955SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37955SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38955SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39955SN/A# 40955SN/A# Authors: Kevin Lim 41955SN/A 422665Ssaidi@eecs.umich.edufrom m5.objects import * 432665Ssaidi@eecs.umich.edufrom Benchmarks import * 445863Snate@binkert.orgfrom m5.util import * 45955SN/A 46955SN/Aclass CowIdeDisk(IdeDisk): 47955SN/A image = CowDiskImage(child=RawDiskImage(read_only=True), 48955SN/A read_only=False) 49955SN/A 508878Ssteve.reinhardt@amd.com def childImage(self, ci): 512632Sstever@eecs.umich.edu self.image.child.image_file = ci 528878Ssteve.reinhardt@amd.com 532632Sstever@eecs.umich.educlass MemBus(CoherentBus): 54955SN/A badaddr_responder = BadAddr() 558878Ssteve.reinhardt@amd.com default = Self.badaddr_responder.pio 562632Sstever@eecs.umich.edu 572761Sstever@eecs.umich.edu 582632Sstever@eecs.umich.edudef makeLinuxAlphaSystem(mem_mode, mdesc = None, ruby = False): 592632Sstever@eecs.umich.edu 602632Sstever@eecs.umich.edu class BaseTsunami(Tsunami): 612761Sstever@eecs.umich.edu ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 622761Sstever@eecs.umich.edu ide = IdeController(disks=[Parent.disk0, Parent.disk2], 632761Sstever@eecs.umich.edu pci_func=0, pci_dev=0, pci_bus=0) 648878Ssteve.reinhardt@amd.com 658878Ssteve.reinhardt@amd.com self = LinuxAlphaSystem() 662761Sstever@eecs.umich.edu if not mdesc: 672761Sstever@eecs.umich.edu # generic system 682761Sstever@eecs.umich.edu mdesc = SysConfig() 692761Sstever@eecs.umich.edu self.readfile = mdesc.script() 702761Sstever@eecs.umich.edu 718878Ssteve.reinhardt@amd.com self.tsunami = BaseTsunami() 728878Ssteve.reinhardt@amd.com 732632Sstever@eecs.umich.edu # Create the io bus to connect all device ports 742632Sstever@eecs.umich.edu self.iobus = NoncoherentBus() 758878Ssteve.reinhardt@amd.com self.tsunami.attachIO(self.iobus) 768878Ssteve.reinhardt@amd.com 772632Sstever@eecs.umich.edu self.tsunami.ide.pio = self.iobus.master 78955SN/A self.tsunami.ide.config = self.iobus.master 79955SN/A 80955SN/A self.tsunami.ethernet.pio = self.iobus.master 815863Snate@binkert.org self.tsunami.ethernet.config = self.iobus.master 825863Snate@binkert.org 835863Snate@binkert.org if ruby: 845863Snate@binkert.org # Store the dma devices for later connection to dma ruby ports. 855863Snate@binkert.org # Append an underscore to dma_ports to avoid the SimObjectVector check. 865863Snate@binkert.org self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma] 875863Snate@binkert.org else: 885863Snate@binkert.org self.membus = MemBus() 895863Snate@binkert.org 905863Snate@binkert.org # By default the bridge responds to all addresses above the I/O 915863Snate@binkert.org # base address (including the PCI config space) 928878Ssteve.reinhardt@amd.com IO_address_space_base = 0x80000000000 935863Snate@binkert.org self.bridge = Bridge(delay='50ns', 945863Snate@binkert.org ranges = [AddrRange(IO_address_space_base, Addr.max)]) 955863Snate@binkert.org self.bridge.master = self.iobus.slave 969812Sandreas.hansson@arm.com self.bridge.slave = self.membus.master 979812Sandreas.hansson@arm.com 985863Snate@binkert.org self.tsunami.ide.dma = self.iobus.slave 999812Sandreas.hansson@arm.com self.tsunami.ethernet.dma = self.iobus.slave 1005863Snate@binkert.org 1015863Snate@binkert.org self.system_port = self.membus.slave 1025863Snate@binkert.org 1039812Sandreas.hansson@arm.com self.mem_ranges = [AddrRange(mdesc.mem())] 1049812Sandreas.hansson@arm.com self.disk0 = CowIdeDisk(driveID='master') 1055863Snate@binkert.org self.disk2 = CowIdeDisk(driveID='master') 1065863Snate@binkert.org self.disk0.childImage(mdesc.disk()) 1078878Ssteve.reinhardt@amd.com self.disk2.childImage(disk('linux-bigswap2.img')) 1085863Snate@binkert.org self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 1095863Snate@binkert.org read_only = True)) 1105863Snate@binkert.org self.intrctrl = IntrControl() 1116654Snate@binkert.org self.mem_mode = mem_mode 11210196SCurtis.Dunham@arm.com self.terminal = Terminal() 113955SN/A self.kernel = binary('vmlinux') 1145396Ssaidi@eecs.umich.edu self.pal = binary('ts_osfpal') 11511401Sandreas.sandberg@arm.com self.console = binary('console') 1165863Snate@binkert.org self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 1175863Snate@binkert.org 1184202Sbinkertn@umich.edu return self 1195863Snate@binkert.org 1205863Snate@binkert.orgdef makeSparcSystem(mem_mode, mdesc = None): 1215863Snate@binkert.org # Constants from iob.cc and uart8250.cc 1225863Snate@binkert.org iob_man_addr = 0x9800000000 123955SN/A uart_pio_size = 8 1246654Snate@binkert.org 1255273Sstever@gmail.com class CowMmDisk(MmDisk): 1265871Snate@binkert.org image = CowDiskImage(child=RawDiskImage(read_only=True), 1275273Sstever@gmail.com read_only=False) 1286655Snate@binkert.org 1298878Ssteve.reinhardt@amd.com def childImage(self, ci): 1306655Snate@binkert.org self.image.child.image_file = ci 1316655Snate@binkert.org 1329219Spower.jg@gmail.com self = SparcSystem() 1336655Snate@binkert.org if not mdesc: 1345871Snate@binkert.org # generic system 1356654Snate@binkert.org mdesc = SysConfig() 1368947Sandreas.hansson@arm.com self.readfile = mdesc.script() 1375396Ssaidi@eecs.umich.edu self.iobus = NoncoherentBus() 1388120Sgblack@eecs.umich.edu self.membus = MemBus() 1398120Sgblack@eecs.umich.edu self.bridge = Bridge(delay='50ns') 1408120Sgblack@eecs.umich.edu self.t1000 = T1000() 1418120Sgblack@eecs.umich.edu self.t1000.attachOnChipIO(self.membus) 1428120Sgblack@eecs.umich.edu self.t1000.attachIO(self.iobus) 1438120Sgblack@eecs.umich.edu self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'), 1448120Sgblack@eecs.umich.edu AddrRange(Addr('2GB'), size ='256MB')] 1458120Sgblack@eecs.umich.edu self.bridge.master = self.iobus.slave 1468879Ssteve.reinhardt@amd.com self.bridge.slave = self.membus.master 1478879Ssteve.reinhardt@amd.com self.rom.port = self.membus.master 1488879Ssteve.reinhardt@amd.com self.nvram.port = self.membus.master 1498879Ssteve.reinhardt@amd.com self.hypervisor_desc.port = self.membus.master 1508879Ssteve.reinhardt@amd.com self.partition_desc.port = self.membus.master 1518879Ssteve.reinhardt@amd.com self.intrctrl = IntrControl() 1528879Ssteve.reinhardt@amd.com self.disk0 = CowMmDisk() 1538879Ssteve.reinhardt@amd.com self.disk0.childImage(disk('disk.s10hw2')) 1548879Ssteve.reinhardt@amd.com self.disk0.pio = self.iobus.master 1558879Ssteve.reinhardt@amd.com 1568879Ssteve.reinhardt@amd.com # The puart0 and hvuart are placed on the IO bus, so create ranges 1578879Ssteve.reinhardt@amd.com # for them. The remaining IO range is rather fragmented, so poke 1588879Ssteve.reinhardt@amd.com # holes for the iob and partition descriptors etc. 1598120Sgblack@eecs.umich.edu self.bridge.ranges = \ 1608120Sgblack@eecs.umich.edu [ 1618120Sgblack@eecs.umich.edu AddrRange(self.t1000.puart0.pio_addr, 1628120Sgblack@eecs.umich.edu self.t1000.puart0.pio_addr + uart_pio_size - 1), 1638120Sgblack@eecs.umich.edu AddrRange(self.disk0.pio_addr, 1648120Sgblack@eecs.umich.edu self.t1000.fake_jbi.pio_addr + 1658120Sgblack@eecs.umich.edu self.t1000.fake_jbi.pio_size - 1), 1668120Sgblack@eecs.umich.edu AddrRange(self.t1000.fake_clk.pio_addr, 1678120Sgblack@eecs.umich.edu iob_man_addr - 1), 1688120Sgblack@eecs.umich.edu AddrRange(self.t1000.fake_l2_1.pio_addr, 1698120Sgblack@eecs.umich.edu self.t1000.fake_ssi.pio_addr + 1708120Sgblack@eecs.umich.edu self.t1000.fake_ssi.pio_size - 1), 1718120Sgblack@eecs.umich.edu AddrRange(self.t1000.hvuart.pio_addr, 1728120Sgblack@eecs.umich.edu self.t1000.hvuart.pio_addr + uart_pio_size - 1) 1738879Ssteve.reinhardt@amd.com ] 1748879Ssteve.reinhardt@amd.com self.reset_bin = binary('reset_new.bin') 1758879Ssteve.reinhardt@amd.com self.hypervisor_bin = binary('q_new.bin') 1768879Ssteve.reinhardt@amd.com self.openboot_bin = binary('openboot_new.bin') 17710458Sandreas.hansson@arm.com self.nvram_bin = binary('nvram1') 17810458Sandreas.hansson@arm.com self.hypervisor_desc_bin = binary('1up-hv.bin') 17910458Sandreas.hansson@arm.com self.partition_desc_bin = binary('1up-md.bin') 1808879Ssteve.reinhardt@amd.com 1818879Ssteve.reinhardt@amd.com self.system_port = self.membus.slave 1828879Ssteve.reinhardt@amd.com 1838879Ssteve.reinhardt@amd.com return self 1849227Sandreas.hansson@arm.com 1859227Sandreas.hansson@arm.comdef makeArmSystem(mem_mode, machine_type, mdesc = None, 1868879Ssteve.reinhardt@amd.com dtb_filename = None, bare_metal=False): 1878879Ssteve.reinhardt@amd.com assert machine_type 1888879Ssteve.reinhardt@amd.com 1898879Ssteve.reinhardt@amd.com if bare_metal: 19010453SAndrew.Bardsley@arm.com self = ArmSystem() 19110453SAndrew.Bardsley@arm.com else: 19210453SAndrew.Bardsley@arm.com self = LinuxArmSystem() 19310456SCurtis.Dunham@arm.com 19410456SCurtis.Dunham@arm.com if not mdesc: 19510456SCurtis.Dunham@arm.com # generic system 19610457Sandreas.hansson@arm.com mdesc = SysConfig() 19710457Sandreas.hansson@arm.com 19811342Sandreas.hansson@arm.com self.readfile = mdesc.script() 19911342Sandreas.hansson@arm.com self.iobus = NoncoherentBus() 2008120Sgblack@eecs.umich.edu self.membus = MemBus() 2018947Sandreas.hansson@arm.com self.membus.badaddr_responder.warn_access = "warn" 2027816Ssteve.reinhardt@amd.com self.bridge = Bridge(delay='50ns') 2035871Snate@binkert.org self.bridge.master = self.iobus.slave 2045871Snate@binkert.org self.bridge.slave = self.membus.master 2056121Snate@binkert.org 2065871Snate@binkert.org self.mem_mode = mem_mode 2075871Snate@binkert.org 2089926Sstan.czerniawski@arm.com if machine_type == "RealView_PBX": 2099926Sstan.czerniawski@arm.com self.realview = RealViewPBX() 2109119Sandreas.hansson@arm.com elif machine_type == "RealView_EB": 21110068Sandreas.hansson@arm.com self.realview = RealViewEB() 21210068Sandreas.hansson@arm.com elif machine_type == "VExpress_ELT": 213955SN/A self.realview = VExpress_ELT() 2149416SAndreas.Sandberg@ARM.com elif machine_type == "VExpress_EMM": 21511342Sandreas.hansson@arm.com self.realview = VExpress_EMM() 21611212Sjoseph.gross@amd.com elif machine_type == "VExpress_EMM64": 21711212Sjoseph.gross@amd.com self.realview = VExpress_EMM64() 21811212Sjoseph.gross@amd.com else: 21911212Sjoseph.gross@amd.com print "Unknown Machine Type" 22011212Sjoseph.gross@amd.com sys.exit(1) 2219416SAndreas.Sandberg@ARM.com 2229416SAndreas.Sandberg@ARM.com self.cf0 = CowIdeDisk(driveID='master') 2235871Snate@binkert.org self.cf0.childImage(mdesc.disk()) 22410584Sandreas.hansson@arm.com 2259416SAndreas.Sandberg@ARM.com # Attach any PCI devices this platform supports 2269416SAndreas.Sandberg@ARM.com self.realview.attachPciDevices() 2275871Snate@binkert.org # default to an IDE controller rather than a CF one 228955SN/A # assuming we've got one; EMM64 is an exception for the moment 22910671Sandreas.hansson@arm.com if machine_type != "VExpress_EMM64": 23010671Sandreas.hansson@arm.com try: 23110671Sandreas.hansson@arm.com self.realview.ide.disks = [self.cf0] 23210671Sandreas.hansson@arm.com except: 2338881Smarc.orr@gmail.com self.realview.cf_ctrl.disks = [self.cf0] 2346121Snate@binkert.org else: 2356121Snate@binkert.org self.realview.cf_ctrl.disks = [self.cf0] 2361533SN/A 2379239Sandreas.hansson@arm.com if bare_metal: 2389239Sandreas.hansson@arm.com # EOT character on UART will end the simulation 2399239Sandreas.hansson@arm.com self.realview.uart.end_on_eot = True 2409239Sandreas.hansson@arm.com self.mem_ranges = [AddrRange(self.realview.mem_start_addr, 2419239Sandreas.hansson@arm.com size = mdesc.mem())] 2429239Sandreas.hansson@arm.com else: 2439239Sandreas.hansson@arm.com if machine_type == "VExpress_EMM64": 2449239Sandreas.hansson@arm.com self.kernel = binary('vmlinux-3.14-aarch64-vexpress-emm64') 2459239Sandreas.hansson@arm.com elif machine_type == "VExpress_EMM": 2469239Sandreas.hansson@arm.com self.kernel = binary('vmlinux-3.3-arm-vexpress-emm-pcie') 2479239Sandreas.hansson@arm.com else: 2489239Sandreas.hansson@arm.com self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8') 2496655Snate@binkert.org 2506655Snate@binkert.org if dtb_filename: 2516655Snate@binkert.org self.dtb_filename = binary(dtb_filename) 2526655Snate@binkert.org self.machine_type = machine_type 2535871Snate@binkert.org if convert.toMemorySize(mdesc.mem()) > int(self.realview.max_mem_size): 2545871Snate@binkert.org print "The currently selected ARM platforms doesn't support" 2555863Snate@binkert.org print " the amount of DRAM you've selected. Please try" 2565871Snate@binkert.org print " another platform" 2578878Ssteve.reinhardt@amd.com sys.exit(1) 2585871Snate@binkert.org 2595871Snate@binkert.org # Ensure that writes to the UART actually go out early in the boot 2605871Snate@binkert.org boot_flags = 'earlyprintk=pl011,0x1c090000 console=ttyAMA0 ' + \ 2615863Snate@binkert.org 'lpj=19988480 norandmaps rw loglevel=8 ' + \ 2626121Snate@binkert.org 'mem=%s root=/dev/sda1' % mdesc.mem() 2635863Snate@binkert.org 26411408Sandreas.sandberg@arm.com self.mem_ranges = [AddrRange(self.realview.mem_start_addr, 26511408Sandreas.sandberg@arm.com size = mdesc.mem())] 2668336Ssteve.reinhardt@amd.com self.realview.setupBootLoader(self.membus, self, binary) 26711469SCurtis.Dunham@arm.com self.gic_cpu_addr = self.realview.gic.cpu_addr 26811469SCurtis.Dunham@arm.com self.flags_addr = self.realview.realview_io.pio_addr + 0x30 2698336Ssteve.reinhardt@amd.com 2704678Snate@binkert.org if mdesc.disk().lower().count('android'): 27111887Sandreas.sandberg@arm.com boot_flags += " init=/init " 27211887Sandreas.sandberg@arm.com self.boot_osflags = boot_flags 27311887Sandreas.sandberg@arm.com self.realview.attachOnChipIO(self.membus, self.bridge) 27411887Sandreas.sandberg@arm.com self.realview.attachIO(self.iobus) 27511887Sandreas.sandberg@arm.com self.intrctrl = IntrControl() 27611887Sandreas.sandberg@arm.com self.terminal = Terminal() 27711887Sandreas.sandberg@arm.com self.vncserver = VncServer() 27811887Sandreas.sandberg@arm.com 27911887Sandreas.sandberg@arm.com self.system_port = self.membus.slave 28011887Sandreas.sandberg@arm.com 28111887Sandreas.sandberg@arm.com return self 28211408Sandreas.sandberg@arm.com 28311401Sandreas.sandberg@arm.com 28411401Sandreas.sandberg@arm.comdef makeLinuxMipsSystem(mem_mode, mdesc = None): 28511401Sandreas.sandberg@arm.com class BaseMalta(Malta): 28611401Sandreas.sandberg@arm.com ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 28711401Sandreas.sandberg@arm.com ide = IdeController(disks=[Parent.disk0, Parent.disk2], 28811401Sandreas.sandberg@arm.com pci_func=0, pci_dev=0, pci_bus=0) 2898336Ssteve.reinhardt@amd.com 2908336Ssteve.reinhardt@amd.com self = LinuxMipsSystem() 2918336Ssteve.reinhardt@amd.com if not mdesc: 2924678Snate@binkert.org # generic system 29311401Sandreas.sandberg@arm.com mdesc = SysConfig() 2944678Snate@binkert.org self.readfile = mdesc.script() 2954678Snate@binkert.org self.iobus = NoncoherentBus() 29611401Sandreas.sandberg@arm.com self.membus = MemBus() 29711401Sandreas.sandberg@arm.com self.bridge = Bridge(delay='50ns') 2988336Ssteve.reinhardt@amd.com self.mem_ranges = [AddrRange('1GB')] 2994678Snate@binkert.org self.bridge.master = self.iobus.slave 3008336Ssteve.reinhardt@amd.com self.bridge.slave = self.membus.master 3018336Ssteve.reinhardt@amd.com self.disk0 = CowIdeDisk(driveID='master') 3028336Ssteve.reinhardt@amd.com self.disk2 = CowIdeDisk(driveID='master') 3038336Ssteve.reinhardt@amd.com self.disk0.childImage(mdesc.disk()) 3048336Ssteve.reinhardt@amd.com self.disk2.childImage(disk('linux-bigswap2.img')) 3058336Ssteve.reinhardt@amd.com self.malta = BaseMalta() 3065871Snate@binkert.org self.malta.attachIO(self.iobus) 3075871Snate@binkert.org self.malta.ide.pio = self.iobus.master 3088336Ssteve.reinhardt@amd.com self.malta.ide.config = self.iobus.master 30911408Sandreas.sandberg@arm.com self.malta.ide.dma = self.iobus.slave 31011408Sandreas.sandberg@arm.com self.malta.ethernet.pio = self.iobus.master 31111408Sandreas.sandberg@arm.com self.malta.ethernet.config = self.iobus.master 31211408Sandreas.sandberg@arm.com self.malta.ethernet.dma = self.iobus.slave 31311408Sandreas.sandberg@arm.com self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 31411408Sandreas.sandberg@arm.com read_only = True)) 31511408Sandreas.sandberg@arm.com self.intrctrl = IntrControl() 3168336Ssteve.reinhardt@amd.com self.mem_mode = mem_mode 31711401Sandreas.sandberg@arm.com self.terminal = Terminal() 31811401Sandreas.sandberg@arm.com self.kernel = binary('mips/vmlinux') 31911401Sandreas.sandberg@arm.com self.console = binary('mips/console') 3205871Snate@binkert.org self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 3218336Ssteve.reinhardt@amd.com 3228336Ssteve.reinhardt@amd.com self.system_port = self.membus.slave 32311401Sandreas.sandberg@arm.com 32411401Sandreas.sandberg@arm.com return self 32511401Sandreas.sandberg@arm.com 32611401Sandreas.sandberg@arm.comdef x86IOAddress(port): 32711401Sandreas.sandberg@arm.com IO_address_space_base = 0x8000000000000000 3284678Snate@binkert.org return IO_address_space_base + port 3295871Snate@binkert.org 3304678Snate@binkert.orgdef connectX86ClassicSystem(x86_sys, numCPUs): 33111401Sandreas.sandberg@arm.com # Constants similar to x86_traits.hh 33211401Sandreas.sandberg@arm.com IO_address_space_base = 0x8000000000000000 33311401Sandreas.sandberg@arm.com pci_config_address_space_base = 0xc000000000000000 33411401Sandreas.sandberg@arm.com interrupts_address_space_base = 0xa000000000000000 33511401Sandreas.sandberg@arm.com APIC_range_size = 1 << 12; 33611401Sandreas.sandberg@arm.com 33711401Sandreas.sandberg@arm.com x86_sys.membus = MemBus() 33811401Sandreas.sandberg@arm.com 33911401Sandreas.sandberg@arm.com # North Bridge 34011401Sandreas.sandberg@arm.com x86_sys.iobus = NoncoherentBus() 34111401Sandreas.sandberg@arm.com x86_sys.bridge = Bridge(delay='50ns') 34211401Sandreas.sandberg@arm.com x86_sys.bridge.master = x86_sys.iobus.slave 34311450Sandreas.sandberg@arm.com x86_sys.bridge.slave = x86_sys.membus.master 34411450Sandreas.sandberg@arm.com # Allow the bridge to pass through the IO APIC (two pages), 34511450Sandreas.sandberg@arm.com # everything in the IO address range up to the local APIC, and 34611450Sandreas.sandberg@arm.com # then the entire PCI address space and beyond 34711450Sandreas.sandberg@arm.com x86_sys.bridge.ranges = \ 34811450Sandreas.sandberg@arm.com [ 34911450Sandreas.sandberg@arm.com AddrRange(x86_sys.pc.south_bridge.io_apic.pio_addr, 35011450Sandreas.sandberg@arm.com x86_sys.pc.south_bridge.io_apic.pio_addr + 35111450Sandreas.sandberg@arm.com APIC_range_size - 1), 35211450Sandreas.sandberg@arm.com AddrRange(IO_address_space_base, 35311450Sandreas.sandberg@arm.com interrupts_address_space_base - 1), 35411401Sandreas.sandberg@arm.com AddrRange(pci_config_address_space_base, 35511450Sandreas.sandberg@arm.com Addr.max) 35611450Sandreas.sandberg@arm.com ] 35711450Sandreas.sandberg@arm.com 35811401Sandreas.sandberg@arm.com # Create a bridge from the IO bus to the memory bus to allow access to 35911450Sandreas.sandberg@arm.com # the local APIC (two pages) 36011401Sandreas.sandberg@arm.com x86_sys.apicbridge = Bridge(delay='50ns') 3618336Ssteve.reinhardt@amd.com x86_sys.apicbridge.slave = x86_sys.iobus.master 3628336Ssteve.reinhardt@amd.com x86_sys.apicbridge.master = x86_sys.membus.slave 3638336Ssteve.reinhardt@amd.com x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base, 3648336Ssteve.reinhardt@amd.com interrupts_address_space_base + 3658336Ssteve.reinhardt@amd.com numCPUs * APIC_range_size 3668336Ssteve.reinhardt@amd.com - 1)] 3678336Ssteve.reinhardt@amd.com 3688336Ssteve.reinhardt@amd.com # connect the io bus 3698336Ssteve.reinhardt@amd.com x86_sys.pc.attachIO(x86_sys.iobus) 3708336Ssteve.reinhardt@amd.com 37111401Sandreas.sandberg@arm.com x86_sys.system_port = x86_sys.membus.slave 37211401Sandreas.sandberg@arm.com 3738336Ssteve.reinhardt@amd.comdef connectX86RubySystem(x86_sys): 3748336Ssteve.reinhardt@amd.com # North Bridge 3758336Ssteve.reinhardt@amd.com x86_sys.iobus = NoncoherentBus() 3765871Snate@binkert.org 37711476Sandreas.sandberg@arm.com # add the ide to the list of dma devices that later need to attach to 37811476Sandreas.sandberg@arm.com # dma controllers 37911476Sandreas.sandberg@arm.com x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma] 38011476Sandreas.sandberg@arm.com x86_sys.pc.attachIO(x86_sys.iobus, x86_sys._dma_ports) 38111476Sandreas.sandberg@arm.com 38211476Sandreas.sandberg@arm.com 38311476Sandreas.sandberg@arm.comdef makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None, 38411476Sandreas.sandberg@arm.com Ruby = False): 38511476Sandreas.sandberg@arm.com if self == None: 38611887Sandreas.sandberg@arm.com self = X86System() 38711887Sandreas.sandberg@arm.com 38811887Sandreas.sandberg@arm.com if not mdesc: 38911408Sandreas.sandberg@arm.com # generic system 39011887Sandreas.sandberg@arm.com mdesc = SysConfig() 39111887Sandreas.sandberg@arm.com self.readfile = mdesc.script() 39211887Sandreas.sandberg@arm.com 39311887Sandreas.sandberg@arm.com self.mem_mode = mem_mode 39411887Sandreas.sandberg@arm.com 39511887Sandreas.sandberg@arm.com # Physical memory 39611926Sgabeblack@google.com # On the PC platform, the memory region 0xC0000000-0xFFFFFFFF is reserved 39711926Sgabeblack@google.com # for various devices. Hence, if the physical memory size is greater than 39811926Sgabeblack@google.com # 3GB, we need to split it into two parts. 39911926Sgabeblack@google.com excess_mem_size = \ 40011887Sandreas.sandberg@arm.com convert.toMemorySize(mdesc.mem()) - convert.toMemorySize('3GB') 40111887Sandreas.sandberg@arm.com if excess_mem_size <= 0: 40211944Sandreas.sandberg@arm.com self.mem_ranges = [AddrRange(mdesc.mem())] 40311887Sandreas.sandberg@arm.com else: 40411927Sgabeblack@google.com warn("Physical memory size specified is %s which is greater than " \ 40511927Sgabeblack@google.com "3GB. Twice the number of memory controllers would be " \ 40611927Sgabeblack@google.com "created." % (mdesc.mem())) 40711927Sgabeblack@google.com 40811927Sgabeblack@google.com self.mem_ranges = [AddrRange('3GB'), 40911927Sgabeblack@google.com AddrRange(Addr('4GB'), size = excess_mem_size)] 41011887Sandreas.sandberg@arm.com 41111928Sgabeblack@google.com # Platform 41211928Sgabeblack@google.com self.pc = Pc() 41311887Sandreas.sandberg@arm.com 41411887Sandreas.sandberg@arm.com # Create and connect the busses required by each memory system 41511887Sandreas.sandberg@arm.com if Ruby: 41611887Sandreas.sandberg@arm.com connectX86RubySystem(self) 41711887Sandreas.sandberg@arm.com else: 41811887Sandreas.sandberg@arm.com connectX86ClassicSystem(self, numCPUs) 41911887Sandreas.sandberg@arm.com 42011887Sandreas.sandberg@arm.com self.intrctrl = IntrControl() 42111887Sandreas.sandberg@arm.com 42211887Sandreas.sandberg@arm.com # Disks 42311476Sandreas.sandberg@arm.com disk0 = CowIdeDisk(driveID='master') 42411476Sandreas.sandberg@arm.com disk2 = CowIdeDisk(driveID='master') 42511408Sandreas.sandberg@arm.com disk0.childImage(mdesc.disk()) 42611408Sandreas.sandberg@arm.com disk2.childImage(disk('linux-bigswap2.img')) 42711408Sandreas.sandberg@arm.com self.pc.south_bridge.ide.disks = [disk0, disk2] 42811408Sandreas.sandberg@arm.com 42911408Sandreas.sandberg@arm.com # Add in a Bios information structure. 43011408Sandreas.sandberg@arm.com structures = [X86SMBiosBiosInformation()] 43111408Sandreas.sandberg@arm.com self.smbios_table.structures = structures 43211887Sandreas.sandberg@arm.com 43311887Sandreas.sandberg@arm.com # Set up the Intel MP table 43411476Sandreas.sandberg@arm.com base_entries = [] 43511887Sandreas.sandberg@arm.com ext_entries = [] 43611887Sandreas.sandberg@arm.com for i in xrange(numCPUs): 43711476Sandreas.sandberg@arm.com bp = X86IntelMPProcessor( 43811476Sandreas.sandberg@arm.com local_apic_id = i, 43911476Sandreas.sandberg@arm.com local_apic_version = 0x14, 44011476Sandreas.sandberg@arm.com enable = True, 4416121Snate@binkert.org bootstrap = (i == 0)) 442955SN/A base_entries.append(bp) 443955SN/A io_apic = X86IntelMPIOAPIC( 4442632Sstever@eecs.umich.edu id = numCPUs, 4452632Sstever@eecs.umich.edu version = 0x11, 446955SN/A enable = True, 447955SN/A address = 0xfec00000) 448955SN/A self.pc.south_bridge.io_apic.apic_id = io_apic.id 449955SN/A base_entries.append(io_apic) 4508878Ssteve.reinhardt@amd.com isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA') 451955SN/A base_entries.append(isa_bus) 4522632Sstever@eecs.umich.edu pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI') 4532632Sstever@eecs.umich.edu base_entries.append(pci_bus) 4542632Sstever@eecs.umich.edu connect_busses = X86IntelMPBusHierarchy(bus_id=0, 4552632Sstever@eecs.umich.edu subtractive_decode=True, parent_bus=1) 4562632Sstever@eecs.umich.edu ext_entries.append(connect_busses) 4572632Sstever@eecs.umich.edu pci_dev4_inta = X86IntelMPIOIntAssignment( 4582632Sstever@eecs.umich.edu interrupt_type = 'INT', 4598268Ssteve.reinhardt@amd.com polarity = 'ConformPolarity', 4608268Ssteve.reinhardt@amd.com trigger = 'ConformTrigger', 4618268Ssteve.reinhardt@amd.com source_bus_id = 1, 4628268Ssteve.reinhardt@amd.com source_bus_irq = 0 + (4 << 2), 4638268Ssteve.reinhardt@amd.com dest_io_apic_id = io_apic.id, 4648268Ssteve.reinhardt@amd.com dest_io_apic_intin = 16) 4658268Ssteve.reinhardt@amd.com base_entries.append(pci_dev4_inta) 4662632Sstever@eecs.umich.edu def assignISAInt(irq, apicPin): 4672632Sstever@eecs.umich.edu assign_8259_to_apic = X86IntelMPIOIntAssignment( 4682632Sstever@eecs.umich.edu interrupt_type = 'ExtInt', 4692632Sstever@eecs.umich.edu polarity = 'ConformPolarity', 4708268Ssteve.reinhardt@amd.com trigger = 'ConformTrigger', 4712632Sstever@eecs.umich.edu source_bus_id = 0, 4728268Ssteve.reinhardt@amd.com source_bus_irq = irq, 4738268Ssteve.reinhardt@amd.com dest_io_apic_id = io_apic.id, 4748268Ssteve.reinhardt@amd.com dest_io_apic_intin = 0) 4758268Ssteve.reinhardt@amd.com base_entries.append(assign_8259_to_apic) 4763718Sstever@eecs.umich.edu assign_to_apic = X86IntelMPIOIntAssignment( 4772634Sstever@eecs.umich.edu interrupt_type = 'INT', 4782634Sstever@eecs.umich.edu polarity = 'ConformPolarity', 4795863Snate@binkert.org trigger = 'ConformTrigger', 4802638Sstever@eecs.umich.edu source_bus_id = 0, 4818268Ssteve.reinhardt@amd.com source_bus_irq = irq, 4822632Sstever@eecs.umich.edu dest_io_apic_id = io_apic.id, 4832632Sstever@eecs.umich.edu dest_io_apic_intin = apicPin) 4842632Sstever@eecs.umich.edu base_entries.append(assign_to_apic) 4852632Sstever@eecs.umich.edu assignISAInt(0, 2) 4862632Sstever@eecs.umich.edu assignISAInt(1, 1) 4871858SN/A for i in range(3, 15): 4883716Sstever@eecs.umich.edu assignISAInt(i, i) 4892638Sstever@eecs.umich.edu self.intel_mp_table.base_entries = base_entries 4902638Sstever@eecs.umich.edu self.intel_mp_table.ext_entries = ext_entries 4912638Sstever@eecs.umich.edu 4922638Sstever@eecs.umich.edudef makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None, 4932638Sstever@eecs.umich.edu Ruby = False): 4942638Sstever@eecs.umich.edu self = LinuxX86System() 4952638Sstever@eecs.umich.edu 4965863Snate@binkert.org # Build up the x86 system and then specialize it for Linux 4975863Snate@binkert.org makeX86System(mem_mode, numCPUs, mdesc, self, Ruby) 4985863Snate@binkert.org 499955SN/A # We assume below that there's at least 1MB of memory. We'll require 2 5005341Sstever@gmail.com # just to avoid corner cases. 5015341Sstever@gmail.com phys_mem_size = sum(map(lambda r: r.size(), self.mem_ranges)) 5025863Snate@binkert.org assert(phys_mem_size >= 0x200000) 5037756SAli.Saidi@ARM.com assert(len(self.mem_ranges) <= 2) 5045341Sstever@gmail.com 5056121Snate@binkert.org entries = \ 5064494Ssaidi@eecs.umich.edu [ 5076121Snate@binkert.org # Mark the first megabyte of memory as reserved 5081105SN/A X86E820Entry(addr = 0, size = '639kB', range_type = 1), 5092667Sstever@eecs.umich.edu X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2), 5102667Sstever@eecs.umich.edu # Mark the rest of physical memory as available 5112667Sstever@eecs.umich.edu X86E820Entry(addr = 0x100000, 5122667Sstever@eecs.umich.edu size = '%dB' % (self.mem_ranges[0].size() - 0x100000), 5136121Snate@binkert.org range_type = 1), 5142667Sstever@eecs.umich.edu # Reserve the last 16kB of the 32-bit address space for the 5155341Sstever@gmail.com # m5op interface 5165863Snate@binkert.org X86E820Entry(addr=0xFFFF0000, size='64kB', range_type=2), 5175341Sstever@gmail.com ] 5185341Sstever@gmail.com 5195341Sstever@gmail.com # In case the physical memory is greater than 3GB, we split it into two 5208120Sgblack@eecs.umich.edu # parts and add a separate e820 entry for the second part. This entry 5215341Sstever@gmail.com # starts at 0x100000000, which is the first address after the space 5228120Sgblack@eecs.umich.edu # reserved for devices. 5235341Sstever@gmail.com if len(self.mem_ranges) == 2: 5248120Sgblack@eecs.umich.edu entries.append(X86E820Entry(addr = 0x100000000, 5256121Snate@binkert.org size = '%dB' % (self.mem_ranges[1].size()), range_type = 1)) 5266121Snate@binkert.org 5278980Ssteve.reinhardt@amd.com self.e820_table.entries = entries 5289396Sandreas.hansson@arm.com 5295397Ssaidi@eecs.umich.edu # Command line 5305397Ssaidi@eecs.umich.edu self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \ 5317727SAli.Saidi@ARM.com 'root=/dev/hda1' 5328268Ssteve.reinhardt@amd.com self.kernel = binary('x86_64-vmlinux-2.6.22.9') 5336168Snate@binkert.org return self 5345341Sstever@gmail.com 5358120Sgblack@eecs.umich.edu 5368120Sgblack@eecs.umich.edudef makeDualRoot(full_system, testSystem, driveSystem, dumpfile): 5378120Sgblack@eecs.umich.edu self = Root(full_system = full_system) 5386814Sgblack@eecs.umich.edu self.testsys = testSystem 5395863Snate@binkert.org self.drivesys = driveSystem 5408120Sgblack@eecs.umich.edu self.etherlink = EtherLink() 5415341Sstever@gmail.com 5425863Snate@binkert.org if hasattr(testSystem, 'realview'): 5438268Ssteve.reinhardt@amd.com self.etherlink.int0 = Parent.testsys.realview.ethernet.interface 5446121Snate@binkert.org self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface 5456121Snate@binkert.org elif hasattr(testSystem, 'tsunami'): 5468268Ssteve.reinhardt@amd.com self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 5475742Snate@binkert.org self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 5485742Snate@binkert.org else: 5495341Sstever@gmail.com fatal("Don't know how to connect these system together") 5505742Snate@binkert.org 5515742Snate@binkert.org if dumpfile: 5525341Sstever@gmail.com self.etherdump = EtherDump(file=dumpfile) 5536017Snate@binkert.org self.etherlink.dump = Parent.etherdump 5546121Snate@binkert.org 5556017Snate@binkert.org return self 5567816Ssteve.reinhardt@amd.com