FSConfig.py revision 10118:5e1f04b4d5e4 
1# Copyright (c) 2010-2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
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11# modified or unmodified, in source code or in binary form.
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13# Copyright (c) 2010-2011 Advanced Micro Devices, Inc.
14# Copyright (c) 2006-2008 The Regents of The University of Michigan
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34# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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39#
40# Authors: Kevin Lim
41
42from m5.objects import *
43from Benchmarks import *
44from m5.util import *
45
46class CowIdeDisk(IdeDisk):
47    image = CowDiskImage(child=RawDiskImage(read_only=True),
48                         read_only=False)
49
50    def childImage(self, ci):
51        self.image.child.image_file = ci
52
53class MemBus(CoherentBus):
54    badaddr_responder = BadAddr()
55    default = Self.badaddr_responder.pio
56
57
58def makeLinuxAlphaSystem(mem_mode, mdesc = None, ruby = False):
59
60    class BaseTsunami(Tsunami):
61        ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
62        ide = IdeController(disks=[Parent.disk0, Parent.disk2],
63                            pci_func=0, pci_dev=0, pci_bus=0)
64
65    self = LinuxAlphaSystem()
66    if not mdesc:
67        # generic system
68        mdesc = SysConfig()
69    self.readfile = mdesc.script()
70
71    self.tsunami = BaseTsunami()
72
73    # Create the io bus to connect all device ports
74    self.iobus = NoncoherentBus()
75    self.tsunami.attachIO(self.iobus)
76
77    self.tsunami.ide.pio = self.iobus.master
78    self.tsunami.ide.config = self.iobus.master
79
80    self.tsunami.ethernet.pio = self.iobus.master
81    self.tsunami.ethernet.config = self.iobus.master
82
83    if ruby:
84        # Store the dma devices for later connection to dma ruby ports.
85        # Append an underscore to dma_ports to avoid the SimObjectVector check.
86        self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma]
87    else:
88        self.membus = MemBus()
89
90        # By default the bridge responds to all addresses above the I/O
91        # base address (including the PCI config space)
92        IO_address_space_base = 0x80000000000
93        self.bridge = Bridge(delay='50ns',
94                         ranges = [AddrRange(IO_address_space_base, Addr.max)])
95        self.bridge.master = self.iobus.slave
96        self.bridge.slave = self.membus.master
97
98        self.tsunami.ide.dma = self.iobus.slave
99        self.tsunami.ethernet.dma = self.iobus.slave
100
101        self.system_port = self.membus.slave
102
103    self.mem_ranges = [AddrRange(mdesc.mem())]
104    self.disk0 = CowIdeDisk(driveID='master')
105    self.disk2 = CowIdeDisk(driveID='master')
106    self.disk0.childImage(mdesc.disk())
107    self.disk2.childImage(disk('linux-bigswap2.img'))
108    self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
109                                               read_only = True))
110    self.intrctrl = IntrControl()
111    self.mem_mode = mem_mode
112    self.terminal = Terminal()
113    self.kernel = binary('vmlinux')
114    self.pal = binary('ts_osfpal')
115    self.console = binary('console')
116    self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
117
118    return self
119
120def makeSparcSystem(mem_mode, mdesc = None):
121    # Constants from iob.cc and uart8250.cc
122    iob_man_addr = 0x9800000000
123    uart_pio_size = 8
124
125    class CowMmDisk(MmDisk):
126        image = CowDiskImage(child=RawDiskImage(read_only=True),
127                             read_only=False)
128
129        def childImage(self, ci):
130            self.image.child.image_file = ci
131
132    self = SparcSystem()
133    if not mdesc:
134        # generic system
135        mdesc = SysConfig()
136    self.readfile = mdesc.script()
137    self.iobus = NoncoherentBus()
138    self.membus = MemBus()
139    self.bridge = Bridge(delay='50ns')
140    self.t1000 = T1000()
141    self.t1000.attachOnChipIO(self.membus)
142    self.t1000.attachIO(self.iobus)
143    self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'),
144                       AddrRange(Addr('2GB'), size ='256MB')]
145    self.bridge.master = self.iobus.slave
146    self.bridge.slave = self.membus.master
147    self.rom.port = self.membus.master
148    self.nvram.port = self.membus.master
149    self.hypervisor_desc.port = self.membus.master
150    self.partition_desc.port = self.membus.master
151    self.intrctrl = IntrControl()
152    self.disk0 = CowMmDisk()
153    self.disk0.childImage(disk('disk.s10hw2'))
154    self.disk0.pio = self.iobus.master
155
156    # The puart0 and hvuart are placed on the IO bus, so create ranges
157    # for them. The remaining IO range is rather fragmented, so poke
158    # holes for the iob and partition descriptors etc.
159    self.bridge.ranges = \
160        [
161        AddrRange(self.t1000.puart0.pio_addr,
162                  self.t1000.puart0.pio_addr + uart_pio_size - 1),
163        AddrRange(self.disk0.pio_addr,
164                  self.t1000.fake_jbi.pio_addr +
165                  self.t1000.fake_jbi.pio_size - 1),
166        AddrRange(self.t1000.fake_clk.pio_addr,
167                  iob_man_addr - 1),
168        AddrRange(self.t1000.fake_l2_1.pio_addr,
169                  self.t1000.fake_ssi.pio_addr +
170                  self.t1000.fake_ssi.pio_size - 1),
171        AddrRange(self.t1000.hvuart.pio_addr,
172                  self.t1000.hvuart.pio_addr + uart_pio_size - 1)
173        ]
174    self.reset_bin = binary('reset_new.bin')
175    self.hypervisor_bin = binary('q_new.bin')
176    self.openboot_bin = binary('openboot_new.bin')
177    self.nvram_bin = binary('nvram1')
178    self.hypervisor_desc_bin = binary('1up-hv.bin')
179    self.partition_desc_bin = binary('1up-md.bin')
180
181    self.system_port = self.membus.slave
182
183    return self
184
185def makeArmSystem(mem_mode, machine_type, mdesc = None,
186                  dtb_filename = None, bare_metal=False):
187    assert machine_type
188
189    if bare_metal:
190        self = ArmSystem()
191    else:
192        self = LinuxArmSystem()
193
194    if not mdesc:
195        # generic system
196        mdesc = SysConfig()
197
198    self.readfile = mdesc.script()
199    self.iobus = NoncoherentBus()
200    self.membus = MemBus()
201    self.membus.badaddr_responder.warn_access = "warn"
202    self.bridge = Bridge(delay='50ns')
203    self.bridge.master = self.iobus.slave
204    self.bridge.slave = self.membus.master
205
206    self.mem_mode = mem_mode
207
208    if machine_type == "RealView_PBX":
209        self.realview = RealViewPBX()
210    elif machine_type == "RealView_EB":
211        self.realview = RealViewEB()
212    elif machine_type == "VExpress_ELT":
213        self.realview = VExpress_ELT()
214    elif machine_type == "VExpress_EMM":
215        self.realview = VExpress_EMM()
216    elif machine_type == "VExpress_EMM64":
217        self.realview = VExpress_EMM64()
218    else:
219        print "Unknown Machine Type"
220        sys.exit(1)
221
222    self.cf0 = CowIdeDisk(driveID='master')
223    self.cf0.childImage(mdesc.disk())
224    # default to an IDE controller rather than a CF one
225    # assuming we've got one; EMM64 is an exception for the moment
226    if machine_type != "VExpress_EMM64":
227        try:
228            self.realview.ide.disks = [self.cf0]
229        except:
230            self.realview.cf_ctrl.disks = [self.cf0]
231    else:
232        self.realview.cf_ctrl.disks = [self.cf0]
233
234    if bare_metal:
235        # EOT character on UART will end the simulation
236        self.realview.uart.end_on_eot = True
237        self.mem_ranges = [AddrRange(self.realview.mem_start_addr,
238                                     size = mdesc.mem())]
239    else:
240        self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8')
241        if dtb_filename:
242            self.dtb_filename = binary(dtb_filename)
243        self.machine_type = machine_type
244        if convert.toMemorySize(mdesc.mem()) > int(self.realview.max_mem_size):
245            print "The currently selected ARM platforms doesn't support"
246            print " the amount of DRAM you've selected. Please try"
247            print " another platform"
248            sys.exit(1)
249
250        # Ensure that writes to the UART actually go out early in the boot
251        boot_flags = 'earlyprintk=pl011,0x1c090000 console=ttyAMA0 ' + \
252                     'lpj=19988480 norandmaps rw loglevel=8 ' + \
253                     'mem=%s root=/dev/sda1' % mdesc.mem()
254
255        self.mem_ranges = [AddrRange(self.realview.mem_start_addr,
256                                     size = mdesc.mem())]
257        self.realview.setupBootLoader(self.membus, self, binary)
258        self.gic_cpu_addr = self.realview.gic.cpu_addr
259        self.flags_addr = self.realview.realview_io.pio_addr + 0x30
260
261        if mdesc.disk().lower().count('android'):
262            boot_flags += " init=/init "
263        self.boot_osflags = boot_flags
264    self.realview.attachOnChipIO(self.membus, self.bridge)
265    self.realview.attachIO(self.iobus)
266    self.intrctrl = IntrControl()
267    self.terminal = Terminal()
268    self.vncserver = VncServer()
269
270    self.system_port = self.membus.slave
271
272    return self
273
274
275def makeLinuxMipsSystem(mem_mode, mdesc = None):
276    class BaseMalta(Malta):
277        ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
278        ide = IdeController(disks=[Parent.disk0, Parent.disk2],
279                            pci_func=0, pci_dev=0, pci_bus=0)
280
281    self = LinuxMipsSystem()
282    if not mdesc:
283        # generic system
284        mdesc = SysConfig()
285    self.readfile = mdesc.script()
286    self.iobus = NoncoherentBus()
287    self.membus = MemBus()
288    self.bridge = Bridge(delay='50ns')
289    self.mem_ranges = [AddrRange('1GB')]
290    self.bridge.master = self.iobus.slave
291    self.bridge.slave = self.membus.master
292    self.disk0 = CowIdeDisk(driveID='master')
293    self.disk2 = CowIdeDisk(driveID='master')
294    self.disk0.childImage(mdesc.disk())
295    self.disk2.childImage(disk('linux-bigswap2.img'))
296    self.malta = BaseMalta()
297    self.malta.attachIO(self.iobus)
298    self.malta.ide.pio = self.iobus.master
299    self.malta.ide.config = self.iobus.master
300    self.malta.ide.dma = self.iobus.slave
301    self.malta.ethernet.pio = self.iobus.master
302    self.malta.ethernet.config = self.iobus.master
303    self.malta.ethernet.dma = self.iobus.slave
304    self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
305                                               read_only = True))
306    self.intrctrl = IntrControl()
307    self.mem_mode = mem_mode
308    self.terminal = Terminal()
309    self.kernel = binary('mips/vmlinux')
310    self.console = binary('mips/console')
311    self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
312
313    self.system_port = self.membus.slave
314
315    return self
316
317def x86IOAddress(port):
318    IO_address_space_base = 0x8000000000000000
319    return IO_address_space_base + port
320
321def connectX86ClassicSystem(x86_sys, numCPUs):
322    # Constants similar to x86_traits.hh
323    IO_address_space_base = 0x8000000000000000
324    pci_config_address_space_base = 0xc000000000000000
325    interrupts_address_space_base = 0xa000000000000000
326    APIC_range_size = 1 << 12;
327
328    x86_sys.membus = MemBus()
329
330    # North Bridge
331    x86_sys.iobus = NoncoherentBus()
332    x86_sys.bridge = Bridge(delay='50ns')
333    x86_sys.bridge.master = x86_sys.iobus.slave
334    x86_sys.bridge.slave = x86_sys.membus.master
335    # Allow the bridge to pass through the IO APIC (two pages),
336    # everything in the IO address range up to the local APIC, and
337    # then the entire PCI address space and beyond
338    x86_sys.bridge.ranges = \
339        [
340        AddrRange(x86_sys.pc.south_bridge.io_apic.pio_addr,
341                  x86_sys.pc.south_bridge.io_apic.pio_addr +
342                  APIC_range_size - 1),
343        AddrRange(IO_address_space_base,
344                  interrupts_address_space_base - 1),
345        AddrRange(pci_config_address_space_base,
346                  Addr.max)
347        ]
348
349    # Create a bridge from the IO bus to the memory bus to allow access to
350    # the local APIC (two pages)
351    x86_sys.apicbridge = Bridge(delay='50ns')
352    x86_sys.apicbridge.slave = x86_sys.iobus.master
353    x86_sys.apicbridge.master = x86_sys.membus.slave
354    x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
355                                           interrupts_address_space_base +
356                                           numCPUs * APIC_range_size
357                                           - 1)]
358
359    # connect the io bus
360    x86_sys.pc.attachIO(x86_sys.iobus)
361
362    x86_sys.system_port = x86_sys.membus.slave
363
364def connectX86RubySystem(x86_sys):
365    # North Bridge
366    x86_sys.iobus = NoncoherentBus()
367
368    # add the ide to the list of dma devices that later need to attach to
369    # dma controllers
370    x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma]
371    x86_sys.pc.attachIO(x86_sys.iobus, x86_sys._dma_ports)
372
373
374def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None,
375                  Ruby = False):
376    if self == None:
377        self = X86System()
378
379    if not mdesc:
380        # generic system
381        mdesc = SysConfig()
382    self.readfile = mdesc.script()
383
384    self.mem_mode = mem_mode
385
386    # Physical memory
387    # On the PC platform, the memory region 0xC0000000-0xFFFFFFFF is reserved
388    # for various devices.  Hence, if the physical memory size is greater than
389    # 3GB, we need to split it into two parts.
390    excess_mem_size = \
391        convert.toMemorySize(mdesc.mem()) - convert.toMemorySize('3GB')
392    if excess_mem_size <= 0:
393        self.mem_ranges = [AddrRange(mdesc.mem())]
394    else:
395        warn("Physical memory size specified is %s which is greater than " \
396             "3GB.  Twice the number of memory controllers would be " \
397             "created."  % (mdesc.mem()))
398
399        self.mem_ranges = [AddrRange('3GB'),
400            AddrRange(Addr('4GB'), size = excess_mem_size)]
401
402    # Platform
403    self.pc = Pc()
404
405    # Create and connect the busses required by each memory system
406    if Ruby:
407        connectX86RubySystem(self)
408    else:
409        connectX86ClassicSystem(self, numCPUs)
410
411    self.intrctrl = IntrControl()
412
413    # Disks
414    disk0 = CowIdeDisk(driveID='master')
415    disk2 = CowIdeDisk(driveID='master')
416    disk0.childImage(mdesc.disk())
417    disk2.childImage(disk('linux-bigswap2.img'))
418    self.pc.south_bridge.ide.disks = [disk0, disk2]
419
420    # Add in a Bios information structure.
421    structures = [X86SMBiosBiosInformation()]
422    self.smbios_table.structures = structures
423
424    # Set up the Intel MP table
425    base_entries = []
426    ext_entries = []
427    for i in xrange(numCPUs):
428        bp = X86IntelMPProcessor(
429                local_apic_id = i,
430                local_apic_version = 0x14,
431                enable = True,
432                bootstrap = (i == 0))
433        base_entries.append(bp)
434    io_apic = X86IntelMPIOAPIC(
435            id = numCPUs,
436            version = 0x11,
437            enable = True,
438            address = 0xfec00000)
439    self.pc.south_bridge.io_apic.apic_id = io_apic.id
440    base_entries.append(io_apic)
441    isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA')
442    base_entries.append(isa_bus)
443    pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI')
444    base_entries.append(pci_bus)
445    connect_busses = X86IntelMPBusHierarchy(bus_id=0,
446            subtractive_decode=True, parent_bus=1)
447    ext_entries.append(connect_busses)
448    pci_dev4_inta = X86IntelMPIOIntAssignment(
449            interrupt_type = 'INT',
450            polarity = 'ConformPolarity',
451            trigger = 'ConformTrigger',
452            source_bus_id = 1,
453            source_bus_irq = 0 + (4 << 2),
454            dest_io_apic_id = io_apic.id,
455            dest_io_apic_intin = 16)
456    base_entries.append(pci_dev4_inta)
457    def assignISAInt(irq, apicPin):
458        assign_8259_to_apic = X86IntelMPIOIntAssignment(
459                interrupt_type = 'ExtInt',
460                polarity = 'ConformPolarity',
461                trigger = 'ConformTrigger',
462                source_bus_id = 0,
463                source_bus_irq = irq,
464                dest_io_apic_id = io_apic.id,
465                dest_io_apic_intin = 0)
466        base_entries.append(assign_8259_to_apic)
467        assign_to_apic = X86IntelMPIOIntAssignment(
468                interrupt_type = 'INT',
469                polarity = 'ConformPolarity',
470                trigger = 'ConformTrigger',
471                source_bus_id = 0,
472                source_bus_irq = irq,
473                dest_io_apic_id = io_apic.id,
474                dest_io_apic_intin = apicPin)
475        base_entries.append(assign_to_apic)
476    assignISAInt(0, 2)
477    assignISAInt(1, 1)
478    for i in range(3, 15):
479        assignISAInt(i, i)
480    self.intel_mp_table.base_entries = base_entries
481    self.intel_mp_table.ext_entries = ext_entries
482
483def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None,
484                       Ruby = False):
485    self = LinuxX86System()
486
487    # Build up the x86 system and then specialize it for Linux
488    makeX86System(mem_mode, numCPUs, mdesc, self, Ruby)
489
490    # We assume below that there's at least 1MB of memory. We'll require 2
491    # just to avoid corner cases.
492    phys_mem_size = sum(map(lambda r: r.size(), self.mem_ranges))
493    assert(phys_mem_size >= 0x200000)
494    assert(len(self.mem_ranges) <= 2)
495
496    entries = \
497       [
498        # Mark the first megabyte of memory as reserved
499        X86E820Entry(addr = 0, size = '639kB', range_type = 1),
500        X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2),
501        # Mark the rest of physical memory as available
502        X86E820Entry(addr = 0x100000,
503                size = '%dB' % (self.mem_ranges[0].size() - 0x100000),
504                range_type = 1),
505        # Reserve the last 16kB of the 32-bit address space for the
506        # m5op interface
507        X86E820Entry(addr=0xFFFF0000, size='64kB', range_type=2),
508        ]
509
510    # In case the physical memory is greater than 3GB, we split it into two
511    # parts and add a separate e820 entry for the second part.  This entry
512    # starts at 0x100000000,  which is the first address after the space
513    # reserved for devices.
514    if len(self.mem_ranges) == 2:
515        entries.append(X86E820Entry(addr = 0x100000000,
516            size = '%dB' % (self.mem_ranges[1].size()), range_type = 1))
517
518    self.e820_table.entries = entries
519
520    # Command line
521    self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \
522                        'root=/dev/hda1'
523    self.kernel = binary('x86_64-vmlinux-2.6.22.9')
524    return self
525
526
527def makeDualRoot(full_system, testSystem, driveSystem, dumpfile):
528    self = Root(full_system = full_system)
529    self.testsys = testSystem
530    self.drivesys = driveSystem
531    self.etherlink = EtherLink()
532    self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
533    self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
534
535    if hasattr(testSystem, 'realview'):
536        self.etherlink.int0 = Parent.testsys.realview.ethernet.interface
537        self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface
538    elif hasattr(testSystem, 'tsunami'):
539        self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
540        self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
541    else:
542        fatal("Don't know how to connect these system together")
543
544    if dumpfile:
545        self.etherdump = EtherDump(file=dumpfile)
546        self.etherlink.dump = Parent.etherdump
547
548    return self
549