FSConfig.py revision 9489
18706Sandreas.hansson@arm.com# Copyright (c) 2010-2012 ARM Limited 27586SAli.Saidi@arm.com# All rights reserved. 37586SAli.Saidi@arm.com# 47586SAli.Saidi@arm.com# The license below extends only to copyright in the software and shall 57586SAli.Saidi@arm.com# not be construed as granting a license to any other intellectual 67586SAli.Saidi@arm.com# property including but not limited to intellectual property relating 77586SAli.Saidi@arm.com# to a hardware implementation of the functionality of the software 87586SAli.Saidi@arm.com# licensed hereunder. You may use the software subject to the license 97586SAli.Saidi@arm.com# terms below provided that you ensure that this notice is replicated 107586SAli.Saidi@arm.com# unmodified and in its entirety in all distributions of the software, 117586SAli.Saidi@arm.com# modified or unmodified, in source code or in binary form. 127586SAli.Saidi@arm.com# 137905SBrad.Beckmann@amd.com# Copyright (c) 2010-2011 Advanced Micro Devices, Inc. 145323Sgblack@eecs.umich.edu# Copyright (c) 2006-2008 The Regents of The University of Michigan 152934Sktlim@umich.edu# All rights reserved. 162934Sktlim@umich.edu# 172934Sktlim@umich.edu# Redistribution and use in source and binary forms, with or without 182934Sktlim@umich.edu# modification, are permitted provided that the following conditions are 192934Sktlim@umich.edu# met: redistributions of source code must retain the above copyright 202934Sktlim@umich.edu# notice, this list of conditions and the following disclaimer; 212934Sktlim@umich.edu# redistributions in binary form must reproduce the above copyright 222934Sktlim@umich.edu# notice, this list of conditions and the following disclaimer in the 232934Sktlim@umich.edu# documentation and/or other materials provided with the distribution; 242934Sktlim@umich.edu# neither the name of the copyright holders nor the names of its 252934Sktlim@umich.edu# contributors may be used to endorse or promote products derived from 262934Sktlim@umich.edu# this software without specific prior written permission. 272934Sktlim@umich.edu# 282934Sktlim@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292934Sktlim@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302934Sktlim@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312934Sktlim@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322934Sktlim@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332934Sktlim@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342934Sktlim@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352934Sktlim@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362934Sktlim@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372934Sktlim@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382934Sktlim@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392934Sktlim@umich.edu# 402934Sktlim@umich.edu# Authors: Kevin Lim 412934Sktlim@umich.edu 422934Sktlim@umich.edufrom m5.objects import * 432995Ssaidi@eecs.umich.edufrom Benchmarks import * 448528SAli.Saidi@ARM.comfrom m5.util import convert 452934Sktlim@umich.edu 462934Sktlim@umich.educlass CowIdeDisk(IdeDisk): 472934Sktlim@umich.edu image = CowDiskImage(child=RawDiskImage(read_only=True), 482934Sktlim@umich.edu read_only=False) 492934Sktlim@umich.edu 502934Sktlim@umich.edu def childImage(self, ci): 512934Sktlim@umich.edu self.image.child.image_file = ci 522934Sktlim@umich.edu 539036Sandreas.hansson@arm.comclass MemBus(CoherentBus): 546122SSteve.Reinhardt@amd.com badaddr_responder = BadAddr() 556122SSteve.Reinhardt@amd.com default = Self.badaddr_responder.pio 566122SSteve.Reinhardt@amd.com 576122SSteve.Reinhardt@amd.com 584520Ssaidi@eecs.umich.edudef makeLinuxAlphaSystem(mem_mode, mdesc = None): 598713Sandreas.hansson@arm.com IO_address_space_base = 0x80000000000 604520Ssaidi@eecs.umich.edu class BaseTsunami(Tsunami): 614982Ssaidi@eecs.umich.edu ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 624520Ssaidi@eecs.umich.edu ide = IdeController(disks=[Parent.disk0, Parent.disk2], 634520Ssaidi@eecs.umich.edu pci_func=0, pci_dev=0, pci_bus=0) 642934Sktlim@umich.edu 652934Sktlim@umich.edu self = LinuxAlphaSystem() 663005Sstever@eecs.umich.edu if not mdesc: 673005Sstever@eecs.umich.edu # generic system 683304Sstever@eecs.umich.edu mdesc = SysConfig() 692995Ssaidi@eecs.umich.edu self.readfile = mdesc.script() 709036Sandreas.hansson@arm.com self.iobus = NoncoherentBus() 719036Sandreas.hansson@arm.com self.membus = MemBus() 728713Sandreas.hansson@arm.com # By default the bridge responds to all addresses above the I/O 738713Sandreas.hansson@arm.com # base address (including the PCI config space) 749164Sandreas.hansson@arm.com self.bridge = Bridge(delay='50ns', 758713Sandreas.hansson@arm.com ranges = [AddrRange(IO_address_space_base, Addr.max)]) 769489Sandreas.hansson@arm.com self.physmem = SimpleDDR3(range = AddrRange(mdesc.mem())) 779408Sandreas.hansson@arm.com self.mem_ranges = [self.physmem.range] 788839Sandreas.hansson@arm.com self.bridge.master = self.iobus.slave 798839Sandreas.hansson@arm.com self.bridge.slave = self.membus.master 808839Sandreas.hansson@arm.com self.physmem.port = self.membus.master 812934Sktlim@umich.edu self.disk0 = CowIdeDisk(driveID='master') 822934Sktlim@umich.edu self.disk2 = CowIdeDisk(driveID='master') 832995Ssaidi@eecs.umich.edu self.disk0.childImage(mdesc.disk()) 842934Sktlim@umich.edu self.disk2.childImage(disk('linux-bigswap2.img')) 852934Sktlim@umich.edu self.tsunami = BaseTsunami() 862934Sktlim@umich.edu self.tsunami.attachIO(self.iobus) 878839Sandreas.hansson@arm.com self.tsunami.ide.pio = self.iobus.master 888839Sandreas.hansson@arm.com self.tsunami.ide.config = self.iobus.master 898839Sandreas.hansson@arm.com self.tsunami.ide.dma = self.iobus.slave 908839Sandreas.hansson@arm.com self.tsunami.ethernet.pio = self.iobus.master 918839Sandreas.hansson@arm.com self.tsunami.ethernet.config = self.iobus.master 928839Sandreas.hansson@arm.com self.tsunami.ethernet.dma = self.iobus.slave 932995Ssaidi@eecs.umich.edu self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 942934Sktlim@umich.edu read_only = True)) 952934Sktlim@umich.edu self.intrctrl = IntrControl() 962953Sktlim@umich.edu self.mem_mode = mem_mode 975478Snate@binkert.org self.terminal = Terminal() 982934Sktlim@umich.edu self.kernel = binary('vmlinux') 993449Shsul@eecs.umich.edu self.pal = binary('ts_osfpal') 1002934Sktlim@umich.edu self.console = binary('console') 1012934Sktlim@umich.edu self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 1022934Sktlim@umich.edu 1038839Sandreas.hansson@arm.com self.system_port = self.membus.slave 1048706Sandreas.hansson@arm.com 1052934Sktlim@umich.edu return self 1062934Sktlim@umich.edu 1077014SBrad.Beckmann@amd.comdef makeLinuxAlphaRubySystem(mem_mode, mdesc = None): 1086765SBrad.Beckmann@amd.com class BaseTsunami(Tsunami): 1096765SBrad.Beckmann@amd.com ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 1106765SBrad.Beckmann@amd.com ide = IdeController(disks=[Parent.disk0, Parent.disk2], 1116765SBrad.Beckmann@amd.com pci_func=0, pci_dev=0, pci_bus=0) 1126765SBrad.Beckmann@amd.com 1139489Sandreas.hansson@arm.com physmem = SimpleDDR3(range = AddrRange(mdesc.mem())) 1147014SBrad.Beckmann@amd.com self = LinuxAlphaSystem(physmem = physmem) 1159408Sandreas.hansson@arm.com self.mem_ranges = [self.physmem.range] 1166765SBrad.Beckmann@amd.com if not mdesc: 1176765SBrad.Beckmann@amd.com # generic system 1186765SBrad.Beckmann@amd.com mdesc = SysConfig() 1196765SBrad.Beckmann@amd.com self.readfile = mdesc.script() 1206765SBrad.Beckmann@amd.com 1216765SBrad.Beckmann@amd.com # Create pio bus to connect all device pio ports to rubymem's pio port 1229036Sandreas.hansson@arm.com self.piobus = NoncoherentBus() 1236893SBrad.Beckmann@amd.com 1246893SBrad.Beckmann@amd.com # 1256893SBrad.Beckmann@amd.com # Pio functional accesses from devices need direct access to memory 1266893SBrad.Beckmann@amd.com # RubyPort currently does support functional accesses. Therefore provide 1276893SBrad.Beckmann@amd.com # the piobus a direct connection to physical memory 1286893SBrad.Beckmann@amd.com # 1298898Snilay@cs.wisc.edu self.piobus.master = physmem.port 1306893SBrad.Beckmann@amd.com 1316765SBrad.Beckmann@amd.com self.disk0 = CowIdeDisk(driveID='master') 1326765SBrad.Beckmann@amd.com self.disk2 = CowIdeDisk(driveID='master') 1336765SBrad.Beckmann@amd.com self.disk0.childImage(mdesc.disk()) 1346765SBrad.Beckmann@amd.com self.disk2.childImage(disk('linux-bigswap2.img')) 1356765SBrad.Beckmann@amd.com self.tsunami = BaseTsunami() 1366765SBrad.Beckmann@amd.com self.tsunami.attachIO(self.piobus) 1378839Sandreas.hansson@arm.com self.tsunami.ide.pio = self.piobus.master 1388839Sandreas.hansson@arm.com self.tsunami.ide.config = self.piobus.master 1398839Sandreas.hansson@arm.com self.tsunami.ethernet.pio = self.piobus.master 1408839Sandreas.hansson@arm.com self.tsunami.ethernet.config = self.piobus.master 1416765SBrad.Beckmann@amd.com 1426893SBrad.Beckmann@amd.com # 1437633SBrad.Beckmann@amd.com # Store the dma devices for later connection to dma ruby ports. 1447633SBrad.Beckmann@amd.com # Append an underscore to dma_devices to avoid the SimObjectVector check. 1456893SBrad.Beckmann@amd.com # 1468929Snilay@cs.wisc.edu self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma] 1476765SBrad.Beckmann@amd.com 1486765SBrad.Beckmann@amd.com self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 1496765SBrad.Beckmann@amd.com read_only = True)) 1506765SBrad.Beckmann@amd.com self.intrctrl = IntrControl() 1516765SBrad.Beckmann@amd.com self.mem_mode = mem_mode 1526765SBrad.Beckmann@amd.com self.terminal = Terminal() 1536765SBrad.Beckmann@amd.com self.kernel = binary('vmlinux') 1546765SBrad.Beckmann@amd.com self.pal = binary('ts_osfpal') 1556765SBrad.Beckmann@amd.com self.console = binary('console') 1566765SBrad.Beckmann@amd.com self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 1576765SBrad.Beckmann@amd.com 1586765SBrad.Beckmann@amd.com return self 1596765SBrad.Beckmann@amd.com 1603584Ssaidi@eecs.umich.edudef makeSparcSystem(mem_mode, mdesc = None): 1618713Sandreas.hansson@arm.com # Constants from iob.cc and uart8250.cc 1628713Sandreas.hansson@arm.com iob_man_addr = 0x9800000000 1638713Sandreas.hansson@arm.com uart_pio_size = 8 1648713Sandreas.hansson@arm.com 1654486Sbinkertn@umich.edu class CowMmDisk(MmDisk): 1664486Sbinkertn@umich.edu image = CowDiskImage(child=RawDiskImage(read_only=True), 1674486Sbinkertn@umich.edu read_only=False) 1684486Sbinkertn@umich.edu 1694486Sbinkertn@umich.edu def childImage(self, ci): 1704486Sbinkertn@umich.edu self.image.child.image_file = ci 1714486Sbinkertn@umich.edu 1723584Ssaidi@eecs.umich.edu self = SparcSystem() 1733584Ssaidi@eecs.umich.edu if not mdesc: 1743584Ssaidi@eecs.umich.edu # generic system 1753584Ssaidi@eecs.umich.edu mdesc = SysConfig() 1763584Ssaidi@eecs.umich.edu self.readfile = mdesc.script() 1779036Sandreas.hansson@arm.com self.iobus = NoncoherentBus() 1789036Sandreas.hansson@arm.com self.membus = MemBus() 1799164Sandreas.hansson@arm.com self.bridge = Bridge(delay='50ns') 1803743Sgblack@eecs.umich.edu self.t1000 = T1000() 1814104Ssaidi@eecs.umich.edu self.t1000.attachOnChipIO(self.membus) 1823743Sgblack@eecs.umich.edu self.t1000.attachIO(self.iobus) 1839489Sandreas.hansson@arm.com self.physmem = SimpleDDR3(range = AddrRange(Addr('1MB'), size = '64MB'), 1849489Sandreas.hansson@arm.com zero = True) 1859489Sandreas.hansson@arm.com self.physmem2 = SimpleDDR3(range = AddrRange(Addr('2GB'), size ='256MB'), 1869489Sandreas.hansson@arm.com zero = True) 1879408Sandreas.hansson@arm.com self.mem_ranges = [self.physmem.range, self.physmem2.range] 1888839Sandreas.hansson@arm.com self.bridge.master = self.iobus.slave 1898839Sandreas.hansson@arm.com self.bridge.slave = self.membus.master 1908839Sandreas.hansson@arm.com self.physmem.port = self.membus.master 1918839Sandreas.hansson@arm.com self.physmem2.port = self.membus.master 1928839Sandreas.hansson@arm.com self.rom.port = self.membus.master 1938839Sandreas.hansson@arm.com self.nvram.port = self.membus.master 1948839Sandreas.hansson@arm.com self.hypervisor_desc.port = self.membus.master 1958839Sandreas.hansson@arm.com self.partition_desc.port = self.membus.master 1963584Ssaidi@eecs.umich.edu self.intrctrl = IntrControl() 1973898Ssaidi@eecs.umich.edu self.disk0 = CowMmDisk() 1983898Ssaidi@eecs.umich.edu self.disk0.childImage(disk('disk.s10hw2')) 1998839Sandreas.hansson@arm.com self.disk0.pio = self.iobus.master 2008713Sandreas.hansson@arm.com 2018713Sandreas.hansson@arm.com # The puart0 and hvuart are placed on the IO bus, so create ranges 2028713Sandreas.hansson@arm.com # for them. The remaining IO range is rather fragmented, so poke 2038713Sandreas.hansson@arm.com # holes for the iob and partition descriptors etc. 2048713Sandreas.hansson@arm.com self.bridge.ranges = \ 2058713Sandreas.hansson@arm.com [ 2068713Sandreas.hansson@arm.com AddrRange(self.t1000.puart0.pio_addr, 2078713Sandreas.hansson@arm.com self.t1000.puart0.pio_addr + uart_pio_size - 1), 2088713Sandreas.hansson@arm.com AddrRange(self.disk0.pio_addr, 2098713Sandreas.hansson@arm.com self.t1000.fake_jbi.pio_addr + 2108713Sandreas.hansson@arm.com self.t1000.fake_jbi.pio_size - 1), 2118713Sandreas.hansson@arm.com AddrRange(self.t1000.fake_clk.pio_addr, 2128713Sandreas.hansson@arm.com iob_man_addr - 1), 2138713Sandreas.hansson@arm.com AddrRange(self.t1000.fake_l2_1.pio_addr, 2148713Sandreas.hansson@arm.com self.t1000.fake_ssi.pio_addr + 2158713Sandreas.hansson@arm.com self.t1000.fake_ssi.pio_size - 1), 2168713Sandreas.hansson@arm.com AddrRange(self.t1000.hvuart.pio_addr, 2178713Sandreas.hansson@arm.com self.t1000.hvuart.pio_addr + uart_pio_size - 1) 2188713Sandreas.hansson@arm.com ] 2194103Ssaidi@eecs.umich.edu self.reset_bin = binary('reset_new.bin') 2204103Ssaidi@eecs.umich.edu self.hypervisor_bin = binary('q_new.bin') 2214103Ssaidi@eecs.umich.edu self.openboot_bin = binary('openboot_new.bin') 2223745Sgblack@eecs.umich.edu self.nvram_bin = binary('nvram1') 2233745Sgblack@eecs.umich.edu self.hypervisor_desc_bin = binary('1up-hv.bin') 2243745Sgblack@eecs.umich.edu self.partition_desc_bin = binary('1up-md.bin') 2253584Ssaidi@eecs.umich.edu 2268839Sandreas.hansson@arm.com self.system_port = self.membus.slave 2278706Sandreas.hansson@arm.com 2283584Ssaidi@eecs.umich.edu return self 2293584Ssaidi@eecs.umich.edu 2308061SAli.Saidi@ARM.comdef makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False): 2318061SAli.Saidi@ARM.com assert machine_type 2328061SAli.Saidi@ARM.com 2337586SAli.Saidi@arm.com if bare_metal: 2347586SAli.Saidi@arm.com self = ArmSystem() 2357586SAli.Saidi@arm.com else: 2367586SAli.Saidi@arm.com self = LinuxArmSystem() 2377586SAli.Saidi@arm.com 2387586SAli.Saidi@arm.com if not mdesc: 2397586SAli.Saidi@arm.com # generic system 2407586SAli.Saidi@arm.com mdesc = SysConfig() 2417586SAli.Saidi@arm.com 2427586SAli.Saidi@arm.com self.readfile = mdesc.script() 2439036Sandreas.hansson@arm.com self.iobus = NoncoherentBus() 2449036Sandreas.hansson@arm.com self.membus = MemBus() 2457586SAli.Saidi@arm.com self.membus.badaddr_responder.warn_access = "warn" 2469164Sandreas.hansson@arm.com self.bridge = Bridge(delay='50ns') 2478839Sandreas.hansson@arm.com self.bridge.master = self.iobus.slave 2488839Sandreas.hansson@arm.com self.bridge.slave = self.membus.master 2497586SAli.Saidi@arm.com 2507586SAli.Saidi@arm.com self.mem_mode = mem_mode 2517586SAli.Saidi@arm.com 2527586SAli.Saidi@arm.com if machine_type == "RealView_PBX": 2537586SAli.Saidi@arm.com self.realview = RealViewPBX() 2547586SAli.Saidi@arm.com elif machine_type == "RealView_EB": 2557586SAli.Saidi@arm.com self.realview = RealViewEB() 2568525SAli.Saidi@ARM.com elif machine_type == "VExpress_ELT": 2578525SAli.Saidi@ARM.com self.realview = VExpress_ELT() 2588870SAli.Saidi@ARM.com elif machine_type == "VExpress_EMM": 2598870SAli.Saidi@ARM.com self.realview = VExpress_EMM() 2608870SAli.Saidi@ARM.com self.load_addr_mask = 0xffffffff 2617586SAli.Saidi@arm.com else: 2627586SAli.Saidi@arm.com print "Unknown Machine Type" 2637586SAli.Saidi@arm.com sys.exit(1) 2647586SAli.Saidi@arm.com 2658528SAli.Saidi@ARM.com self.cf0 = CowIdeDisk(driveID='master') 2668528SAli.Saidi@ARM.com self.cf0.childImage(mdesc.disk()) 2678528SAli.Saidi@ARM.com # default to an IDE controller rather than a CF one 2688528SAli.Saidi@ARM.com # assuming we've got one 2698528SAli.Saidi@ARM.com try: 2708528SAli.Saidi@ARM.com self.realview.ide.disks = [self.cf0] 2718528SAli.Saidi@ARM.com except: 2728528SAli.Saidi@ARM.com self.realview.cf_ctrl.disks = [self.cf0] 2738528SAli.Saidi@ARM.com 2748061SAli.Saidi@ARM.com if bare_metal: 2758061SAli.Saidi@ARM.com # EOT character on UART will end the simulation 2768061SAli.Saidi@ARM.com self.realview.uart.end_on_eot = True 2779489Sandreas.hansson@arm.com self.physmem = SimpleDDR3(range = AddrRange(Addr(mdesc.mem())), 2789489Sandreas.hansson@arm.com zero = True) 2799408Sandreas.hansson@arm.com self.mem_ranges = [self.physmem.range] 2808061SAli.Saidi@ARM.com else: 2818528SAli.Saidi@ARM.com self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8') 2827586SAli.Saidi@arm.com self.machine_type = machine_type 2838894Ssaidi@eecs.umich.edu if convert.toMemorySize(mdesc.mem()) > int(self.realview.max_mem_size): 2848870SAli.Saidi@ARM.com print "The currently selected ARM platforms doesn't support" 2858870SAli.Saidi@ARM.com print " the amount of DRAM you've selected. Please try" 2868870SAli.Saidi@ARM.com print " another platform" 2878894Ssaidi@eecs.umich.edu sys.exit(1) 2888528SAli.Saidi@ARM.com 2898212SAli.Saidi@ARM.com boot_flags = 'earlyprintk console=ttyAMA0 lpj=19988480 norandmaps ' + \ 2908528SAli.Saidi@ARM.com 'rw loglevel=8 mem=%s root=/dev/sda1' % mdesc.mem() 2918528SAli.Saidi@ARM.com 2929489Sandreas.hansson@arm.com self.physmem = SimpleDDR3(range = 2939489Sandreas.hansson@arm.com AddrRange(self.realview.mem_start_addr, 2949489Sandreas.hansson@arm.com size = mdesc.mem()), 2959489Sandreas.hansson@arm.com conf_table_reported = True) 2969408Sandreas.hansson@arm.com self.mem_ranges = [self.physmem.range] 2978870SAli.Saidi@ARM.com self.realview.setupBootLoader(self.membus, self, binary) 2988528SAli.Saidi@ARM.com self.gic_cpu_addr = self.realview.gic.cpu_addr 2998528SAli.Saidi@ARM.com self.flags_addr = self.realview.realview_io.pio_addr + 0x30 3008287SAli.Saidi@ARM.com 3018643Satgutier@umich.edu if mdesc.disk().lower().count('android'): 3028595SAli.Saidi@ARM.com boot_flags += " init=/init " 3038212SAli.Saidi@ARM.com self.boot_osflags = boot_flags 3047586SAli.Saidi@arm.com 3058839Sandreas.hansson@arm.com self.physmem.port = self.membus.master 3068713Sandreas.hansson@arm.com self.realview.attachOnChipIO(self.membus, self.bridge) 3077586SAli.Saidi@arm.com self.realview.attachIO(self.iobus) 3087586SAli.Saidi@arm.com self.intrctrl = IntrControl() 3097586SAli.Saidi@arm.com self.terminal = Terminal() 3107949SAli.Saidi@ARM.com self.vncserver = VncServer() 3117586SAli.Saidi@arm.com 3128839Sandreas.hansson@arm.com self.system_port = self.membus.slave 3138706Sandreas.hansson@arm.com 3147586SAli.Saidi@arm.com return self 3157586SAli.Saidi@arm.com 3167586SAli.Saidi@arm.com 3175222Sksewell@umich.edudef makeLinuxMipsSystem(mem_mode, mdesc = None): 3185222Sksewell@umich.edu class BaseMalta(Malta): 3195222Sksewell@umich.edu ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 3205222Sksewell@umich.edu ide = IdeController(disks=[Parent.disk0, Parent.disk2], 3215222Sksewell@umich.edu pci_func=0, pci_dev=0, pci_bus=0) 3225222Sksewell@umich.edu 3235222Sksewell@umich.edu self = LinuxMipsSystem() 3245222Sksewell@umich.edu if not mdesc: 3255222Sksewell@umich.edu # generic system 3265222Sksewell@umich.edu mdesc = SysConfig() 3275222Sksewell@umich.edu self.readfile = mdesc.script() 3289036Sandreas.hansson@arm.com self.iobus = NoncoherentBus() 3299036Sandreas.hansson@arm.com self.membus = MemBus() 3309164Sandreas.hansson@arm.com self.bridge = Bridge(delay='50ns') 3319489Sandreas.hansson@arm.com self.physmem = SimpleDDR3(range = AddrRange('1GB')) 3329408Sandreas.hansson@arm.com self.mem_ranges = [self.physmem.range] 3338839Sandreas.hansson@arm.com self.bridge.master = self.iobus.slave 3348839Sandreas.hansson@arm.com self.bridge.slave = self.membus.master 3358839Sandreas.hansson@arm.com self.physmem.port = self.membus.master 3365222Sksewell@umich.edu self.disk0 = CowIdeDisk(driveID='master') 3375222Sksewell@umich.edu self.disk2 = CowIdeDisk(driveID='master') 3385222Sksewell@umich.edu self.disk0.childImage(mdesc.disk()) 3395222Sksewell@umich.edu self.disk2.childImage(disk('linux-bigswap2.img')) 3405222Sksewell@umich.edu self.malta = BaseMalta() 3415222Sksewell@umich.edu self.malta.attachIO(self.iobus) 3428839Sandreas.hansson@arm.com self.malta.ide.pio = self.iobus.master 3438839Sandreas.hansson@arm.com self.malta.ide.config = self.iobus.master 3448839Sandreas.hansson@arm.com self.malta.ide.dma = self.iobus.slave 3458839Sandreas.hansson@arm.com self.malta.ethernet.pio = self.iobus.master 3468839Sandreas.hansson@arm.com self.malta.ethernet.config = self.iobus.master 3478839Sandreas.hansson@arm.com self.malta.ethernet.dma = self.iobus.slave 3485222Sksewell@umich.edu self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 3495222Sksewell@umich.edu read_only = True)) 3505222Sksewell@umich.edu self.intrctrl = IntrControl() 3515222Sksewell@umich.edu self.mem_mode = mem_mode 3525478Snate@binkert.org self.terminal = Terminal() 3535222Sksewell@umich.edu self.kernel = binary('mips/vmlinux') 3545222Sksewell@umich.edu self.console = binary('mips/console') 3555222Sksewell@umich.edu self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 3565222Sksewell@umich.edu 3578839Sandreas.hansson@arm.com self.system_port = self.membus.slave 3588706Sandreas.hansson@arm.com 3595222Sksewell@umich.edu return self 3605222Sksewell@umich.edu 3615323Sgblack@eecs.umich.edudef x86IOAddress(port): 3625357Sgblack@eecs.umich.edu IO_address_space_base = 0x8000000000000000 3638323Ssteve.reinhardt@amd.com return IO_address_space_base + port 3645323Sgblack@eecs.umich.edu 3658858Sgblack@eecs.umich.edudef connectX86ClassicSystem(x86_sys, numCPUs): 3668713Sandreas.hansson@arm.com # Constants similar to x86_traits.hh 3678713Sandreas.hansson@arm.com IO_address_space_base = 0x8000000000000000 3688713Sandreas.hansson@arm.com pci_config_address_space_base = 0xc000000000000000 3698713Sandreas.hansson@arm.com interrupts_address_space_base = 0xa000000000000000 3708713Sandreas.hansson@arm.com APIC_range_size = 1 << 12; 3718713Sandreas.hansson@arm.com 3729036Sandreas.hansson@arm.com x86_sys.membus = MemBus() 3738839Sandreas.hansson@arm.com x86_sys.physmem.port = x86_sys.membus.master 3747905SBrad.Beckmann@amd.com 3757905SBrad.Beckmann@amd.com # North Bridge 3769036Sandreas.hansson@arm.com x86_sys.iobus = NoncoherentBus() 3779164Sandreas.hansson@arm.com x86_sys.bridge = Bridge(delay='50ns') 3788839Sandreas.hansson@arm.com x86_sys.bridge.master = x86_sys.iobus.slave 3798839Sandreas.hansson@arm.com x86_sys.bridge.slave = x86_sys.membus.master 3808713Sandreas.hansson@arm.com # Allow the bridge to pass through the IO APIC (two pages), 3818713Sandreas.hansson@arm.com # everything in the IO address range up to the local APIC, and 3828713Sandreas.hansson@arm.com # then the entire PCI address space and beyond 3838713Sandreas.hansson@arm.com x86_sys.bridge.ranges = \ 3848713Sandreas.hansson@arm.com [ 3858713Sandreas.hansson@arm.com AddrRange(x86_sys.pc.south_bridge.io_apic.pio_addr, 3868713Sandreas.hansson@arm.com x86_sys.pc.south_bridge.io_apic.pio_addr + 3878713Sandreas.hansson@arm.com APIC_range_size - 1), 3888713Sandreas.hansson@arm.com AddrRange(IO_address_space_base, 3898713Sandreas.hansson@arm.com interrupts_address_space_base - 1), 3908713Sandreas.hansson@arm.com AddrRange(pci_config_address_space_base, 3918713Sandreas.hansson@arm.com Addr.max) 3928713Sandreas.hansson@arm.com ] 3938713Sandreas.hansson@arm.com 3948713Sandreas.hansson@arm.com # Create a bridge from the IO bus to the memory bus to allow access to 3958713Sandreas.hansson@arm.com # the local APIC (two pages) 3969164Sandreas.hansson@arm.com x86_sys.apicbridge = Bridge(delay='50ns') 3978839Sandreas.hansson@arm.com x86_sys.apicbridge.slave = x86_sys.iobus.master 3988839Sandreas.hansson@arm.com x86_sys.apicbridge.master = x86_sys.membus.slave 3998815Sgblack@eecs.umich.edu x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base, 4008815Sgblack@eecs.umich.edu interrupts_address_space_base + 4018858Sgblack@eecs.umich.edu numCPUs * APIC_range_size 4028858Sgblack@eecs.umich.edu - 1)] 4037905SBrad.Beckmann@amd.com 4047905SBrad.Beckmann@amd.com # connect the io bus 4057905SBrad.Beckmann@amd.com x86_sys.pc.attachIO(x86_sys.iobus) 4067905SBrad.Beckmann@amd.com 4078839Sandreas.hansson@arm.com x86_sys.system_port = x86_sys.membus.slave 4088706Sandreas.hansson@arm.com 4097905SBrad.Beckmann@amd.comdef connectX86RubySystem(x86_sys): 4107905SBrad.Beckmann@amd.com # North Bridge 4119036Sandreas.hansson@arm.com x86_sys.piobus = NoncoherentBus() 4127905SBrad.Beckmann@amd.com 4137905SBrad.Beckmann@amd.com # 4147905SBrad.Beckmann@amd.com # Pio functional accesses from devices need direct access to memory 4157905SBrad.Beckmann@amd.com # RubyPort currently does support functional accesses. Therefore provide 4167905SBrad.Beckmann@amd.com # the piobus a direct connection to physical memory 4177905SBrad.Beckmann@amd.com # 4188839Sandreas.hansson@arm.com x86_sys.piobus.master = x86_sys.physmem.port 4198929Snilay@cs.wisc.edu # add the ide to the list of dma devices that later need to attach to 4208929Snilay@cs.wisc.edu # dma controllers 4218929Snilay@cs.wisc.edu x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma] 4228929Snilay@cs.wisc.edu x86_sys.pc.attachIO(x86_sys.piobus, x86_sys._dma_ports) 4237905SBrad.Beckmann@amd.com 4247905SBrad.Beckmann@amd.com 4257905SBrad.Beckmann@amd.comdef makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None, Ruby = False): 4265613Sgblack@eecs.umich.edu if self == None: 4275613Sgblack@eecs.umich.edu self = X86System() 4285613Sgblack@eecs.umich.edu 4295133Sgblack@eecs.umich.edu if not mdesc: 4305133Sgblack@eecs.umich.edu # generic system 4315133Sgblack@eecs.umich.edu mdesc = SysConfig() 4325133Sgblack@eecs.umich.edu self.readfile = mdesc.script() 4335133Sgblack@eecs.umich.edu 4346802Sgblack@eecs.umich.edu self.mem_mode = mem_mode 4356802Sgblack@eecs.umich.edu 4365133Sgblack@eecs.umich.edu # Physical memory 4379489Sandreas.hansson@arm.com self.physmem = SimpleDDR3(range = AddrRange(mdesc.mem())) 4389408Sandreas.hansson@arm.com self.mem_ranges = [self.physmem.range] 4395613Sgblack@eecs.umich.edu 4405613Sgblack@eecs.umich.edu # Platform 4415638Sgblack@eecs.umich.edu self.pc = Pc() 4427905SBrad.Beckmann@amd.com 4437905SBrad.Beckmann@amd.com # Create and connect the busses required by each memory system 4447905SBrad.Beckmann@amd.com if Ruby: 4457905SBrad.Beckmann@amd.com connectX86RubySystem(self) 4467905SBrad.Beckmann@amd.com else: 4478858Sgblack@eecs.umich.edu connectX86ClassicSystem(self, numCPUs) 4485613Sgblack@eecs.umich.edu 4495613Sgblack@eecs.umich.edu self.intrctrl = IntrControl() 4505613Sgblack@eecs.umich.edu 4515841Sgblack@eecs.umich.edu # Disks 4525841Sgblack@eecs.umich.edu disk0 = CowIdeDisk(driveID='master') 4535841Sgblack@eecs.umich.edu disk2 = CowIdeDisk(driveID='master') 4545841Sgblack@eecs.umich.edu disk0.childImage(mdesc.disk()) 4555841Sgblack@eecs.umich.edu disk2.childImage(disk('linux-bigswap2.img')) 4565841Sgblack@eecs.umich.edu self.pc.south_bridge.ide.disks = [disk0, disk2] 4575841Sgblack@eecs.umich.edu 4585615Sgblack@eecs.umich.edu # Add in a Bios information structure. 4595615Sgblack@eecs.umich.edu structures = [X86SMBiosBiosInformation()] 4605615Sgblack@eecs.umich.edu self.smbios_table.structures = structures 4615615Sgblack@eecs.umich.edu 4625641Sgblack@eecs.umich.edu # Set up the Intel MP table 4638323Ssteve.reinhardt@amd.com base_entries = [] 4648323Ssteve.reinhardt@amd.com ext_entries = [] 4656135Sgblack@eecs.umich.edu for i in xrange(numCPUs): 4666135Sgblack@eecs.umich.edu bp = X86IntelMPProcessor( 4676135Sgblack@eecs.umich.edu local_apic_id = i, 4686135Sgblack@eecs.umich.edu local_apic_version = 0x14, 4696135Sgblack@eecs.umich.edu enable = True, 4706135Sgblack@eecs.umich.edu bootstrap = (i == 0)) 4718323Ssteve.reinhardt@amd.com base_entries.append(bp) 4725644Sgblack@eecs.umich.edu io_apic = X86IntelMPIOAPIC( 4736135Sgblack@eecs.umich.edu id = numCPUs, 4745644Sgblack@eecs.umich.edu version = 0x11, 4755644Sgblack@eecs.umich.edu enable = True, 4765644Sgblack@eecs.umich.edu address = 0xfec00000) 4776135Sgblack@eecs.umich.edu self.pc.south_bridge.io_apic.apic_id = io_apic.id 4788323Ssteve.reinhardt@amd.com base_entries.append(io_apic) 4795644Sgblack@eecs.umich.edu isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA') 4808323Ssteve.reinhardt@amd.com base_entries.append(isa_bus) 4815843Sgblack@eecs.umich.edu pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI') 4828323Ssteve.reinhardt@amd.com base_entries.append(pci_bus) 4835843Sgblack@eecs.umich.edu connect_busses = X86IntelMPBusHierarchy(bus_id=0, 4845843Sgblack@eecs.umich.edu subtractive_decode=True, parent_bus=1) 4858323Ssteve.reinhardt@amd.com ext_entries.append(connect_busses) 4865843Sgblack@eecs.umich.edu pci_dev4_inta = X86IntelMPIOIntAssignment( 4875843Sgblack@eecs.umich.edu interrupt_type = 'INT', 4885843Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 4895843Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 4905843Sgblack@eecs.umich.edu source_bus_id = 1, 4915843Sgblack@eecs.umich.edu source_bus_irq = 0 + (4 << 2), 4926044Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 4935843Sgblack@eecs.umich.edu dest_io_apic_intin = 16) 4948323Ssteve.reinhardt@amd.com base_entries.append(pci_dev4_inta) 4956135Sgblack@eecs.umich.edu def assignISAInt(irq, apicPin): 4966135Sgblack@eecs.umich.edu assign_8259_to_apic = X86IntelMPIOIntAssignment( 4976135Sgblack@eecs.umich.edu interrupt_type = 'ExtInt', 4986135Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 4996135Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 5006135Sgblack@eecs.umich.edu source_bus_id = 0, 5016135Sgblack@eecs.umich.edu source_bus_irq = irq, 5026135Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 5036135Sgblack@eecs.umich.edu dest_io_apic_intin = 0) 5048323Ssteve.reinhardt@amd.com base_entries.append(assign_8259_to_apic) 5056135Sgblack@eecs.umich.edu assign_to_apic = X86IntelMPIOIntAssignment( 5066135Sgblack@eecs.umich.edu interrupt_type = 'INT', 5076135Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 5086135Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 5096135Sgblack@eecs.umich.edu source_bus_id = 0, 5106135Sgblack@eecs.umich.edu source_bus_irq = irq, 5116135Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 5126135Sgblack@eecs.umich.edu dest_io_apic_intin = apicPin) 5138323Ssteve.reinhardt@amd.com base_entries.append(assign_to_apic) 5146135Sgblack@eecs.umich.edu assignISAInt(0, 2) 5156135Sgblack@eecs.umich.edu assignISAInt(1, 1) 5166135Sgblack@eecs.umich.edu for i in range(3, 15): 5176135Sgblack@eecs.umich.edu assignISAInt(i, i) 5188323Ssteve.reinhardt@amd.com self.intel_mp_table.base_entries = base_entries 5198323Ssteve.reinhardt@amd.com self.intel_mp_table.ext_entries = ext_entries 5205641Sgblack@eecs.umich.edu 5217925Sgblack@eecs.umich.edudef makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None, Ruby = False): 5225613Sgblack@eecs.umich.edu self = LinuxX86System() 5235613Sgblack@eecs.umich.edu 5247905SBrad.Beckmann@amd.com # Build up the x86 system and then specialize it for Linux 5257905SBrad.Beckmann@amd.com makeX86System(mem_mode, numCPUs, mdesc, self, Ruby) 5265613Sgblack@eecs.umich.edu 5275450Sgblack@eecs.umich.edu # We assume below that there's at least 1MB of memory. We'll require 2 5285450Sgblack@eecs.umich.edu # just to avoid corner cases. 5299232Sandreas.hansson@arm.com phys_mem_size = sum(map(lambda mem: mem.range.size(), 5309232Sandreas.hansson@arm.com self.memories.unproxy(self))) 5319232Sandreas.hansson@arm.com assert(phys_mem_size >= 0x200000) 5325450Sgblack@eecs.umich.edu 5338323Ssteve.reinhardt@amd.com self.e820_table.entries = \ 5348323Ssteve.reinhardt@amd.com [ 5358323Ssteve.reinhardt@amd.com # Mark the first megabyte of memory as reserved 5368323Ssteve.reinhardt@amd.com X86E820Entry(addr = 0, size = '1MB', range_type = 2), 5378323Ssteve.reinhardt@amd.com # Mark the rest as available 5388323Ssteve.reinhardt@amd.com X86E820Entry(addr = 0x100000, 5399232Sandreas.hansson@arm.com size = '%dB' % (phys_mem_size - 0x100000), 5408323Ssteve.reinhardt@amd.com range_type = 1) 5418323Ssteve.reinhardt@amd.com ] 5425450Sgblack@eecs.umich.edu 5435330Sgblack@eecs.umich.edu # Command line 5445847Sgblack@eecs.umich.edu self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \ 5455845Sgblack@eecs.umich.edu 'root=/dev/hda1' 5465133Sgblack@eecs.umich.edu return self 5475133Sgblack@eecs.umich.edu 5483584Ssaidi@eecs.umich.edu 5498801Sgblack@eecs.umich.edudef makeDualRoot(full_system, testSystem, driveSystem, dumpfile): 5508801Sgblack@eecs.umich.edu self = Root(full_system = full_system) 5512995Ssaidi@eecs.umich.edu self.testsys = testSystem 5522995Ssaidi@eecs.umich.edu self.drivesys = driveSystem 5534981Ssaidi@eecs.umich.edu self.etherlink = EtherLink() 5544981Ssaidi@eecs.umich.edu self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 5554981Ssaidi@eecs.umich.edu self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 5564981Ssaidi@eecs.umich.edu 5578661SAli.Saidi@ARM.com if hasattr(testSystem, 'realview'): 5588661SAli.Saidi@ARM.com self.etherlink.int0 = Parent.testsys.realview.ethernet.interface 5598661SAli.Saidi@ARM.com self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface 5608661SAli.Saidi@ARM.com elif hasattr(testSystem, 'tsunami'): 5618661SAli.Saidi@ARM.com self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 5628661SAli.Saidi@ARM.com self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 5638661SAli.Saidi@ARM.com else: 5648661SAli.Saidi@ARM.com fatal("Don't know how to connect these system together") 5658661SAli.Saidi@ARM.com 5663025Ssaidi@eecs.umich.edu if dumpfile: 5673025Ssaidi@eecs.umich.edu self.etherdump = EtherDump(file=dumpfile) 5683025Ssaidi@eecs.umich.edu self.etherlink.dump = Parent.etherdump 5692934Sktlim@umich.edu 5702934Sktlim@umich.edu return self 571