FSConfig.py revision 9164
11689SN/A# Copyright (c) 2010-2012 ARM Limited 21689SN/A# All rights reserved. 31689SN/A# 41689SN/A# The license below extends only to copyright in the software and shall 51689SN/A# not be construed as granting a license to any other intellectual 61689SN/A# property including but not limited to intellectual property relating 71689SN/A# to a hardware implementation of the functionality of the software 81689SN/A# licensed hereunder. You may use the software subject to the license 91689SN/A# terms below provided that you ensure that this notice is replicated 101689SN/A# unmodified and in its entirety in all distributions of the software, 111689SN/A# modified or unmodified, in source code or in binary form. 121689SN/A# 131689SN/A# Copyright (c) 2010-2011 Advanced Micro Devices, Inc. 141689SN/A# Copyright (c) 2006-2008 The Regents of The University of Michigan 151689SN/A# All rights reserved. 161689SN/A# 171689SN/A# Redistribution and use in source and binary forms, with or without 181689SN/A# modification, are permitted provided that the following conditions are 191689SN/A# met: redistributions of source code must retain the above copyright 201689SN/A# notice, this list of conditions and the following disclaimer; 211689SN/A# redistributions in binary form must reproduce the above copyright 221689SN/A# notice, this list of conditions and the following disclaimer in the 231689SN/A# documentation and/or other materials provided with the distribution; 241689SN/A# neither the name of the copyright holders nor the names of its 251689SN/A# contributors may be used to endorse or promote products derived from 261689SN/A# this software without specific prior written permission. 272665Ssaidi@eecs.umich.edu# 282665Ssaidi@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301464SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311464SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321060SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331717SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341060SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351464SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361464SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371060SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381060SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 391061SN/A# 401061SN/A# Authors: Kevin Lim 411061SN/A 421061SN/Afrom m5.objects import * 431060SN/Afrom Benchmarks import * 441060SN/Afrom m5.util import convert 451060SN/A 461060SN/Aclass CowIdeDisk(IdeDisk): 471060SN/A image = CowDiskImage(child=RawDiskImage(read_only=True), 481060SN/A read_only=False) 491060SN/A 501060SN/A def childImage(self, ci): 511060SN/A self.image.child.image_file = ci 521060SN/A 531060SN/Aclass MemBus(CoherentBus): 541060SN/A badaddr_responder = BadAddr() 551060SN/A default = Self.badaddr_responder.pio 561060SN/A 571060SN/A 581060SN/Adef makeLinuxAlphaSystem(mem_mode, mdesc = None): 591060SN/A IO_address_space_base = 0x80000000000 601060SN/A class BaseTsunami(Tsunami): 611060SN/A ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 621060SN/A ide = IdeController(disks=[Parent.disk0, Parent.disk2], 631060SN/A pci_func=0, pci_dev=0, pci_bus=0) 641060SN/A 651060SN/A self = LinuxAlphaSystem() 661060SN/A if not mdesc: 671060SN/A # generic system 681060SN/A mdesc = SysConfig() 691061SN/A self.readfile = mdesc.script() 701060SN/A self.iobus = NoncoherentBus() 711061SN/A self.membus = MemBus() 721060SN/A # By default the bridge responds to all addresses above the I/O 731061SN/A # base address (including the PCI config space) 741061SN/A self.bridge = Bridge(delay='50ns', 751060SN/A ranges = [AddrRange(IO_address_space_base, Addr.max)]) 761060SN/A self.physmem = SimpleMemory(range = AddrRange(mdesc.mem())) 771060SN/A self.bridge.master = self.iobus.slave 781060SN/A self.bridge.slave = self.membus.master 791060SN/A self.physmem.port = self.membus.master 801060SN/A self.disk0 = CowIdeDisk(driveID='master') 811060SN/A self.disk2 = CowIdeDisk(driveID='master') 821060SN/A self.disk0.childImage(mdesc.disk()) 831060SN/A self.disk2.childImage(disk('linux-bigswap2.img')) 841060SN/A self.tsunami = BaseTsunami() 851060SN/A self.tsunami.attachIO(self.iobus) 861060SN/A self.tsunami.ide.pio = self.iobus.master 871060SN/A self.tsunami.ide.config = self.iobus.master 881060SN/A self.tsunami.ide.dma = self.iobus.slave 891060SN/A self.tsunami.ethernet.pio = self.iobus.master 901060SN/A self.tsunami.ethernet.config = self.iobus.master 911060SN/A self.tsunami.ethernet.dma = self.iobus.slave 921060SN/A self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 931060SN/A read_only = True)) 941061SN/A self.intrctrl = IntrControl() 951061SN/A self.mem_mode = mem_mode 961060SN/A self.terminal = Terminal() 971060SN/A self.kernel = binary('vmlinux') 981060SN/A self.pal = binary('ts_osfpal') 991061SN/A self.console = binary('console') 1001061SN/A self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 1011061SN/A 1021061SN/A self.system_port = self.membus.slave 1031061SN/A 1041060SN/A return self 1051061SN/A 1061061SN/Adef makeLinuxAlphaRubySystem(mem_mode, mdesc = None): 1071061SN/A class BaseTsunami(Tsunami): 1081062SN/A ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 1091061SN/A ide = IdeController(disks=[Parent.disk0, Parent.disk2], 1101061SN/A pci_func=0, pci_dev=0, pci_bus=0) 1111060SN/A 1121060SN/A physmem = SimpleMemory(range = AddrRange(mdesc.mem())) 1131060SN/A self = LinuxAlphaSystem(physmem = physmem) 1141060SN/A if not mdesc: 1151060SN/A # generic system 1161061SN/A mdesc = SysConfig() 1171061SN/A self.readfile = mdesc.script() 1181060SN/A 1191060SN/A # Create pio bus to connect all device pio ports to rubymem's pio port 1201060SN/A self.piobus = NoncoherentBus() 1211060SN/A 1221060SN/A # 1231060SN/A # Pio functional accesses from devices need direct access to memory 1241062SN/A # RubyPort currently does support functional accesses. Therefore provide 1251061SN/A # the piobus a direct connection to physical memory 1261060SN/A # 1271060SN/A self.piobus.master = physmem.port 1281060SN/A 1291060SN/A self.disk0 = CowIdeDisk(driveID='master') 1301060SN/A self.disk2 = CowIdeDisk(driveID='master') 1311061SN/A self.disk0.childImage(mdesc.disk()) 1321061SN/A self.disk2.childImage(disk('linux-bigswap2.img')) 1331061SN/A self.tsunami = BaseTsunami() 1341061SN/A self.tsunami.attachIO(self.piobus) 1351061SN/A self.tsunami.ide.pio = self.piobus.master 1361061SN/A self.tsunami.ide.config = self.piobus.master 1371061SN/A self.tsunami.ethernet.pio = self.piobus.master 1381060SN/A self.tsunami.ethernet.config = self.piobus.master 1391060SN/A 1401060SN/A # 1411060SN/A # Store the dma devices for later connection to dma ruby ports. 1421060SN/A # Append an underscore to dma_devices to avoid the SimObjectVector check. 1431060SN/A # 1441060SN/A self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma] 1451060SN/A 1461060SN/A self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 1471060SN/A read_only = True)) 1481060SN/A self.intrctrl = IntrControl() 1491060SN/A self.mem_mode = mem_mode 1501060SN/A self.terminal = Terminal() 1511060SN/A self.kernel = binary('vmlinux') 1521060SN/A self.pal = binary('ts_osfpal') 1531060SN/A self.console = binary('console') 1541060SN/A self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 1551060SN/A 1561060SN/A return self 1571060SN/A 1581060SN/Adef makeSparcSystem(mem_mode, mdesc = None): 1591060SN/A # Constants from iob.cc and uart8250.cc 1601060SN/A iob_man_addr = 0x9800000000 1611060SN/A uart_pio_size = 8 1621060SN/A 1631060SN/A class CowMmDisk(MmDisk): 1641060SN/A image = CowDiskImage(child=RawDiskImage(read_only=True), 1651060SN/A read_only=False) 1661060SN/A 1671060SN/A def childImage(self, ci): 1681060SN/A self.image.child.image_file = ci 1691060SN/A 1701061SN/A self = SparcSystem() 1711061SN/A if not mdesc: 1721060SN/A # generic system 1731060SN/A mdesc = SysConfig() 1741060SN/A self.readfile = mdesc.script() 1751060SN/A self.iobus = NoncoherentBus() 1761060SN/A self.membus = MemBus() 1771060SN/A self.bridge = Bridge(delay='50ns') 1781060SN/A self.t1000 = T1000() 1791060SN/A self.t1000.attachOnChipIO(self.membus) 1801061SN/A self.t1000.attachIO(self.iobus) 1811060SN/A self.physmem = SimpleMemory(range = AddrRange(Addr('1MB'), size = '64MB'), 1821060SN/A zero = True) 1831060SN/A self.physmem2 = SimpleMemory(range = AddrRange(Addr('2GB'), size ='256MB'), 1841060SN/A zero = True) 1851060SN/A self.bridge.master = self.iobus.slave 1861060SN/A self.bridge.slave = self.membus.master 1871060SN/A self.physmem.port = self.membus.master 1881060SN/A self.physmem2.port = self.membus.master 1891060SN/A self.rom.port = self.membus.master 1901060SN/A self.nvram.port = self.membus.master 1911060SN/A self.hypervisor_desc.port = self.membus.master 1921060SN/A self.partition_desc.port = self.membus.master 1931060SN/A self.intrctrl = IntrControl() 1941060SN/A self.disk0 = CowMmDisk() 1951061SN/A self.disk0.childImage(disk('disk.s10hw2')) 1961061SN/A self.disk0.pio = self.iobus.master 1971061SN/A 1981060SN/A # The puart0 and hvuart are placed on the IO bus, so create ranges 1991060SN/A # for them. The remaining IO range is rather fragmented, so poke 2001060SN/A # holes for the iob and partition descriptors etc. 2011060SN/A self.bridge.ranges = \ 2021060SN/A [ 2031060SN/A AddrRange(self.t1000.puart0.pio_addr, 2041060SN/A self.t1000.puart0.pio_addr + uart_pio_size - 1), 2051060SN/A AddrRange(self.disk0.pio_addr, 2061060SN/A self.t1000.fake_jbi.pio_addr + 2071060SN/A self.t1000.fake_jbi.pio_size - 1), 2081060SN/A AddrRange(self.t1000.fake_clk.pio_addr, 2091060SN/A iob_man_addr - 1), 2101060SN/A AddrRange(self.t1000.fake_l2_1.pio_addr, 2111060SN/A self.t1000.fake_ssi.pio_addr + 2121060SN/A self.t1000.fake_ssi.pio_size - 1), 2131060SN/A AddrRange(self.t1000.hvuart.pio_addr, 2141060SN/A self.t1000.hvuart.pio_addr + uart_pio_size - 1) 2151060SN/A ] 2161060SN/A self.reset_bin = binary('reset_new.bin') 2171060SN/A self.hypervisor_bin = binary('q_new.bin') 2181060SN/A self.openboot_bin = binary('openboot_new.bin') 2191061SN/A self.nvram_bin = binary('nvram1') 2201061SN/A self.hypervisor_desc_bin = binary('1up-hv.bin') 2211060SN/A self.partition_desc_bin = binary('1up-md.bin') 2221060SN/A 2231060SN/A self.system_port = self.membus.slave 2241060SN/A 2251060SN/A return self 2261060SN/A 2271060SN/Adef makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False): 2281060SN/A assert machine_type 2291060SN/A 2301060SN/A if bare_metal: 2311060SN/A self = ArmSystem() 2321060SN/A else: 2331060SN/A self = LinuxArmSystem() 2341060SN/A 2351060SN/A if not mdesc: 2361061SN/A # generic system 2371060SN/A mdesc = SysConfig() 2381060SN/A 2391060SN/A self.readfile = mdesc.script() 2401060SN/A self.iobus = NoncoherentBus() 2411060SN/A self.membus = MemBus() 2421060SN/A self.membus.badaddr_responder.warn_access = "warn" 2431060SN/A self.bridge = Bridge(delay='50ns') 2441060SN/A self.bridge.master = self.iobus.slave 2451060SN/A self.bridge.slave = self.membus.master 2461060SN/A 2471060SN/A self.mem_mode = mem_mode 2481060SN/A 2491060SN/A if machine_type == "RealView_PBX": 2501060SN/A self.realview = RealViewPBX() 2511060SN/A elif machine_type == "RealView_EB": 2521060SN/A self.realview = RealViewEB() 2531060SN/A elif machine_type == "VExpress_ELT": 2541060SN/A self.realview = VExpress_ELT() 2551060SN/A elif machine_type == "VExpress_EMM": 2561060SN/A self.realview = VExpress_EMM() 2571061SN/A self.load_addr_mask = 0xffffffff 2581060SN/A else: 2591060SN/A print "Unknown Machine Type" 2601060SN/A sys.exit(1) 2611060SN/A 2621061SN/A self.cf0 = CowIdeDisk(driveID='master') 2631060SN/A self.cf0.childImage(mdesc.disk()) 2641060SN/A # default to an IDE controller rather than a CF one 2651060SN/A # assuming we've got one 2661060SN/A try: 2671060SN/A self.realview.ide.disks = [self.cf0] 2681060SN/A except: 2691060SN/A self.realview.cf_ctrl.disks = [self.cf0] 2701060SN/A 2711060SN/A if bare_metal: 2721060SN/A # EOT character on UART will end the simulation 2731060SN/A self.realview.uart.end_on_eot = True 2741060SN/A self.physmem = SimpleMemory(range = AddrRange(Addr(mdesc.mem())), 2751060SN/A zero = True) 2761060SN/A else: 2771060SN/A self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8') 2781060SN/A self.machine_type = machine_type 2791061SN/A if convert.toMemorySize(mdesc.mem()) > int(self.realview.max_mem_size): 2801060SN/A print "The currently selected ARM platforms doesn't support" 2811060SN/A print " the amount of DRAM you've selected. Please try" 2821061SN/A print " another platform" 2831060SN/A sys.exit(1) 2841060SN/A 2851060SN/A boot_flags = 'earlyprintk console=ttyAMA0 lpj=19988480 norandmaps ' + \ 2861060SN/A 'rw loglevel=8 mem=%s root=/dev/sda1' % mdesc.mem() 2871060SN/A 2881060SN/A self.physmem = SimpleMemory(range = 2891060SN/A AddrRange(self.realview.mem_start_addr, 2901060SN/A size = mdesc.mem()), 2911060SN/A conf_table_reported = True) 2921061SN/A self.realview.setupBootLoader(self.membus, self, binary) 2931061SN/A self.gic_cpu_addr = self.realview.gic.cpu_addr 2941060SN/A self.flags_addr = self.realview.realview_io.pio_addr + 0x30 2951060SN/A 2961060SN/A if mdesc.disk().lower().count('android'): 2971060SN/A boot_flags += " init=/init " 2981060SN/A self.boot_osflags = boot_flags 2991060SN/A 3001060SN/A self.physmem.port = self.membus.master 3011060SN/A self.realview.attachOnChipIO(self.membus, self.bridge) 3021060SN/A self.realview.attachIO(self.iobus) 3031060SN/A self.intrctrl = IntrControl() 3041060SN/A self.terminal = Terminal() 3051060SN/A self.vncserver = VncServer() 3061060SN/A 3071060SN/A self.system_port = self.membus.slave 3081060SN/A 3091060SN/A return self 3101060SN/A 3111060SN/A 3121060SN/Adef makeLinuxMipsSystem(mem_mode, mdesc = None): 3131060SN/A class BaseMalta(Malta): 3141060SN/A ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 3151060SN/A ide = IdeController(disks=[Parent.disk0, Parent.disk2], 3161060SN/A pci_func=0, pci_dev=0, pci_bus=0) 3171060SN/A 3181060SN/A self = LinuxMipsSystem() 3191060SN/A if not mdesc: 3201061SN/A # generic system 3211061SN/A mdesc = SysConfig() 3221060SN/A self.readfile = mdesc.script() 3231060SN/A self.iobus = NoncoherentBus() 3241060SN/A self.membus = MemBus() 3251060SN/A self.bridge = Bridge(delay='50ns') 3261061SN/A self.physmem = SimpleMemory(range = AddrRange('1GB')) 3271060SN/A self.bridge.master = self.iobus.slave 3281060SN/A self.bridge.slave = self.membus.master 3291060SN/A self.physmem.port = self.membus.master 3301060SN/A self.disk0 = CowIdeDisk(driveID='master') 3311061SN/A self.disk2 = CowIdeDisk(driveID='master') 3321060SN/A self.disk0.childImage(mdesc.disk()) 3331060SN/A self.disk2.childImage(disk('linux-bigswap2.img')) 3341060SN/A self.malta = BaseMalta() 3351060SN/A self.malta.attachIO(self.iobus) 3361060SN/A self.malta.ide.pio = self.iobus.master 3371060SN/A self.malta.ide.config = self.iobus.master 3381060SN/A self.malta.ide.dma = self.iobus.slave 3391060SN/A self.malta.ethernet.pio = self.iobus.master 3401060SN/A self.malta.ethernet.config = self.iobus.master 3411060SN/A self.malta.ethernet.dma = self.iobus.slave 3421060SN/A self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 3431060SN/A read_only = True)) 3441060SN/A self.intrctrl = IntrControl() 3451060SN/A self.mem_mode = mem_mode 3461060SN/A self.terminal = Terminal() 3471060SN/A self.kernel = binary('mips/vmlinux') 3481060SN/A self.console = binary('mips/console') 349 self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 350 351 self.system_port = self.membus.slave 352 353 return self 354 355def x86IOAddress(port): 356 IO_address_space_base = 0x8000000000000000 357 return IO_address_space_base + port 358 359def connectX86ClassicSystem(x86_sys, numCPUs): 360 # Constants similar to x86_traits.hh 361 IO_address_space_base = 0x8000000000000000 362 pci_config_address_space_base = 0xc000000000000000 363 interrupts_address_space_base = 0xa000000000000000 364 APIC_range_size = 1 << 12; 365 366 x86_sys.membus = MemBus() 367 x86_sys.physmem.port = x86_sys.membus.master 368 369 # North Bridge 370 x86_sys.iobus = NoncoherentBus() 371 x86_sys.bridge = Bridge(delay='50ns') 372 x86_sys.bridge.master = x86_sys.iobus.slave 373 x86_sys.bridge.slave = x86_sys.membus.master 374 # Allow the bridge to pass through the IO APIC (two pages), 375 # everything in the IO address range up to the local APIC, and 376 # then the entire PCI address space and beyond 377 x86_sys.bridge.ranges = \ 378 [ 379 AddrRange(x86_sys.pc.south_bridge.io_apic.pio_addr, 380 x86_sys.pc.south_bridge.io_apic.pio_addr + 381 APIC_range_size - 1), 382 AddrRange(IO_address_space_base, 383 interrupts_address_space_base - 1), 384 AddrRange(pci_config_address_space_base, 385 Addr.max) 386 ] 387 388 # Create a bridge from the IO bus to the memory bus to allow access to 389 # the local APIC (two pages) 390 x86_sys.apicbridge = Bridge(delay='50ns') 391 x86_sys.apicbridge.slave = x86_sys.iobus.master 392 x86_sys.apicbridge.master = x86_sys.membus.slave 393 x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base, 394 interrupts_address_space_base + 395 numCPUs * APIC_range_size 396 - 1)] 397 398 # connect the io bus 399 x86_sys.pc.attachIO(x86_sys.iobus) 400 401 x86_sys.system_port = x86_sys.membus.slave 402 403def connectX86RubySystem(x86_sys): 404 # North Bridge 405 x86_sys.piobus = NoncoherentBus() 406 407 # 408 # Pio functional accesses from devices need direct access to memory 409 # RubyPort currently does support functional accesses. Therefore provide 410 # the piobus a direct connection to physical memory 411 # 412 x86_sys.piobus.master = x86_sys.physmem.port 413 # add the ide to the list of dma devices that later need to attach to 414 # dma controllers 415 x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma] 416 x86_sys.pc.attachIO(x86_sys.piobus, x86_sys._dma_ports) 417 418 419def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None, Ruby = False): 420 if self == None: 421 self = X86System() 422 423 if not mdesc: 424 # generic system 425 mdesc = SysConfig() 426 self.readfile = mdesc.script() 427 428 self.mem_mode = mem_mode 429 430 # Physical memory 431 self.physmem = SimpleMemory(range = AddrRange(mdesc.mem())) 432 433 # Platform 434 self.pc = Pc() 435 436 # Create and connect the busses required by each memory system 437 if Ruby: 438 connectX86RubySystem(self) 439 else: 440 connectX86ClassicSystem(self, numCPUs) 441 442 self.intrctrl = IntrControl() 443 444 # Disks 445 disk0 = CowIdeDisk(driveID='master') 446 disk2 = CowIdeDisk(driveID='master') 447 disk0.childImage(mdesc.disk()) 448 disk2.childImage(disk('linux-bigswap2.img')) 449 self.pc.south_bridge.ide.disks = [disk0, disk2] 450 451 # Add in a Bios information structure. 452 structures = [X86SMBiosBiosInformation()] 453 self.smbios_table.structures = structures 454 455 # Set up the Intel MP table 456 base_entries = [] 457 ext_entries = [] 458 for i in xrange(numCPUs): 459 bp = X86IntelMPProcessor( 460 local_apic_id = i, 461 local_apic_version = 0x14, 462 enable = True, 463 bootstrap = (i == 0)) 464 base_entries.append(bp) 465 io_apic = X86IntelMPIOAPIC( 466 id = numCPUs, 467 version = 0x11, 468 enable = True, 469 address = 0xfec00000) 470 self.pc.south_bridge.io_apic.apic_id = io_apic.id 471 base_entries.append(io_apic) 472 isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA') 473 base_entries.append(isa_bus) 474 pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI') 475 base_entries.append(pci_bus) 476 connect_busses = X86IntelMPBusHierarchy(bus_id=0, 477 subtractive_decode=True, parent_bus=1) 478 ext_entries.append(connect_busses) 479 pci_dev4_inta = X86IntelMPIOIntAssignment( 480 interrupt_type = 'INT', 481 polarity = 'ConformPolarity', 482 trigger = 'ConformTrigger', 483 source_bus_id = 1, 484 source_bus_irq = 0 + (4 << 2), 485 dest_io_apic_id = io_apic.id, 486 dest_io_apic_intin = 16) 487 base_entries.append(pci_dev4_inta) 488 def assignISAInt(irq, apicPin): 489 assign_8259_to_apic = X86IntelMPIOIntAssignment( 490 interrupt_type = 'ExtInt', 491 polarity = 'ConformPolarity', 492 trigger = 'ConformTrigger', 493 source_bus_id = 0, 494 source_bus_irq = irq, 495 dest_io_apic_id = io_apic.id, 496 dest_io_apic_intin = 0) 497 base_entries.append(assign_8259_to_apic) 498 assign_to_apic = X86IntelMPIOIntAssignment( 499 interrupt_type = 'INT', 500 polarity = 'ConformPolarity', 501 trigger = 'ConformTrigger', 502 source_bus_id = 0, 503 source_bus_irq = irq, 504 dest_io_apic_id = io_apic.id, 505 dest_io_apic_intin = apicPin) 506 base_entries.append(assign_to_apic) 507 assignISAInt(0, 2) 508 assignISAInt(1, 1) 509 for i in range(3, 15): 510 assignISAInt(i, i) 511 self.intel_mp_table.base_entries = base_entries 512 self.intel_mp_table.ext_entries = ext_entries 513 514def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None, Ruby = False): 515 self = LinuxX86System() 516 517 # Build up the x86 system and then specialize it for Linux 518 makeX86System(mem_mode, numCPUs, mdesc, self, Ruby) 519 520 # We assume below that there's at least 1MB of memory. We'll require 2 521 # just to avoid corner cases. 522 assert(self.physmem.range.second.getValue() >= 0x200000) 523 524 self.e820_table.entries = \ 525 [ 526 # Mark the first megabyte of memory as reserved 527 X86E820Entry(addr = 0, size = '1MB', range_type = 2), 528 # Mark the rest as available 529 X86E820Entry(addr = 0x100000, 530 size = '%dB' % (self.physmem.range.second - 0x100000 + 1), 531 range_type = 1) 532 ] 533 534 # Command line 535 self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \ 536 'root=/dev/hda1' 537 return self 538 539 540def makeDualRoot(full_system, testSystem, driveSystem, dumpfile): 541 self = Root(full_system = full_system) 542 self.testsys = testSystem 543 self.drivesys = driveSystem 544 self.etherlink = EtherLink() 545 self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 546 self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 547 548 if hasattr(testSystem, 'realview'): 549 self.etherlink.int0 = Parent.testsys.realview.ethernet.interface 550 self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface 551 elif hasattr(testSystem, 'tsunami'): 552 self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 553 self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 554 else: 555 fatal("Don't know how to connect these system together") 556 557 if dumpfile: 558 self.etherdump = EtherDump(file=dumpfile) 559 self.etherlink.dump = Parent.etherdump 560 561 return self 562