FSConfig.py revision 8713
18706Sandreas.hansson@arm.com# Copyright (c) 2010-2012 ARM Limited 27586SAli.Saidi@arm.com# All rights reserved. 37586SAli.Saidi@arm.com# 47586SAli.Saidi@arm.com# The license below extends only to copyright in the software and shall 57586SAli.Saidi@arm.com# not be construed as granting a license to any other intellectual 67586SAli.Saidi@arm.com# property including but not limited to intellectual property relating 77586SAli.Saidi@arm.com# to a hardware implementation of the functionality of the software 87586SAli.Saidi@arm.com# licensed hereunder. You may use the software subject to the license 97586SAli.Saidi@arm.com# terms below provided that you ensure that this notice is replicated 107586SAli.Saidi@arm.com# unmodified and in its entirety in all distributions of the software, 117586SAli.Saidi@arm.com# modified or unmodified, in source code or in binary form. 127586SAli.Saidi@arm.com# 137905SBrad.Beckmann@amd.com# Copyright (c) 2010-2011 Advanced Micro Devices, Inc. 145323Sgblack@eecs.umich.edu# Copyright (c) 2006-2008 The Regents of The University of Michigan 152934Sktlim@umich.edu# All rights reserved. 162934Sktlim@umich.edu# 172934Sktlim@umich.edu# Redistribution and use in source and binary forms, with or without 182934Sktlim@umich.edu# modification, are permitted provided that the following conditions are 192934Sktlim@umich.edu# met: redistributions of source code must retain the above copyright 202934Sktlim@umich.edu# notice, this list of conditions and the following disclaimer; 212934Sktlim@umich.edu# redistributions in binary form must reproduce the above copyright 222934Sktlim@umich.edu# notice, this list of conditions and the following disclaimer in the 232934Sktlim@umich.edu# documentation and/or other materials provided with the distribution; 242934Sktlim@umich.edu# neither the name of the copyright holders nor the names of its 252934Sktlim@umich.edu# contributors may be used to endorse or promote products derived from 262934Sktlim@umich.edu# this software without specific prior written permission. 272934Sktlim@umich.edu# 282934Sktlim@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292934Sktlim@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302934Sktlim@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312934Sktlim@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322934Sktlim@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332934Sktlim@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342934Sktlim@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352934Sktlim@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362934Sktlim@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372934Sktlim@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382934Sktlim@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392934Sktlim@umich.edu# 402934Sktlim@umich.edu# Authors: Kevin Lim 412934Sktlim@umich.edu 422934Sktlim@umich.edufrom m5.objects import * 432995Ssaidi@eecs.umich.edufrom Benchmarks import * 448528SAli.Saidi@ARM.comfrom m5.util import convert 452934Sktlim@umich.edu 462934Sktlim@umich.educlass CowIdeDisk(IdeDisk): 472934Sktlim@umich.edu image = CowDiskImage(child=RawDiskImage(read_only=True), 482934Sktlim@umich.edu read_only=False) 492934Sktlim@umich.edu 502934Sktlim@umich.edu def childImage(self, ci): 512934Sktlim@umich.edu self.image.child.image_file = ci 522934Sktlim@umich.edu 536122SSteve.Reinhardt@amd.comclass MemBus(Bus): 546122SSteve.Reinhardt@amd.com badaddr_responder = BadAddr() 556122SSteve.Reinhardt@amd.com default = Self.badaddr_responder.pio 566122SSteve.Reinhardt@amd.com 576122SSteve.Reinhardt@amd.com 584520Ssaidi@eecs.umich.edudef makeLinuxAlphaSystem(mem_mode, mdesc = None): 598713Sandreas.hansson@arm.com IO_address_space_base = 0x80000000000 604520Ssaidi@eecs.umich.edu class BaseTsunami(Tsunami): 614982Ssaidi@eecs.umich.edu ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 624520Ssaidi@eecs.umich.edu ide = IdeController(disks=[Parent.disk0, Parent.disk2], 634520Ssaidi@eecs.umich.edu pci_func=0, pci_dev=0, pci_bus=0) 642934Sktlim@umich.edu 652934Sktlim@umich.edu self = LinuxAlphaSystem() 663005Sstever@eecs.umich.edu if not mdesc: 673005Sstever@eecs.umich.edu # generic system 683304Sstever@eecs.umich.edu mdesc = SysConfig() 692995Ssaidi@eecs.umich.edu self.readfile = mdesc.script() 702934Sktlim@umich.edu self.iobus = Bus(bus_id=0) 716122SSteve.Reinhardt@amd.com self.membus = MemBus(bus_id=1) 728713Sandreas.hansson@arm.com # By default the bridge responds to all addresses above the I/O 738713Sandreas.hansson@arm.com # base address (including the PCI config space) 748713Sandreas.hansson@arm.com self.bridge = Bridge(delay='50ns', nack_delay='4ns', 758713Sandreas.hansson@arm.com ranges = [AddrRange(IO_address_space_base, Addr.max)]) 765266Sksewell@umich.edu self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) 778713Sandreas.hansson@arm.com self.bridge.master = self.iobus.port 788713Sandreas.hansson@arm.com self.bridge.slave = self.membus.port 792934Sktlim@umich.edu self.physmem.port = self.membus.port 802934Sktlim@umich.edu self.disk0 = CowIdeDisk(driveID='master') 812934Sktlim@umich.edu self.disk2 = CowIdeDisk(driveID='master') 822995Ssaidi@eecs.umich.edu self.disk0.childImage(mdesc.disk()) 832934Sktlim@umich.edu self.disk2.childImage(disk('linux-bigswap2.img')) 842934Sktlim@umich.edu self.tsunami = BaseTsunami() 852934Sktlim@umich.edu self.tsunami.attachIO(self.iobus) 862934Sktlim@umich.edu self.tsunami.ide.pio = self.iobus.port 872934Sktlim@umich.edu self.tsunami.ethernet.pio = self.iobus.port 882995Ssaidi@eecs.umich.edu self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 892934Sktlim@umich.edu read_only = True)) 902934Sktlim@umich.edu self.intrctrl = IntrControl() 912953Sktlim@umich.edu self.mem_mode = mem_mode 925478Snate@binkert.org self.terminal = Terminal() 932934Sktlim@umich.edu self.kernel = binary('vmlinux') 943449Shsul@eecs.umich.edu self.pal = binary('ts_osfpal') 952934Sktlim@umich.edu self.console = binary('console') 962934Sktlim@umich.edu self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 972934Sktlim@umich.edu 988706Sandreas.hansson@arm.com self.system_port = self.membus.port 998706Sandreas.hansson@arm.com 1002934Sktlim@umich.edu return self 1012934Sktlim@umich.edu 1027014SBrad.Beckmann@amd.comdef makeLinuxAlphaRubySystem(mem_mode, mdesc = None): 1036765SBrad.Beckmann@amd.com class BaseTsunami(Tsunami): 1046765SBrad.Beckmann@amd.com ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 1056765SBrad.Beckmann@amd.com ide = IdeController(disks=[Parent.disk0, Parent.disk2], 1066765SBrad.Beckmann@amd.com pci_func=0, pci_dev=0, pci_bus=0) 1076765SBrad.Beckmann@amd.com 1087014SBrad.Beckmann@amd.com physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) 1097014SBrad.Beckmann@amd.com self = LinuxAlphaSystem(physmem = physmem) 1106765SBrad.Beckmann@amd.com if not mdesc: 1116765SBrad.Beckmann@amd.com # generic system 1126765SBrad.Beckmann@amd.com mdesc = SysConfig() 1136765SBrad.Beckmann@amd.com self.readfile = mdesc.script() 1146765SBrad.Beckmann@amd.com 1156765SBrad.Beckmann@amd.com # Create pio bus to connect all device pio ports to rubymem's pio port 1166765SBrad.Beckmann@amd.com self.piobus = Bus(bus_id=0) 1176893SBrad.Beckmann@amd.com 1186893SBrad.Beckmann@amd.com # 1196893SBrad.Beckmann@amd.com # Pio functional accesses from devices need direct access to memory 1206893SBrad.Beckmann@amd.com # RubyPort currently does support functional accesses. Therefore provide 1216893SBrad.Beckmann@amd.com # the piobus a direct connection to physical memory 1226893SBrad.Beckmann@amd.com # 1237014SBrad.Beckmann@amd.com self.piobus.port = physmem.port 1246893SBrad.Beckmann@amd.com 1256765SBrad.Beckmann@amd.com self.disk0 = CowIdeDisk(driveID='master') 1266765SBrad.Beckmann@amd.com self.disk2 = CowIdeDisk(driveID='master') 1276765SBrad.Beckmann@amd.com self.disk0.childImage(mdesc.disk()) 1286765SBrad.Beckmann@amd.com self.disk2.childImage(disk('linux-bigswap2.img')) 1296765SBrad.Beckmann@amd.com self.tsunami = BaseTsunami() 1306765SBrad.Beckmann@amd.com self.tsunami.attachIO(self.piobus) 1316765SBrad.Beckmann@amd.com self.tsunami.ide.pio = self.piobus.port 1326765SBrad.Beckmann@amd.com self.tsunami.ethernet.pio = self.piobus.port 1336765SBrad.Beckmann@amd.com 1346893SBrad.Beckmann@amd.com # 1357633SBrad.Beckmann@amd.com # Store the dma devices for later connection to dma ruby ports. 1367633SBrad.Beckmann@amd.com # Append an underscore to dma_devices to avoid the SimObjectVector check. 1376893SBrad.Beckmann@amd.com # 1387633SBrad.Beckmann@amd.com self._dma_devices = [self.tsunami.ide, self.tsunami.ethernet] 1396765SBrad.Beckmann@amd.com 1406765SBrad.Beckmann@amd.com self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 1416765SBrad.Beckmann@amd.com read_only = True)) 1426765SBrad.Beckmann@amd.com self.intrctrl = IntrControl() 1436765SBrad.Beckmann@amd.com self.mem_mode = mem_mode 1446765SBrad.Beckmann@amd.com self.terminal = Terminal() 1456765SBrad.Beckmann@amd.com self.kernel = binary('vmlinux') 1466765SBrad.Beckmann@amd.com self.pal = binary('ts_osfpal') 1476765SBrad.Beckmann@amd.com self.console = binary('console') 1486765SBrad.Beckmann@amd.com self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 1496765SBrad.Beckmann@amd.com 1506765SBrad.Beckmann@amd.com return self 1516765SBrad.Beckmann@amd.com 1523584Ssaidi@eecs.umich.edudef makeSparcSystem(mem_mode, mdesc = None): 1538713Sandreas.hansson@arm.com # Constants from iob.cc and uart8250.cc 1548713Sandreas.hansson@arm.com iob_man_addr = 0x9800000000 1558713Sandreas.hansson@arm.com uart_pio_size = 8 1568713Sandreas.hansson@arm.com 1574486Sbinkertn@umich.edu class CowMmDisk(MmDisk): 1584486Sbinkertn@umich.edu image = CowDiskImage(child=RawDiskImage(read_only=True), 1594486Sbinkertn@umich.edu read_only=False) 1604486Sbinkertn@umich.edu 1614486Sbinkertn@umich.edu def childImage(self, ci): 1624486Sbinkertn@umich.edu self.image.child.image_file = ci 1634486Sbinkertn@umich.edu 1643584Ssaidi@eecs.umich.edu self = SparcSystem() 1653584Ssaidi@eecs.umich.edu if not mdesc: 1663584Ssaidi@eecs.umich.edu # generic system 1673584Ssaidi@eecs.umich.edu mdesc = SysConfig() 1683584Ssaidi@eecs.umich.edu self.readfile = mdesc.script() 1693743Sgblack@eecs.umich.edu self.iobus = Bus(bus_id=0) 1706122SSteve.Reinhardt@amd.com self.membus = MemBus(bus_id=1) 1714972Ssaidi@eecs.umich.edu self.bridge = Bridge(delay='50ns', nack_delay='4ns') 1723743Sgblack@eecs.umich.edu self.t1000 = T1000() 1734104Ssaidi@eecs.umich.edu self.t1000.attachOnChipIO(self.membus) 1743743Sgblack@eecs.umich.edu self.t1000.attachIO(self.iobus) 1753823Ssaidi@eecs.umich.edu self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True) 1763814Ssaidi@eecs.umich.edu self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True) 1778713Sandreas.hansson@arm.com self.bridge.master = self.iobus.port 1788713Sandreas.hansson@arm.com self.bridge.slave = self.membus.port 1793584Ssaidi@eecs.umich.edu self.physmem.port = self.membus.port 1803814Ssaidi@eecs.umich.edu self.physmem2.port = self.membus.port 1813584Ssaidi@eecs.umich.edu self.rom.port = self.membus.port 1823745Sgblack@eecs.umich.edu self.nvram.port = self.membus.port 1833745Sgblack@eecs.umich.edu self.hypervisor_desc.port = self.membus.port 1843745Sgblack@eecs.umich.edu self.partition_desc.port = self.membus.port 1853584Ssaidi@eecs.umich.edu self.intrctrl = IntrControl() 1863898Ssaidi@eecs.umich.edu self.disk0 = CowMmDisk() 1873898Ssaidi@eecs.umich.edu self.disk0.childImage(disk('disk.s10hw2')) 1883898Ssaidi@eecs.umich.edu self.disk0.pio = self.iobus.port 1898713Sandreas.hansson@arm.com 1908713Sandreas.hansson@arm.com # The puart0 and hvuart are placed on the IO bus, so create ranges 1918713Sandreas.hansson@arm.com # for them. The remaining IO range is rather fragmented, so poke 1928713Sandreas.hansson@arm.com # holes for the iob and partition descriptors etc. 1938713Sandreas.hansson@arm.com self.bridge.ranges = \ 1948713Sandreas.hansson@arm.com [ 1958713Sandreas.hansson@arm.com AddrRange(self.t1000.puart0.pio_addr, 1968713Sandreas.hansson@arm.com self.t1000.puart0.pio_addr + uart_pio_size - 1), 1978713Sandreas.hansson@arm.com AddrRange(self.disk0.pio_addr, 1988713Sandreas.hansson@arm.com self.t1000.fake_jbi.pio_addr + 1998713Sandreas.hansson@arm.com self.t1000.fake_jbi.pio_size - 1), 2008713Sandreas.hansson@arm.com AddrRange(self.t1000.fake_clk.pio_addr, 2018713Sandreas.hansson@arm.com iob_man_addr - 1), 2028713Sandreas.hansson@arm.com AddrRange(self.t1000.fake_l2_1.pio_addr, 2038713Sandreas.hansson@arm.com self.t1000.fake_ssi.pio_addr + 2048713Sandreas.hansson@arm.com self.t1000.fake_ssi.pio_size - 1), 2058713Sandreas.hansson@arm.com AddrRange(self.t1000.hvuart.pio_addr, 2068713Sandreas.hansson@arm.com self.t1000.hvuart.pio_addr + uart_pio_size - 1) 2078713Sandreas.hansson@arm.com ] 2084103Ssaidi@eecs.umich.edu self.reset_bin = binary('reset_new.bin') 2094103Ssaidi@eecs.umich.edu self.hypervisor_bin = binary('q_new.bin') 2104103Ssaidi@eecs.umich.edu self.openboot_bin = binary('openboot_new.bin') 2113745Sgblack@eecs.umich.edu self.nvram_bin = binary('nvram1') 2123745Sgblack@eecs.umich.edu self.hypervisor_desc_bin = binary('1up-hv.bin') 2133745Sgblack@eecs.umich.edu self.partition_desc_bin = binary('1up-md.bin') 2143584Ssaidi@eecs.umich.edu 2158706Sandreas.hansson@arm.com self.system_port = self.membus.port 2168706Sandreas.hansson@arm.com 2173584Ssaidi@eecs.umich.edu return self 2183584Ssaidi@eecs.umich.edu 2198061SAli.Saidi@ARM.comdef makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False): 2208061SAli.Saidi@ARM.com assert machine_type 2218061SAli.Saidi@ARM.com 2227586SAli.Saidi@arm.com if bare_metal: 2237586SAli.Saidi@arm.com self = ArmSystem() 2247586SAli.Saidi@arm.com else: 2257586SAli.Saidi@arm.com self = LinuxArmSystem() 2267586SAli.Saidi@arm.com 2277586SAli.Saidi@arm.com if not mdesc: 2287586SAli.Saidi@arm.com # generic system 2297586SAli.Saidi@arm.com mdesc = SysConfig() 2307586SAli.Saidi@arm.com 2317586SAli.Saidi@arm.com self.readfile = mdesc.script() 2327586SAli.Saidi@arm.com self.iobus = Bus(bus_id=0) 2337586SAli.Saidi@arm.com self.membus = MemBus(bus_id=1) 2347586SAli.Saidi@arm.com self.membus.badaddr_responder.warn_access = "warn" 2357586SAli.Saidi@arm.com self.bridge = Bridge(delay='50ns', nack_delay='4ns') 2368713Sandreas.hansson@arm.com self.bridge.master = self.iobus.port 2378713Sandreas.hansson@arm.com self.bridge.slave = self.membus.port 2387586SAli.Saidi@arm.com 2397586SAli.Saidi@arm.com self.mem_mode = mem_mode 2407586SAli.Saidi@arm.com 2417586SAli.Saidi@arm.com if machine_type == "RealView_PBX": 2427586SAli.Saidi@arm.com self.realview = RealViewPBX() 2437586SAli.Saidi@arm.com elif machine_type == "RealView_EB": 2447586SAli.Saidi@arm.com self.realview = RealViewEB() 2458525SAli.Saidi@ARM.com elif machine_type == "VExpress_ELT": 2468525SAli.Saidi@ARM.com self.realview = VExpress_ELT() 2477586SAli.Saidi@arm.com else: 2487586SAli.Saidi@arm.com print "Unknown Machine Type" 2497586SAli.Saidi@arm.com sys.exit(1) 2507586SAli.Saidi@arm.com 2518528SAli.Saidi@ARM.com self.cf0 = CowIdeDisk(driveID='master') 2528528SAli.Saidi@ARM.com self.cf0.childImage(mdesc.disk()) 2538528SAli.Saidi@ARM.com # default to an IDE controller rather than a CF one 2548528SAli.Saidi@ARM.com # assuming we've got one 2558528SAli.Saidi@ARM.com try: 2568528SAli.Saidi@ARM.com self.realview.ide.disks = [self.cf0] 2578528SAli.Saidi@ARM.com except: 2588528SAli.Saidi@ARM.com self.realview.cf_ctrl.disks = [self.cf0] 2598528SAli.Saidi@ARM.com 2608061SAli.Saidi@ARM.com if bare_metal: 2618061SAli.Saidi@ARM.com # EOT character on UART will end the simulation 2628061SAli.Saidi@ARM.com self.realview.uart.end_on_eot = True 2638528SAli.Saidi@ARM.com self.physmem = PhysicalMemory(range = AddrRange(Addr(mdesc.mem())), 2648212SAli.Saidi@ARM.com zero = True) 2658061SAli.Saidi@ARM.com else: 2668528SAli.Saidi@ARM.com self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8') 2677586SAli.Saidi@arm.com self.machine_type = machine_type 2688528SAli.Saidi@ARM.com if convert.toMemorySize(mdesc.mem()) > convert.toMemorySize('256MB'): 2698528SAli.Saidi@ARM.com print "The currently implemented ARM platforms only easily support 256MB of DRAM" 2708528SAli.Saidi@ARM.com print "It might be possible to get some more by using 256MB@0x30000000, but this" 2718528SAli.Saidi@ARM.com print "is untested and may require some heroics" 2728528SAli.Saidi@ARM.com 2738212SAli.Saidi@ARM.com boot_flags = 'earlyprintk console=ttyAMA0 lpj=19988480 norandmaps ' + \ 2748528SAli.Saidi@ARM.com 'rw loglevel=8 mem=%s root=/dev/sda1' % mdesc.mem() 2758528SAli.Saidi@ARM.com 2768528SAli.Saidi@ARM.com self.physmem = PhysicalMemory(range = AddrRange(Addr(mdesc.mem())), 2778528SAli.Saidi@ARM.com zero = True) 2788528SAli.Saidi@ARM.com self.nvmem = PhysicalMemory(range = AddrRange(Addr('2GB'), 2798528SAli.Saidi@ARM.com size = '64MB'), zero = True) 2808528SAli.Saidi@ARM.com self.nvmem.port = self.membus.port 2818528SAli.Saidi@ARM.com self.boot_loader = binary('boot.arm') 2828528SAli.Saidi@ARM.com self.boot_loader_mem = self.nvmem 2838528SAli.Saidi@ARM.com self.gic_cpu_addr = self.realview.gic.cpu_addr 2848528SAli.Saidi@ARM.com self.flags_addr = self.realview.realview_io.pio_addr + 0x30 2858287SAli.Saidi@ARM.com 2868643Satgutier@umich.edu if mdesc.disk().lower().count('android'): 2878595SAli.Saidi@ARM.com boot_flags += " init=/init " 2888212SAli.Saidi@ARM.com self.boot_osflags = boot_flags 2897586SAli.Saidi@arm.com 2908145SAli.Saidi@ARM.com self.physmem.port = self.membus.port 2918713Sandreas.hansson@arm.com self.realview.attachOnChipIO(self.membus, self.bridge) 2927586SAli.Saidi@arm.com self.realview.attachIO(self.iobus) 2937586SAli.Saidi@arm.com self.intrctrl = IntrControl() 2947586SAli.Saidi@arm.com self.terminal = Terminal() 2957949SAli.Saidi@ARM.com self.vncserver = VncServer() 2967586SAli.Saidi@arm.com 2978706Sandreas.hansson@arm.com self.system_port = self.membus.port 2988706Sandreas.hansson@arm.com 2997586SAli.Saidi@arm.com return self 3007586SAli.Saidi@arm.com 3017586SAli.Saidi@arm.com 3025222Sksewell@umich.edudef makeLinuxMipsSystem(mem_mode, mdesc = None): 3035222Sksewell@umich.edu class BaseMalta(Malta): 3045222Sksewell@umich.edu ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 3055222Sksewell@umich.edu ide = IdeController(disks=[Parent.disk0, Parent.disk2], 3065222Sksewell@umich.edu pci_func=0, pci_dev=0, pci_bus=0) 3075222Sksewell@umich.edu 3085222Sksewell@umich.edu self = LinuxMipsSystem() 3095222Sksewell@umich.edu if not mdesc: 3105222Sksewell@umich.edu # generic system 3115222Sksewell@umich.edu mdesc = SysConfig() 3125222Sksewell@umich.edu self.readfile = mdesc.script() 3135222Sksewell@umich.edu self.iobus = Bus(bus_id=0) 3146122SSteve.Reinhardt@amd.com self.membus = MemBus(bus_id=1) 3155222Sksewell@umich.edu self.bridge = Bridge(delay='50ns', nack_delay='4ns') 3165222Sksewell@umich.edu self.physmem = PhysicalMemory(range = AddrRange('1GB')) 3178713Sandreas.hansson@arm.com self.bridge.master = self.iobus.port 3188713Sandreas.hansson@arm.com self.bridge.slave = self.membus.port 3195222Sksewell@umich.edu self.physmem.port = self.membus.port 3205222Sksewell@umich.edu self.disk0 = CowIdeDisk(driveID='master') 3215222Sksewell@umich.edu self.disk2 = CowIdeDisk(driveID='master') 3225222Sksewell@umich.edu self.disk0.childImage(mdesc.disk()) 3235222Sksewell@umich.edu self.disk2.childImage(disk('linux-bigswap2.img')) 3245222Sksewell@umich.edu self.malta = BaseMalta() 3255222Sksewell@umich.edu self.malta.attachIO(self.iobus) 3265222Sksewell@umich.edu self.malta.ide.pio = self.iobus.port 3275222Sksewell@umich.edu self.malta.ethernet.pio = self.iobus.port 3285222Sksewell@umich.edu self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 3295222Sksewell@umich.edu read_only = True)) 3305222Sksewell@umich.edu self.intrctrl = IntrControl() 3315222Sksewell@umich.edu self.mem_mode = mem_mode 3325478Snate@binkert.org self.terminal = Terminal() 3335222Sksewell@umich.edu self.kernel = binary('mips/vmlinux') 3345222Sksewell@umich.edu self.console = binary('mips/console') 3355222Sksewell@umich.edu self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 3365222Sksewell@umich.edu 3378706Sandreas.hansson@arm.com self.system_port = self.membus.port 3388706Sandreas.hansson@arm.com 3395222Sksewell@umich.edu return self 3405222Sksewell@umich.edu 3415323Sgblack@eecs.umich.edudef x86IOAddress(port): 3425357Sgblack@eecs.umich.edu IO_address_space_base = 0x8000000000000000 3438323Ssteve.reinhardt@amd.com return IO_address_space_base + port 3445323Sgblack@eecs.umich.edu 3457905SBrad.Beckmann@amd.comdef connectX86ClassicSystem(x86_sys): 3468713Sandreas.hansson@arm.com # Constants similar to x86_traits.hh 3478713Sandreas.hansson@arm.com IO_address_space_base = 0x8000000000000000 3488713Sandreas.hansson@arm.com pci_config_address_space_base = 0xc000000000000000 3498713Sandreas.hansson@arm.com interrupts_address_space_base = 0xa000000000000000 3508713Sandreas.hansson@arm.com APIC_range_size = 1 << 12; 3518713Sandreas.hansson@arm.com 3527905SBrad.Beckmann@amd.com x86_sys.membus = MemBus(bus_id=1) 3537905SBrad.Beckmann@amd.com x86_sys.physmem.port = x86_sys.membus.port 3547905SBrad.Beckmann@amd.com 3557905SBrad.Beckmann@amd.com # North Bridge 3567905SBrad.Beckmann@amd.com x86_sys.iobus = Bus(bus_id=0) 3577905SBrad.Beckmann@amd.com x86_sys.bridge = Bridge(delay='50ns', nack_delay='4ns') 3588713Sandreas.hansson@arm.com x86_sys.bridge.master = x86_sys.iobus.port 3598713Sandreas.hansson@arm.com x86_sys.bridge.slave = x86_sys.membus.port 3608713Sandreas.hansson@arm.com # Allow the bridge to pass through the IO APIC (two pages), 3618713Sandreas.hansson@arm.com # everything in the IO address range up to the local APIC, and 3628713Sandreas.hansson@arm.com # then the entire PCI address space and beyond 3638713Sandreas.hansson@arm.com x86_sys.bridge.ranges = \ 3648713Sandreas.hansson@arm.com [ 3658713Sandreas.hansson@arm.com AddrRange(x86_sys.pc.south_bridge.io_apic.pio_addr, 3668713Sandreas.hansson@arm.com x86_sys.pc.south_bridge.io_apic.pio_addr + 3678713Sandreas.hansson@arm.com APIC_range_size - 1), 3688713Sandreas.hansson@arm.com AddrRange(IO_address_space_base, 3698713Sandreas.hansson@arm.com interrupts_address_space_base - 1), 3708713Sandreas.hansson@arm.com AddrRange(pci_config_address_space_base, 3718713Sandreas.hansson@arm.com Addr.max) 3728713Sandreas.hansson@arm.com ] 3738713Sandreas.hansson@arm.com 3748713Sandreas.hansson@arm.com # Create a bridge from the IO bus to the memory bus to allow access to 3758713Sandreas.hansson@arm.com # the local APIC (two pages) 3768713Sandreas.hansson@arm.com x86_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns') 3778713Sandreas.hansson@arm.com x86_sys.iobridge.slave = x86_sys.iobus.port 3788713Sandreas.hansson@arm.com x86_sys.iobridge.master = x86_sys.membus.port 3798713Sandreas.hansson@arm.com x86_sys.iobridge.ranges = [AddrRange(interrupts_address_space_base, 3808713Sandreas.hansson@arm.com interrupts_address_space_base + 3818713Sandreas.hansson@arm.com APIC_range_size - 1)] 3827905SBrad.Beckmann@amd.com 3837905SBrad.Beckmann@amd.com # connect the io bus 3847905SBrad.Beckmann@amd.com x86_sys.pc.attachIO(x86_sys.iobus) 3857905SBrad.Beckmann@amd.com 3868706Sandreas.hansson@arm.com x86_sys.system_port = x86_sys.membus.port 3878706Sandreas.hansson@arm.com 3887905SBrad.Beckmann@amd.comdef connectX86RubySystem(x86_sys): 3897905SBrad.Beckmann@amd.com # North Bridge 3907905SBrad.Beckmann@amd.com x86_sys.piobus = Bus(bus_id=0) 3917905SBrad.Beckmann@amd.com 3927905SBrad.Beckmann@amd.com # 3937905SBrad.Beckmann@amd.com # Pio functional accesses from devices need direct access to memory 3947905SBrad.Beckmann@amd.com # RubyPort currently does support functional accesses. Therefore provide 3957905SBrad.Beckmann@amd.com # the piobus a direct connection to physical memory 3967905SBrad.Beckmann@amd.com # 3977905SBrad.Beckmann@amd.com x86_sys.piobus.port = x86_sys.physmem.port 3987905SBrad.Beckmann@amd.com 3997905SBrad.Beckmann@amd.com x86_sys.pc.attachIO(x86_sys.piobus) 4007905SBrad.Beckmann@amd.com 4017905SBrad.Beckmann@amd.com 4027905SBrad.Beckmann@amd.comdef makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None, Ruby = False): 4035613Sgblack@eecs.umich.edu if self == None: 4045613Sgblack@eecs.umich.edu self = X86System() 4055613Sgblack@eecs.umich.edu 4065133Sgblack@eecs.umich.edu if not mdesc: 4075133Sgblack@eecs.umich.edu # generic system 4085133Sgblack@eecs.umich.edu mdesc = SysConfig() 4095133Sgblack@eecs.umich.edu self.readfile = mdesc.script() 4105133Sgblack@eecs.umich.edu 4116802Sgblack@eecs.umich.edu self.mem_mode = mem_mode 4126802Sgblack@eecs.umich.edu 4135133Sgblack@eecs.umich.edu # Physical memory 4145450Sgblack@eecs.umich.edu self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) 4155613Sgblack@eecs.umich.edu 4165613Sgblack@eecs.umich.edu # Platform 4175638Sgblack@eecs.umich.edu self.pc = Pc() 4187905SBrad.Beckmann@amd.com 4197905SBrad.Beckmann@amd.com # Create and connect the busses required by each memory system 4207905SBrad.Beckmann@amd.com if Ruby: 4217905SBrad.Beckmann@amd.com connectX86RubySystem(self) 4227937SBrad.Beckmann@amd.com # add the ide to the list of dma devices that later need to attach to 4237937SBrad.Beckmann@amd.com # dma controllers 4247937SBrad.Beckmann@amd.com self._dma_devices = [self.pc.south_bridge.ide] 4257905SBrad.Beckmann@amd.com else: 4267905SBrad.Beckmann@amd.com connectX86ClassicSystem(self) 4275613Sgblack@eecs.umich.edu 4285613Sgblack@eecs.umich.edu self.intrctrl = IntrControl() 4295613Sgblack@eecs.umich.edu 4305841Sgblack@eecs.umich.edu # Disks 4315841Sgblack@eecs.umich.edu disk0 = CowIdeDisk(driveID='master') 4325841Sgblack@eecs.umich.edu disk2 = CowIdeDisk(driveID='master') 4335841Sgblack@eecs.umich.edu disk0.childImage(mdesc.disk()) 4345841Sgblack@eecs.umich.edu disk2.childImage(disk('linux-bigswap2.img')) 4355841Sgblack@eecs.umich.edu self.pc.south_bridge.ide.disks = [disk0, disk2] 4365841Sgblack@eecs.umich.edu 4375615Sgblack@eecs.umich.edu # Add in a Bios information structure. 4385615Sgblack@eecs.umich.edu structures = [X86SMBiosBiosInformation()] 4395615Sgblack@eecs.umich.edu self.smbios_table.structures = structures 4405615Sgblack@eecs.umich.edu 4415641Sgblack@eecs.umich.edu # Set up the Intel MP table 4428323Ssteve.reinhardt@amd.com base_entries = [] 4438323Ssteve.reinhardt@amd.com ext_entries = [] 4446135Sgblack@eecs.umich.edu for i in xrange(numCPUs): 4456135Sgblack@eecs.umich.edu bp = X86IntelMPProcessor( 4466135Sgblack@eecs.umich.edu local_apic_id = i, 4476135Sgblack@eecs.umich.edu local_apic_version = 0x14, 4486135Sgblack@eecs.umich.edu enable = True, 4496135Sgblack@eecs.umich.edu bootstrap = (i == 0)) 4508323Ssteve.reinhardt@amd.com base_entries.append(bp) 4515644Sgblack@eecs.umich.edu io_apic = X86IntelMPIOAPIC( 4526135Sgblack@eecs.umich.edu id = numCPUs, 4535644Sgblack@eecs.umich.edu version = 0x11, 4545644Sgblack@eecs.umich.edu enable = True, 4555644Sgblack@eecs.umich.edu address = 0xfec00000) 4566135Sgblack@eecs.umich.edu self.pc.south_bridge.io_apic.apic_id = io_apic.id 4578323Ssteve.reinhardt@amd.com base_entries.append(io_apic) 4585644Sgblack@eecs.umich.edu isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA') 4598323Ssteve.reinhardt@amd.com base_entries.append(isa_bus) 4605843Sgblack@eecs.umich.edu pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI') 4618323Ssteve.reinhardt@amd.com base_entries.append(pci_bus) 4625843Sgblack@eecs.umich.edu connect_busses = X86IntelMPBusHierarchy(bus_id=0, 4635843Sgblack@eecs.umich.edu subtractive_decode=True, parent_bus=1) 4648323Ssteve.reinhardt@amd.com ext_entries.append(connect_busses) 4655843Sgblack@eecs.umich.edu pci_dev4_inta = X86IntelMPIOIntAssignment( 4665843Sgblack@eecs.umich.edu interrupt_type = 'INT', 4675843Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 4685843Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 4695843Sgblack@eecs.umich.edu source_bus_id = 1, 4705843Sgblack@eecs.umich.edu source_bus_irq = 0 + (4 << 2), 4716044Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 4725843Sgblack@eecs.umich.edu dest_io_apic_intin = 16) 4738323Ssteve.reinhardt@amd.com base_entries.append(pci_dev4_inta) 4746135Sgblack@eecs.umich.edu def assignISAInt(irq, apicPin): 4756135Sgblack@eecs.umich.edu assign_8259_to_apic = X86IntelMPIOIntAssignment( 4766135Sgblack@eecs.umich.edu interrupt_type = 'ExtInt', 4776135Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 4786135Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 4796135Sgblack@eecs.umich.edu source_bus_id = 0, 4806135Sgblack@eecs.umich.edu source_bus_irq = irq, 4816135Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 4826135Sgblack@eecs.umich.edu dest_io_apic_intin = 0) 4838323Ssteve.reinhardt@amd.com base_entries.append(assign_8259_to_apic) 4846135Sgblack@eecs.umich.edu assign_to_apic = X86IntelMPIOIntAssignment( 4856135Sgblack@eecs.umich.edu interrupt_type = 'INT', 4866135Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 4876135Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 4886135Sgblack@eecs.umich.edu source_bus_id = 0, 4896135Sgblack@eecs.umich.edu source_bus_irq = irq, 4906135Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 4916135Sgblack@eecs.umich.edu dest_io_apic_intin = apicPin) 4928323Ssteve.reinhardt@amd.com base_entries.append(assign_to_apic) 4936135Sgblack@eecs.umich.edu assignISAInt(0, 2) 4946135Sgblack@eecs.umich.edu assignISAInt(1, 1) 4956135Sgblack@eecs.umich.edu for i in range(3, 15): 4966135Sgblack@eecs.umich.edu assignISAInt(i, i) 4978323Ssteve.reinhardt@amd.com self.intel_mp_table.base_entries = base_entries 4988323Ssteve.reinhardt@amd.com self.intel_mp_table.ext_entries = ext_entries 4995641Sgblack@eecs.umich.edu 5007925Sgblack@eecs.umich.edudef setWorkCountOptions(system, options): 5017925Sgblack@eecs.umich.edu if options.work_item_id != None: 5027925Sgblack@eecs.umich.edu system.work_item_id = options.work_item_id 5037925Sgblack@eecs.umich.edu if options.work_begin_cpu_id_exit != None: 5047925Sgblack@eecs.umich.edu system.work_begin_cpu_id_exit = options.work_begin_cpu_id_exit 5057925Sgblack@eecs.umich.edu if options.work_end_exit_count != None: 5067925Sgblack@eecs.umich.edu system.work_end_exit_count = options.work_end_exit_count 5077925Sgblack@eecs.umich.edu if options.work_end_checkpoint_count != None: 5087925Sgblack@eecs.umich.edu system.work_end_ckpt_count = options.work_end_checkpoint_count 5097925Sgblack@eecs.umich.edu if options.work_begin_exit_count != None: 5107925Sgblack@eecs.umich.edu system.work_begin_exit_count = options.work_begin_exit_count 5117925Sgblack@eecs.umich.edu if options.work_begin_checkpoint_count != None: 5127925Sgblack@eecs.umich.edu system.work_begin_ckpt_count = options.work_begin_checkpoint_count 5137925Sgblack@eecs.umich.edu if options.work_cpus_checkpoint_count != None: 5147925Sgblack@eecs.umich.edu system.work_cpus_ckpt_count = options.work_cpus_checkpoint_count 5157925Sgblack@eecs.umich.edu 5167925Sgblack@eecs.umich.edu 5177925Sgblack@eecs.umich.edudef makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None, Ruby = False): 5185613Sgblack@eecs.umich.edu self = LinuxX86System() 5195613Sgblack@eecs.umich.edu 5207905SBrad.Beckmann@amd.com # Build up the x86 system and then specialize it for Linux 5217905SBrad.Beckmann@amd.com makeX86System(mem_mode, numCPUs, mdesc, self, Ruby) 5225613Sgblack@eecs.umich.edu 5235450Sgblack@eecs.umich.edu # We assume below that there's at least 1MB of memory. We'll require 2 5245450Sgblack@eecs.umich.edu # just to avoid corner cases. 5257069Snate@binkert.org assert(self.physmem.range.second.getValue() >= 0x200000) 5265450Sgblack@eecs.umich.edu 5278323Ssteve.reinhardt@amd.com self.e820_table.entries = \ 5288323Ssteve.reinhardt@amd.com [ 5298323Ssteve.reinhardt@amd.com # Mark the first megabyte of memory as reserved 5308323Ssteve.reinhardt@amd.com X86E820Entry(addr = 0, size = '1MB', range_type = 2), 5318323Ssteve.reinhardt@amd.com # Mark the rest as available 5328323Ssteve.reinhardt@amd.com X86E820Entry(addr = 0x100000, 5336072Sgblack@eecs.umich.edu size = '%dB' % (self.physmem.range.second - 0x100000 + 1), 5348323Ssteve.reinhardt@amd.com range_type = 1) 5358323Ssteve.reinhardt@amd.com ] 5365450Sgblack@eecs.umich.edu 5375330Sgblack@eecs.umich.edu # Command line 5385847Sgblack@eecs.umich.edu self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \ 5395845Sgblack@eecs.umich.edu 'root=/dev/hda1' 5405133Sgblack@eecs.umich.edu return self 5415133Sgblack@eecs.umich.edu 5423584Ssaidi@eecs.umich.edu 5433025Ssaidi@eecs.umich.edudef makeDualRoot(testSystem, driveSystem, dumpfile): 5442934Sktlim@umich.edu self = Root() 5452995Ssaidi@eecs.umich.edu self.testsys = testSystem 5462995Ssaidi@eecs.umich.edu self.drivesys = driveSystem 5474981Ssaidi@eecs.umich.edu self.etherlink = EtherLink() 5484981Ssaidi@eecs.umich.edu self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 5494981Ssaidi@eecs.umich.edu self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 5504981Ssaidi@eecs.umich.edu 5518661SAli.Saidi@ARM.com if hasattr(testSystem, 'realview'): 5528661SAli.Saidi@ARM.com self.etherlink.int0 = Parent.testsys.realview.ethernet.interface 5538661SAli.Saidi@ARM.com self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface 5548661SAli.Saidi@ARM.com elif hasattr(testSystem, 'tsunami'): 5558661SAli.Saidi@ARM.com self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 5568661SAli.Saidi@ARM.com self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 5578661SAli.Saidi@ARM.com else: 5588661SAli.Saidi@ARM.com fatal("Don't know how to connect these system together") 5598661SAli.Saidi@ARM.com 5603025Ssaidi@eecs.umich.edu if dumpfile: 5613025Ssaidi@eecs.umich.edu self.etherdump = EtherDump(file=dumpfile) 5623025Ssaidi@eecs.umich.edu self.etherlink.dump = Parent.etherdump 5632934Sktlim@umich.edu 5642934Sktlim@umich.edu return self 5655253Sksewell@umich.edu 5665263Sksewell@umich.edudef setMipsOptions(TestCPUClass): 5675253Sksewell@umich.edu #CP0 Configuration 5685253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_PRId_CompanyOptions = 0 5695253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_PRId_CompanyID = 1 5705253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_PRId_ProcessorID = 147 5715253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_PRId_Revision = 0 5725253Sksewell@umich.edu 5735253Sksewell@umich.edu #CP0 Interrupt Control 5745253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_IntCtl_IPTI = 7 5755253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_IntCtl_IPPCI = 7 5765253Sksewell@umich.edu 5775253Sksewell@umich.edu # Config Register 5785253Sksewell@umich.edu #TestCPUClass.CoreParams.CP0_Config_K23 = 0 # Since TLB 5795253Sksewell@umich.edu #TestCPUClass.CoreParams.CP0_Config_KU = 0 # Since TLB 5805253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config_BE = 0 # Little Endian 5815253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config_AR = 1 # Architecture Revision 2 5825253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config_AT = 0 # MIPS32 5835253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config_MT = 1 # TLB MMU 5845253Sksewell@umich.edu #TestCPUClass.CoreParams.CP0_Config_K0 = 2 # Uncached 5855253Sksewell@umich.edu 5865253Sksewell@umich.edu #Config 1 Register 5875253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_M = 1 # Config2 Implemented 5885253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_MMU = 63 # TLB Size 5895253Sksewell@umich.edu # ***VERY IMPORTANT*** 5905253Sksewell@umich.edu # Remember to modify CP0_Config1 according to cache specs 5915253Sksewell@umich.edu # Examine file ../common/Cache.py 5925253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_IS = 1 # I-Cache Sets Per Way, 16KB cache, i.e., 1 (128) 5935253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_IL = 5 # I-Cache Line Size, default in Cache.py is 64, i.e 5 5945253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_IA = 1 # I-Cache Associativity, default in Cache.py is 2, i.e, a value of 1 5955253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_DS = 2 # D-Cache Sets Per Way (see below), 32KB cache, i.e., 2 5965253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_DL = 5 # D-Cache Line Size, default is 64, i.e., 5 5975253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_DA = 1 # D-Cache Associativity, default is 2, i.e. 1 5985253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_C2 = 0 # Coprocessor 2 not implemented(?) 5995253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_MD = 0 # MDMX ASE not implemented in Mips32 6005253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_PC = 1 # Performance Counters Implemented 6015253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_WR = 0 # Watch Registers Implemented 6025253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_CA = 0 # Mips16e NOT implemented 6035253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_EP = 0 # EJTag Not Implemented 6045253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_FP = 0 # FPU Implemented 6055253Sksewell@umich.edu 6065253Sksewell@umich.edu #Config 2 Register 6075253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_M = 1 # Config3 Implemented 6085253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_TU = 0 # Tertiary Cache Control 6095253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_TS = 0 # Tertiary Cache Sets Per Way 6105253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_TL = 0 # Tertiary Cache Line Size 6115253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_TA = 0 # Tertiary Cache Associativity 6125253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_SU = 0 # Secondary Cache Control 6135253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_SS = 0 # Secondary Cache Sets Per Way 6145253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_SL = 0 # Secondary Cache Line Size 6155253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_SA = 0 # Secondary Cache Associativity 6165253Sksewell@umich.edu 6175253Sksewell@umich.edu 6185253Sksewell@umich.edu #Config 3 Register 6195253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_M = 0 # Config4 Not Implemented 6205253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_DSPP = 1 # DSP ASE Present 6215253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_LPA = 0 # Large Physical Addresses Not supported in Mips32 6225253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_VEIC = 0 # EIC Supported 6235253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_VInt = 0 # Vectored Interrupts Implemented 6245253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_SP = 0 # Small Pages Supported (PageGrain reg. exists) 6255253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_MT = 0 # MT Not present 6265253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_SM = 0 # SmartMIPS ASE Not implemented 6275253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_TL = 0 # TraceLogic Not implemented 6285253Sksewell@umich.edu 6295253Sksewell@umich.edu #SRS Ctl - HSS 6305253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_SrsCtl_HSS = 3 # Four shadow register sets implemented 6315253Sksewell@umich.edu 6325253Sksewell@umich.edu 6335253Sksewell@umich.edu #TestCPUClass.CoreParams.tlb = TLB() 6345253Sksewell@umich.edu #TestCPUClass.CoreParams.UnifiedTLB = 1 635