FSConfig.py revision 8706
18706Sandreas.hansson@arm.com# Copyright (c) 2010-2012 ARM Limited 27586SAli.Saidi@arm.com# All rights reserved. 37586SAli.Saidi@arm.com# 47586SAli.Saidi@arm.com# The license below extends only to copyright in the software and shall 57586SAli.Saidi@arm.com# not be construed as granting a license to any other intellectual 67586SAli.Saidi@arm.com# property including but not limited to intellectual property relating 77586SAli.Saidi@arm.com# to a hardware implementation of the functionality of the software 87586SAli.Saidi@arm.com# licensed hereunder. You may use the software subject to the license 97586SAli.Saidi@arm.com# terms below provided that you ensure that this notice is replicated 107586SAli.Saidi@arm.com# unmodified and in its entirety in all distributions of the software, 117586SAli.Saidi@arm.com# modified or unmodified, in source code or in binary form. 127586SAli.Saidi@arm.com# 137905SBrad.Beckmann@amd.com# Copyright (c) 2010-2011 Advanced Micro Devices, Inc. 145323Sgblack@eecs.umich.edu# Copyright (c) 2006-2008 The Regents of The University of Michigan 152934Sktlim@umich.edu# All rights reserved. 162934Sktlim@umich.edu# 172934Sktlim@umich.edu# Redistribution and use in source and binary forms, with or without 182934Sktlim@umich.edu# modification, are permitted provided that the following conditions are 192934Sktlim@umich.edu# met: redistributions of source code must retain the above copyright 202934Sktlim@umich.edu# notice, this list of conditions and the following disclaimer; 212934Sktlim@umich.edu# redistributions in binary form must reproduce the above copyright 222934Sktlim@umich.edu# notice, this list of conditions and the following disclaimer in the 232934Sktlim@umich.edu# documentation and/or other materials provided with the distribution; 242934Sktlim@umich.edu# neither the name of the copyright holders nor the names of its 252934Sktlim@umich.edu# contributors may be used to endorse or promote products derived from 262934Sktlim@umich.edu# this software without specific prior written permission. 272934Sktlim@umich.edu# 282934Sktlim@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292934Sktlim@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302934Sktlim@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312934Sktlim@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322934Sktlim@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332934Sktlim@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342934Sktlim@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352934Sktlim@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362934Sktlim@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372934Sktlim@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382934Sktlim@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392934Sktlim@umich.edu# 402934Sktlim@umich.edu# Authors: Kevin Lim 412934Sktlim@umich.edu 422934Sktlim@umich.edufrom m5.objects import * 432995Ssaidi@eecs.umich.edufrom Benchmarks import * 448528SAli.Saidi@ARM.comfrom m5.util import convert 452934Sktlim@umich.edu 462934Sktlim@umich.educlass CowIdeDisk(IdeDisk): 472934Sktlim@umich.edu image = CowDiskImage(child=RawDiskImage(read_only=True), 482934Sktlim@umich.edu read_only=False) 492934Sktlim@umich.edu 502934Sktlim@umich.edu def childImage(self, ci): 512934Sktlim@umich.edu self.image.child.image_file = ci 522934Sktlim@umich.edu 536122SSteve.Reinhardt@amd.comclass MemBus(Bus): 546122SSteve.Reinhardt@amd.com badaddr_responder = BadAddr() 556122SSteve.Reinhardt@amd.com default = Self.badaddr_responder.pio 566122SSteve.Reinhardt@amd.com 576122SSteve.Reinhardt@amd.com 584520Ssaidi@eecs.umich.edudef makeLinuxAlphaSystem(mem_mode, mdesc = None): 594520Ssaidi@eecs.umich.edu class BaseTsunami(Tsunami): 604982Ssaidi@eecs.umich.edu ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 614520Ssaidi@eecs.umich.edu ide = IdeController(disks=[Parent.disk0, Parent.disk2], 624520Ssaidi@eecs.umich.edu pci_func=0, pci_dev=0, pci_bus=0) 632934Sktlim@umich.edu 642934Sktlim@umich.edu self = LinuxAlphaSystem() 653005Sstever@eecs.umich.edu if not mdesc: 663005Sstever@eecs.umich.edu # generic system 673304Sstever@eecs.umich.edu mdesc = SysConfig() 682995Ssaidi@eecs.umich.edu self.readfile = mdesc.script() 692934Sktlim@umich.edu self.iobus = Bus(bus_id=0) 706122SSteve.Reinhardt@amd.com self.membus = MemBus(bus_id=1) 714965Ssaidi@eecs.umich.edu self.bridge = Bridge(delay='50ns', nack_delay='4ns') 725266Sksewell@umich.edu self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) 732934Sktlim@umich.edu self.bridge.side_a = self.iobus.port 742934Sktlim@umich.edu self.bridge.side_b = self.membus.port 752934Sktlim@umich.edu self.physmem.port = self.membus.port 762934Sktlim@umich.edu self.disk0 = CowIdeDisk(driveID='master') 772934Sktlim@umich.edu self.disk2 = CowIdeDisk(driveID='master') 782995Ssaidi@eecs.umich.edu self.disk0.childImage(mdesc.disk()) 792934Sktlim@umich.edu self.disk2.childImage(disk('linux-bigswap2.img')) 802934Sktlim@umich.edu self.tsunami = BaseTsunami() 812934Sktlim@umich.edu self.tsunami.attachIO(self.iobus) 822934Sktlim@umich.edu self.tsunami.ide.pio = self.iobus.port 832934Sktlim@umich.edu self.tsunami.ethernet.pio = self.iobus.port 842995Ssaidi@eecs.umich.edu self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 852934Sktlim@umich.edu read_only = True)) 862934Sktlim@umich.edu self.intrctrl = IntrControl() 872953Sktlim@umich.edu self.mem_mode = mem_mode 885478Snate@binkert.org self.terminal = Terminal() 892934Sktlim@umich.edu self.kernel = binary('vmlinux') 903449Shsul@eecs.umich.edu self.pal = binary('ts_osfpal') 912934Sktlim@umich.edu self.console = binary('console') 922934Sktlim@umich.edu self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 932934Sktlim@umich.edu 948706Sandreas.hansson@arm.com self.system_port = self.membus.port 958706Sandreas.hansson@arm.com 962934Sktlim@umich.edu return self 972934Sktlim@umich.edu 987014SBrad.Beckmann@amd.comdef makeLinuxAlphaRubySystem(mem_mode, mdesc = None): 996765SBrad.Beckmann@amd.com class BaseTsunami(Tsunami): 1006765SBrad.Beckmann@amd.com ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 1016765SBrad.Beckmann@amd.com ide = IdeController(disks=[Parent.disk0, Parent.disk2], 1026765SBrad.Beckmann@amd.com pci_func=0, pci_dev=0, pci_bus=0) 1036765SBrad.Beckmann@amd.com 1047014SBrad.Beckmann@amd.com physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) 1057014SBrad.Beckmann@amd.com self = LinuxAlphaSystem(physmem = physmem) 1066765SBrad.Beckmann@amd.com if not mdesc: 1076765SBrad.Beckmann@amd.com # generic system 1086765SBrad.Beckmann@amd.com mdesc = SysConfig() 1096765SBrad.Beckmann@amd.com self.readfile = mdesc.script() 1106765SBrad.Beckmann@amd.com 1116765SBrad.Beckmann@amd.com # Create pio bus to connect all device pio ports to rubymem's pio port 1126765SBrad.Beckmann@amd.com self.piobus = Bus(bus_id=0) 1136893SBrad.Beckmann@amd.com 1146893SBrad.Beckmann@amd.com # 1156893SBrad.Beckmann@amd.com # Pio functional accesses from devices need direct access to memory 1166893SBrad.Beckmann@amd.com # RubyPort currently does support functional accesses. Therefore provide 1176893SBrad.Beckmann@amd.com # the piobus a direct connection to physical memory 1186893SBrad.Beckmann@amd.com # 1197014SBrad.Beckmann@amd.com self.piobus.port = physmem.port 1206893SBrad.Beckmann@amd.com 1216765SBrad.Beckmann@amd.com self.disk0 = CowIdeDisk(driveID='master') 1226765SBrad.Beckmann@amd.com self.disk2 = CowIdeDisk(driveID='master') 1236765SBrad.Beckmann@amd.com self.disk0.childImage(mdesc.disk()) 1246765SBrad.Beckmann@amd.com self.disk2.childImage(disk('linux-bigswap2.img')) 1256765SBrad.Beckmann@amd.com self.tsunami = BaseTsunami() 1266765SBrad.Beckmann@amd.com self.tsunami.attachIO(self.piobus) 1276765SBrad.Beckmann@amd.com self.tsunami.ide.pio = self.piobus.port 1286765SBrad.Beckmann@amd.com self.tsunami.ethernet.pio = self.piobus.port 1296765SBrad.Beckmann@amd.com 1306893SBrad.Beckmann@amd.com # 1317633SBrad.Beckmann@amd.com # Store the dma devices for later connection to dma ruby ports. 1327633SBrad.Beckmann@amd.com # Append an underscore to dma_devices to avoid the SimObjectVector check. 1336893SBrad.Beckmann@amd.com # 1347633SBrad.Beckmann@amd.com self._dma_devices = [self.tsunami.ide, self.tsunami.ethernet] 1356765SBrad.Beckmann@amd.com 1366765SBrad.Beckmann@amd.com self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 1376765SBrad.Beckmann@amd.com read_only = True)) 1386765SBrad.Beckmann@amd.com self.intrctrl = IntrControl() 1396765SBrad.Beckmann@amd.com self.mem_mode = mem_mode 1406765SBrad.Beckmann@amd.com self.terminal = Terminal() 1416765SBrad.Beckmann@amd.com self.kernel = binary('vmlinux') 1426765SBrad.Beckmann@amd.com self.pal = binary('ts_osfpal') 1436765SBrad.Beckmann@amd.com self.console = binary('console') 1446765SBrad.Beckmann@amd.com self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 1456765SBrad.Beckmann@amd.com 1466765SBrad.Beckmann@amd.com return self 1476765SBrad.Beckmann@amd.com 1483584Ssaidi@eecs.umich.edudef makeSparcSystem(mem_mode, mdesc = None): 1494486Sbinkertn@umich.edu class CowMmDisk(MmDisk): 1504486Sbinkertn@umich.edu image = CowDiskImage(child=RawDiskImage(read_only=True), 1514486Sbinkertn@umich.edu read_only=False) 1524486Sbinkertn@umich.edu 1534486Sbinkertn@umich.edu def childImage(self, ci): 1544486Sbinkertn@umich.edu self.image.child.image_file = ci 1554486Sbinkertn@umich.edu 1563584Ssaidi@eecs.umich.edu self = SparcSystem() 1573584Ssaidi@eecs.umich.edu if not mdesc: 1583584Ssaidi@eecs.umich.edu # generic system 1593584Ssaidi@eecs.umich.edu mdesc = SysConfig() 1603584Ssaidi@eecs.umich.edu self.readfile = mdesc.script() 1613743Sgblack@eecs.umich.edu self.iobus = Bus(bus_id=0) 1626122SSteve.Reinhardt@amd.com self.membus = MemBus(bus_id=1) 1634972Ssaidi@eecs.umich.edu self.bridge = Bridge(delay='50ns', nack_delay='4ns') 1643743Sgblack@eecs.umich.edu self.t1000 = T1000() 1654104Ssaidi@eecs.umich.edu self.t1000.attachOnChipIO(self.membus) 1663743Sgblack@eecs.umich.edu self.t1000.attachIO(self.iobus) 1673823Ssaidi@eecs.umich.edu self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True) 1683814Ssaidi@eecs.umich.edu self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True) 1693743Sgblack@eecs.umich.edu self.bridge.side_a = self.iobus.port 1703743Sgblack@eecs.umich.edu self.bridge.side_b = self.membus.port 1713584Ssaidi@eecs.umich.edu self.physmem.port = self.membus.port 1723814Ssaidi@eecs.umich.edu self.physmem2.port = self.membus.port 1733584Ssaidi@eecs.umich.edu self.rom.port = self.membus.port 1743745Sgblack@eecs.umich.edu self.nvram.port = self.membus.port 1753745Sgblack@eecs.umich.edu self.hypervisor_desc.port = self.membus.port 1763745Sgblack@eecs.umich.edu self.partition_desc.port = self.membus.port 1773584Ssaidi@eecs.umich.edu self.intrctrl = IntrControl() 1783898Ssaidi@eecs.umich.edu self.disk0 = CowMmDisk() 1793898Ssaidi@eecs.umich.edu self.disk0.childImage(disk('disk.s10hw2')) 1803898Ssaidi@eecs.umich.edu self.disk0.pio = self.iobus.port 1814103Ssaidi@eecs.umich.edu self.reset_bin = binary('reset_new.bin') 1824103Ssaidi@eecs.umich.edu self.hypervisor_bin = binary('q_new.bin') 1834103Ssaidi@eecs.umich.edu self.openboot_bin = binary('openboot_new.bin') 1843745Sgblack@eecs.umich.edu self.nvram_bin = binary('nvram1') 1853745Sgblack@eecs.umich.edu self.hypervisor_desc_bin = binary('1up-hv.bin') 1863745Sgblack@eecs.umich.edu self.partition_desc_bin = binary('1up-md.bin') 1873584Ssaidi@eecs.umich.edu 1888706Sandreas.hansson@arm.com self.system_port = self.membus.port 1898706Sandreas.hansson@arm.com 1903584Ssaidi@eecs.umich.edu return self 1913584Ssaidi@eecs.umich.edu 1928061SAli.Saidi@ARM.comdef makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False): 1938061SAli.Saidi@ARM.com assert machine_type 1948061SAli.Saidi@ARM.com 1957586SAli.Saidi@arm.com if bare_metal: 1967586SAli.Saidi@arm.com self = ArmSystem() 1977586SAli.Saidi@arm.com else: 1987586SAli.Saidi@arm.com self = LinuxArmSystem() 1997586SAli.Saidi@arm.com 2007586SAli.Saidi@arm.com if not mdesc: 2017586SAli.Saidi@arm.com # generic system 2027586SAli.Saidi@arm.com mdesc = SysConfig() 2037586SAli.Saidi@arm.com 2047586SAli.Saidi@arm.com self.readfile = mdesc.script() 2057586SAli.Saidi@arm.com self.iobus = Bus(bus_id=0) 2067586SAli.Saidi@arm.com self.membus = MemBus(bus_id=1) 2077586SAli.Saidi@arm.com self.membus.badaddr_responder.warn_access = "warn" 2087586SAli.Saidi@arm.com self.bridge = Bridge(delay='50ns', nack_delay='4ns') 2097586SAli.Saidi@arm.com self.bridge.side_a = self.iobus.port 2107586SAli.Saidi@arm.com self.bridge.side_b = self.membus.port 2117586SAli.Saidi@arm.com 2127586SAli.Saidi@arm.com self.mem_mode = mem_mode 2137586SAli.Saidi@arm.com 2147586SAli.Saidi@arm.com if machine_type == "RealView_PBX": 2157586SAli.Saidi@arm.com self.realview = RealViewPBX() 2167586SAli.Saidi@arm.com elif machine_type == "RealView_EB": 2177586SAli.Saidi@arm.com self.realview = RealViewEB() 2188525SAli.Saidi@ARM.com elif machine_type == "VExpress_ELT": 2198525SAli.Saidi@ARM.com self.realview = VExpress_ELT() 2207586SAli.Saidi@arm.com else: 2217586SAli.Saidi@arm.com print "Unknown Machine Type" 2227586SAli.Saidi@arm.com sys.exit(1) 2237586SAli.Saidi@arm.com 2248528SAli.Saidi@ARM.com self.cf0 = CowIdeDisk(driveID='master') 2258528SAli.Saidi@ARM.com self.cf0.childImage(mdesc.disk()) 2268528SAli.Saidi@ARM.com # default to an IDE controller rather than a CF one 2278528SAli.Saidi@ARM.com # assuming we've got one 2288528SAli.Saidi@ARM.com try: 2298528SAli.Saidi@ARM.com self.realview.ide.disks = [self.cf0] 2308528SAli.Saidi@ARM.com except: 2318528SAli.Saidi@ARM.com self.realview.cf_ctrl.disks = [self.cf0] 2328528SAli.Saidi@ARM.com 2338061SAli.Saidi@ARM.com if bare_metal: 2348061SAli.Saidi@ARM.com # EOT character on UART will end the simulation 2358061SAli.Saidi@ARM.com self.realview.uart.end_on_eot = True 2368528SAli.Saidi@ARM.com self.physmem = PhysicalMemory(range = AddrRange(Addr(mdesc.mem())), 2378212SAli.Saidi@ARM.com zero = True) 2388061SAli.Saidi@ARM.com else: 2398528SAli.Saidi@ARM.com self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8') 2407586SAli.Saidi@arm.com self.machine_type = machine_type 2418528SAli.Saidi@ARM.com if convert.toMemorySize(mdesc.mem()) > convert.toMemorySize('256MB'): 2428528SAli.Saidi@ARM.com print "The currently implemented ARM platforms only easily support 256MB of DRAM" 2438528SAli.Saidi@ARM.com print "It might be possible to get some more by using 256MB@0x30000000, but this" 2448528SAli.Saidi@ARM.com print "is untested and may require some heroics" 2458528SAli.Saidi@ARM.com 2468212SAli.Saidi@ARM.com boot_flags = 'earlyprintk console=ttyAMA0 lpj=19988480 norandmaps ' + \ 2478528SAli.Saidi@ARM.com 'rw loglevel=8 mem=%s root=/dev/sda1' % mdesc.mem() 2488528SAli.Saidi@ARM.com 2498528SAli.Saidi@ARM.com self.physmem = PhysicalMemory(range = AddrRange(Addr(mdesc.mem())), 2508528SAli.Saidi@ARM.com zero = True) 2518528SAli.Saidi@ARM.com self.nvmem = PhysicalMemory(range = AddrRange(Addr('2GB'), 2528528SAli.Saidi@ARM.com size = '64MB'), zero = True) 2538528SAli.Saidi@ARM.com self.nvmem.port = self.membus.port 2548528SAli.Saidi@ARM.com self.boot_loader = binary('boot.arm') 2558528SAli.Saidi@ARM.com self.boot_loader_mem = self.nvmem 2568528SAli.Saidi@ARM.com self.gic_cpu_addr = self.realview.gic.cpu_addr 2578528SAli.Saidi@ARM.com self.flags_addr = self.realview.realview_io.pio_addr + 0x30 2588287SAli.Saidi@ARM.com 2598643Satgutier@umich.edu if mdesc.disk().lower().count('android'): 2608595SAli.Saidi@ARM.com boot_flags += " init=/init " 2618212SAli.Saidi@ARM.com self.boot_osflags = boot_flags 2627586SAli.Saidi@arm.com 2638145SAli.Saidi@ARM.com self.physmem.port = self.membus.port 2647586SAli.Saidi@arm.com self.realview.attachOnChipIO(self.membus) 2657586SAli.Saidi@arm.com self.realview.attachIO(self.iobus) 2667586SAli.Saidi@arm.com self.intrctrl = IntrControl() 2677586SAli.Saidi@arm.com self.terminal = Terminal() 2687949SAli.Saidi@ARM.com self.vncserver = VncServer() 2697586SAli.Saidi@arm.com 2708706Sandreas.hansson@arm.com self.system_port = self.membus.port 2718706Sandreas.hansson@arm.com 2727586SAli.Saidi@arm.com return self 2737586SAli.Saidi@arm.com 2747586SAli.Saidi@arm.com 2755222Sksewell@umich.edudef makeLinuxMipsSystem(mem_mode, mdesc = None): 2765222Sksewell@umich.edu class BaseMalta(Malta): 2775222Sksewell@umich.edu ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 2785222Sksewell@umich.edu ide = IdeController(disks=[Parent.disk0, Parent.disk2], 2795222Sksewell@umich.edu pci_func=0, pci_dev=0, pci_bus=0) 2805222Sksewell@umich.edu 2815222Sksewell@umich.edu self = LinuxMipsSystem() 2825222Sksewell@umich.edu if not mdesc: 2835222Sksewell@umich.edu # generic system 2845222Sksewell@umich.edu mdesc = SysConfig() 2855222Sksewell@umich.edu self.readfile = mdesc.script() 2865222Sksewell@umich.edu self.iobus = Bus(bus_id=0) 2876122SSteve.Reinhardt@amd.com self.membus = MemBus(bus_id=1) 2885222Sksewell@umich.edu self.bridge = Bridge(delay='50ns', nack_delay='4ns') 2895222Sksewell@umich.edu self.physmem = PhysicalMemory(range = AddrRange('1GB')) 2905222Sksewell@umich.edu self.bridge.side_a = self.iobus.port 2915222Sksewell@umich.edu self.bridge.side_b = self.membus.port 2925222Sksewell@umich.edu self.physmem.port = self.membus.port 2935222Sksewell@umich.edu self.disk0 = CowIdeDisk(driveID='master') 2945222Sksewell@umich.edu self.disk2 = CowIdeDisk(driveID='master') 2955222Sksewell@umich.edu self.disk0.childImage(mdesc.disk()) 2965222Sksewell@umich.edu self.disk2.childImage(disk('linux-bigswap2.img')) 2975222Sksewell@umich.edu self.malta = BaseMalta() 2985222Sksewell@umich.edu self.malta.attachIO(self.iobus) 2995222Sksewell@umich.edu self.malta.ide.pio = self.iobus.port 3005222Sksewell@umich.edu self.malta.ethernet.pio = self.iobus.port 3015222Sksewell@umich.edu self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 3025222Sksewell@umich.edu read_only = True)) 3035222Sksewell@umich.edu self.intrctrl = IntrControl() 3045222Sksewell@umich.edu self.mem_mode = mem_mode 3055478Snate@binkert.org self.terminal = Terminal() 3065222Sksewell@umich.edu self.kernel = binary('mips/vmlinux') 3075222Sksewell@umich.edu self.console = binary('mips/console') 3085222Sksewell@umich.edu self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 3095222Sksewell@umich.edu 3108706Sandreas.hansson@arm.com self.system_port = self.membus.port 3118706Sandreas.hansson@arm.com 3125222Sksewell@umich.edu return self 3135222Sksewell@umich.edu 3145323Sgblack@eecs.umich.edudef x86IOAddress(port): 3155357Sgblack@eecs.umich.edu IO_address_space_base = 0x8000000000000000 3168323Ssteve.reinhardt@amd.com return IO_address_space_base + port 3175323Sgblack@eecs.umich.edu 3187905SBrad.Beckmann@amd.comdef connectX86ClassicSystem(x86_sys): 3197905SBrad.Beckmann@amd.com x86_sys.membus = MemBus(bus_id=1) 3207905SBrad.Beckmann@amd.com x86_sys.physmem.port = x86_sys.membus.port 3217905SBrad.Beckmann@amd.com 3227905SBrad.Beckmann@amd.com # North Bridge 3237905SBrad.Beckmann@amd.com x86_sys.iobus = Bus(bus_id=0) 3247905SBrad.Beckmann@amd.com x86_sys.bridge = Bridge(delay='50ns', nack_delay='4ns') 3257905SBrad.Beckmann@amd.com x86_sys.bridge.side_a = x86_sys.iobus.port 3267905SBrad.Beckmann@amd.com x86_sys.bridge.side_b = x86_sys.membus.port 3277905SBrad.Beckmann@amd.com 3287905SBrad.Beckmann@amd.com # connect the io bus 3297905SBrad.Beckmann@amd.com x86_sys.pc.attachIO(x86_sys.iobus) 3307905SBrad.Beckmann@amd.com 3318706Sandreas.hansson@arm.com x86_sys.system_port = x86_sys.membus.port 3328706Sandreas.hansson@arm.com 3337905SBrad.Beckmann@amd.comdef connectX86RubySystem(x86_sys): 3347905SBrad.Beckmann@amd.com # North Bridge 3357905SBrad.Beckmann@amd.com x86_sys.piobus = Bus(bus_id=0) 3367905SBrad.Beckmann@amd.com 3377905SBrad.Beckmann@amd.com # 3387905SBrad.Beckmann@amd.com # Pio functional accesses from devices need direct access to memory 3397905SBrad.Beckmann@amd.com # RubyPort currently does support functional accesses. Therefore provide 3407905SBrad.Beckmann@amd.com # the piobus a direct connection to physical memory 3417905SBrad.Beckmann@amd.com # 3427905SBrad.Beckmann@amd.com x86_sys.piobus.port = x86_sys.physmem.port 3437905SBrad.Beckmann@amd.com 3447905SBrad.Beckmann@amd.com x86_sys.pc.attachIO(x86_sys.piobus) 3457905SBrad.Beckmann@amd.com 3467905SBrad.Beckmann@amd.com 3477905SBrad.Beckmann@amd.comdef makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None, Ruby = False): 3485613Sgblack@eecs.umich.edu if self == None: 3495613Sgblack@eecs.umich.edu self = X86System() 3505613Sgblack@eecs.umich.edu 3515133Sgblack@eecs.umich.edu if not mdesc: 3525133Sgblack@eecs.umich.edu # generic system 3535133Sgblack@eecs.umich.edu mdesc = SysConfig() 3545133Sgblack@eecs.umich.edu self.readfile = mdesc.script() 3555133Sgblack@eecs.umich.edu 3566802Sgblack@eecs.umich.edu self.mem_mode = mem_mode 3576802Sgblack@eecs.umich.edu 3585133Sgblack@eecs.umich.edu # Physical memory 3595450Sgblack@eecs.umich.edu self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) 3605613Sgblack@eecs.umich.edu 3615613Sgblack@eecs.umich.edu # Platform 3625638Sgblack@eecs.umich.edu self.pc = Pc() 3637905SBrad.Beckmann@amd.com 3647905SBrad.Beckmann@amd.com # Create and connect the busses required by each memory system 3657905SBrad.Beckmann@amd.com if Ruby: 3667905SBrad.Beckmann@amd.com connectX86RubySystem(self) 3677937SBrad.Beckmann@amd.com # add the ide to the list of dma devices that later need to attach to 3687937SBrad.Beckmann@amd.com # dma controllers 3697937SBrad.Beckmann@amd.com self._dma_devices = [self.pc.south_bridge.ide] 3707905SBrad.Beckmann@amd.com else: 3717905SBrad.Beckmann@amd.com connectX86ClassicSystem(self) 3725613Sgblack@eecs.umich.edu 3735613Sgblack@eecs.umich.edu self.intrctrl = IntrControl() 3745613Sgblack@eecs.umich.edu 3755841Sgblack@eecs.umich.edu # Disks 3765841Sgblack@eecs.umich.edu disk0 = CowIdeDisk(driveID='master') 3775841Sgblack@eecs.umich.edu disk2 = CowIdeDisk(driveID='master') 3785841Sgblack@eecs.umich.edu disk0.childImage(mdesc.disk()) 3795841Sgblack@eecs.umich.edu disk2.childImage(disk('linux-bigswap2.img')) 3805841Sgblack@eecs.umich.edu self.pc.south_bridge.ide.disks = [disk0, disk2] 3815841Sgblack@eecs.umich.edu 3825615Sgblack@eecs.umich.edu # Add in a Bios information structure. 3835615Sgblack@eecs.umich.edu structures = [X86SMBiosBiosInformation()] 3845615Sgblack@eecs.umich.edu self.smbios_table.structures = structures 3855615Sgblack@eecs.umich.edu 3865641Sgblack@eecs.umich.edu # Set up the Intel MP table 3878323Ssteve.reinhardt@amd.com base_entries = [] 3888323Ssteve.reinhardt@amd.com ext_entries = [] 3896135Sgblack@eecs.umich.edu for i in xrange(numCPUs): 3906135Sgblack@eecs.umich.edu bp = X86IntelMPProcessor( 3916135Sgblack@eecs.umich.edu local_apic_id = i, 3926135Sgblack@eecs.umich.edu local_apic_version = 0x14, 3936135Sgblack@eecs.umich.edu enable = True, 3946135Sgblack@eecs.umich.edu bootstrap = (i == 0)) 3958323Ssteve.reinhardt@amd.com base_entries.append(bp) 3965644Sgblack@eecs.umich.edu io_apic = X86IntelMPIOAPIC( 3976135Sgblack@eecs.umich.edu id = numCPUs, 3985644Sgblack@eecs.umich.edu version = 0x11, 3995644Sgblack@eecs.umich.edu enable = True, 4005644Sgblack@eecs.umich.edu address = 0xfec00000) 4016135Sgblack@eecs.umich.edu self.pc.south_bridge.io_apic.apic_id = io_apic.id 4028323Ssteve.reinhardt@amd.com base_entries.append(io_apic) 4035644Sgblack@eecs.umich.edu isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA') 4048323Ssteve.reinhardt@amd.com base_entries.append(isa_bus) 4055843Sgblack@eecs.umich.edu pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI') 4068323Ssteve.reinhardt@amd.com base_entries.append(pci_bus) 4075843Sgblack@eecs.umich.edu connect_busses = X86IntelMPBusHierarchy(bus_id=0, 4085843Sgblack@eecs.umich.edu subtractive_decode=True, parent_bus=1) 4098323Ssteve.reinhardt@amd.com ext_entries.append(connect_busses) 4105843Sgblack@eecs.umich.edu pci_dev4_inta = X86IntelMPIOIntAssignment( 4115843Sgblack@eecs.umich.edu interrupt_type = 'INT', 4125843Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 4135843Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 4145843Sgblack@eecs.umich.edu source_bus_id = 1, 4155843Sgblack@eecs.umich.edu source_bus_irq = 0 + (4 << 2), 4166044Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 4175843Sgblack@eecs.umich.edu dest_io_apic_intin = 16) 4188323Ssteve.reinhardt@amd.com base_entries.append(pci_dev4_inta) 4196135Sgblack@eecs.umich.edu def assignISAInt(irq, apicPin): 4206135Sgblack@eecs.umich.edu assign_8259_to_apic = X86IntelMPIOIntAssignment( 4216135Sgblack@eecs.umich.edu interrupt_type = 'ExtInt', 4226135Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 4236135Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 4246135Sgblack@eecs.umich.edu source_bus_id = 0, 4256135Sgblack@eecs.umich.edu source_bus_irq = irq, 4266135Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 4276135Sgblack@eecs.umich.edu dest_io_apic_intin = 0) 4288323Ssteve.reinhardt@amd.com base_entries.append(assign_8259_to_apic) 4296135Sgblack@eecs.umich.edu assign_to_apic = X86IntelMPIOIntAssignment( 4306135Sgblack@eecs.umich.edu interrupt_type = 'INT', 4316135Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 4326135Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 4336135Sgblack@eecs.umich.edu source_bus_id = 0, 4346135Sgblack@eecs.umich.edu source_bus_irq = irq, 4356135Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 4366135Sgblack@eecs.umich.edu dest_io_apic_intin = apicPin) 4378323Ssteve.reinhardt@amd.com base_entries.append(assign_to_apic) 4386135Sgblack@eecs.umich.edu assignISAInt(0, 2) 4396135Sgblack@eecs.umich.edu assignISAInt(1, 1) 4406135Sgblack@eecs.umich.edu for i in range(3, 15): 4416135Sgblack@eecs.umich.edu assignISAInt(i, i) 4428323Ssteve.reinhardt@amd.com self.intel_mp_table.base_entries = base_entries 4438323Ssteve.reinhardt@amd.com self.intel_mp_table.ext_entries = ext_entries 4445641Sgblack@eecs.umich.edu 4457925Sgblack@eecs.umich.edudef setWorkCountOptions(system, options): 4467925Sgblack@eecs.umich.edu if options.work_item_id != None: 4477925Sgblack@eecs.umich.edu system.work_item_id = options.work_item_id 4487925Sgblack@eecs.umich.edu if options.work_begin_cpu_id_exit != None: 4497925Sgblack@eecs.umich.edu system.work_begin_cpu_id_exit = options.work_begin_cpu_id_exit 4507925Sgblack@eecs.umich.edu if options.work_end_exit_count != None: 4517925Sgblack@eecs.umich.edu system.work_end_exit_count = options.work_end_exit_count 4527925Sgblack@eecs.umich.edu if options.work_end_checkpoint_count != None: 4537925Sgblack@eecs.umich.edu system.work_end_ckpt_count = options.work_end_checkpoint_count 4547925Sgblack@eecs.umich.edu if options.work_begin_exit_count != None: 4557925Sgblack@eecs.umich.edu system.work_begin_exit_count = options.work_begin_exit_count 4567925Sgblack@eecs.umich.edu if options.work_begin_checkpoint_count != None: 4577925Sgblack@eecs.umich.edu system.work_begin_ckpt_count = options.work_begin_checkpoint_count 4587925Sgblack@eecs.umich.edu if options.work_cpus_checkpoint_count != None: 4597925Sgblack@eecs.umich.edu system.work_cpus_ckpt_count = options.work_cpus_checkpoint_count 4607925Sgblack@eecs.umich.edu 4617925Sgblack@eecs.umich.edu 4627925Sgblack@eecs.umich.edudef makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None, Ruby = False): 4635613Sgblack@eecs.umich.edu self = LinuxX86System() 4645613Sgblack@eecs.umich.edu 4657905SBrad.Beckmann@amd.com # Build up the x86 system and then specialize it for Linux 4667905SBrad.Beckmann@amd.com makeX86System(mem_mode, numCPUs, mdesc, self, Ruby) 4675613Sgblack@eecs.umich.edu 4685450Sgblack@eecs.umich.edu # We assume below that there's at least 1MB of memory. We'll require 2 4695450Sgblack@eecs.umich.edu # just to avoid corner cases. 4707069Snate@binkert.org assert(self.physmem.range.second.getValue() >= 0x200000) 4715450Sgblack@eecs.umich.edu 4728323Ssteve.reinhardt@amd.com self.e820_table.entries = \ 4738323Ssteve.reinhardt@amd.com [ 4748323Ssteve.reinhardt@amd.com # Mark the first megabyte of memory as reserved 4758323Ssteve.reinhardt@amd.com X86E820Entry(addr = 0, size = '1MB', range_type = 2), 4768323Ssteve.reinhardt@amd.com # Mark the rest as available 4778323Ssteve.reinhardt@amd.com X86E820Entry(addr = 0x100000, 4786072Sgblack@eecs.umich.edu size = '%dB' % (self.physmem.range.second - 0x100000 + 1), 4798323Ssteve.reinhardt@amd.com range_type = 1) 4808323Ssteve.reinhardt@amd.com ] 4815450Sgblack@eecs.umich.edu 4825330Sgblack@eecs.umich.edu # Command line 4835847Sgblack@eecs.umich.edu self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \ 4845845Sgblack@eecs.umich.edu 'root=/dev/hda1' 4855133Sgblack@eecs.umich.edu return self 4865133Sgblack@eecs.umich.edu 4873584Ssaidi@eecs.umich.edu 4883025Ssaidi@eecs.umich.edudef makeDualRoot(testSystem, driveSystem, dumpfile): 4892934Sktlim@umich.edu self = Root() 4902995Ssaidi@eecs.umich.edu self.testsys = testSystem 4912995Ssaidi@eecs.umich.edu self.drivesys = driveSystem 4924981Ssaidi@eecs.umich.edu self.etherlink = EtherLink() 4934981Ssaidi@eecs.umich.edu self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 4944981Ssaidi@eecs.umich.edu self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 4954981Ssaidi@eecs.umich.edu 4968661SAli.Saidi@ARM.com if hasattr(testSystem, 'realview'): 4978661SAli.Saidi@ARM.com self.etherlink.int0 = Parent.testsys.realview.ethernet.interface 4988661SAli.Saidi@ARM.com self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface 4998661SAli.Saidi@ARM.com elif hasattr(testSystem, 'tsunami'): 5008661SAli.Saidi@ARM.com self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 5018661SAli.Saidi@ARM.com self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 5028661SAli.Saidi@ARM.com else: 5038661SAli.Saidi@ARM.com fatal("Don't know how to connect these system together") 5048661SAli.Saidi@ARM.com 5053025Ssaidi@eecs.umich.edu if dumpfile: 5063025Ssaidi@eecs.umich.edu self.etherdump = EtherDump(file=dumpfile) 5073025Ssaidi@eecs.umich.edu self.etherlink.dump = Parent.etherdump 5082934Sktlim@umich.edu 5092934Sktlim@umich.edu return self 5105253Sksewell@umich.edu 5115263Sksewell@umich.edudef setMipsOptions(TestCPUClass): 5125253Sksewell@umich.edu #CP0 Configuration 5135253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_PRId_CompanyOptions = 0 5145253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_PRId_CompanyID = 1 5155253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_PRId_ProcessorID = 147 5165253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_PRId_Revision = 0 5175253Sksewell@umich.edu 5185253Sksewell@umich.edu #CP0 Interrupt Control 5195253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_IntCtl_IPTI = 7 5205253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_IntCtl_IPPCI = 7 5215253Sksewell@umich.edu 5225253Sksewell@umich.edu # Config Register 5235253Sksewell@umich.edu #TestCPUClass.CoreParams.CP0_Config_K23 = 0 # Since TLB 5245253Sksewell@umich.edu #TestCPUClass.CoreParams.CP0_Config_KU = 0 # Since TLB 5255253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config_BE = 0 # Little Endian 5265253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config_AR = 1 # Architecture Revision 2 5275253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config_AT = 0 # MIPS32 5285253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config_MT = 1 # TLB MMU 5295253Sksewell@umich.edu #TestCPUClass.CoreParams.CP0_Config_K0 = 2 # Uncached 5305253Sksewell@umich.edu 5315253Sksewell@umich.edu #Config 1 Register 5325253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_M = 1 # Config2 Implemented 5335253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_MMU = 63 # TLB Size 5345253Sksewell@umich.edu # ***VERY IMPORTANT*** 5355253Sksewell@umich.edu # Remember to modify CP0_Config1 according to cache specs 5365253Sksewell@umich.edu # Examine file ../common/Cache.py 5375253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_IS = 1 # I-Cache Sets Per Way, 16KB cache, i.e., 1 (128) 5385253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_IL = 5 # I-Cache Line Size, default in Cache.py is 64, i.e 5 5395253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_IA = 1 # I-Cache Associativity, default in Cache.py is 2, i.e, a value of 1 5405253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_DS = 2 # D-Cache Sets Per Way (see below), 32KB cache, i.e., 2 5415253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_DL = 5 # D-Cache Line Size, default is 64, i.e., 5 5425253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_DA = 1 # D-Cache Associativity, default is 2, i.e. 1 5435253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_C2 = 0 # Coprocessor 2 not implemented(?) 5445253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_MD = 0 # MDMX ASE not implemented in Mips32 5455253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_PC = 1 # Performance Counters Implemented 5465253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_WR = 0 # Watch Registers Implemented 5475253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_CA = 0 # Mips16e NOT implemented 5485253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_EP = 0 # EJTag Not Implemented 5495253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_FP = 0 # FPU Implemented 5505253Sksewell@umich.edu 5515253Sksewell@umich.edu #Config 2 Register 5525253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_M = 1 # Config3 Implemented 5535253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_TU = 0 # Tertiary Cache Control 5545253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_TS = 0 # Tertiary Cache Sets Per Way 5555253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_TL = 0 # Tertiary Cache Line Size 5565253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_TA = 0 # Tertiary Cache Associativity 5575253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_SU = 0 # Secondary Cache Control 5585253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_SS = 0 # Secondary Cache Sets Per Way 5595253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_SL = 0 # Secondary Cache Line Size 5605253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_SA = 0 # Secondary Cache Associativity 5615253Sksewell@umich.edu 5625253Sksewell@umich.edu 5635253Sksewell@umich.edu #Config 3 Register 5645253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_M = 0 # Config4 Not Implemented 5655253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_DSPP = 1 # DSP ASE Present 5665253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_LPA = 0 # Large Physical Addresses Not supported in Mips32 5675253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_VEIC = 0 # EIC Supported 5685253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_VInt = 0 # Vectored Interrupts Implemented 5695253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_SP = 0 # Small Pages Supported (PageGrain reg. exists) 5705253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_MT = 0 # MT Not present 5715253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_SM = 0 # SmartMIPS ASE Not implemented 5725253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_TL = 0 # TraceLogic Not implemented 5735253Sksewell@umich.edu 5745253Sksewell@umich.edu #SRS Ctl - HSS 5755253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_SrsCtl_HSS = 3 # Four shadow register sets implemented 5765253Sksewell@umich.edu 5775253Sksewell@umich.edu 5785253Sksewell@umich.edu #TestCPUClass.CoreParams.tlb = TLB() 5795253Sksewell@umich.edu #TestCPUClass.CoreParams.UnifiedTLB = 1 580