FSConfig.py revision 8061
17586SAli.Saidi@arm.com# Copyright (c) 2010 ARM Limited 27586SAli.Saidi@arm.com# All rights reserved. 37586SAli.Saidi@arm.com# 47586SAli.Saidi@arm.com# The license below extends only to copyright in the software and shall 57586SAli.Saidi@arm.com# not be construed as granting a license to any other intellectual 67586SAli.Saidi@arm.com# property including but not limited to intellectual property relating 77586SAli.Saidi@arm.com# to a hardware implementation of the functionality of the software 87586SAli.Saidi@arm.com# licensed hereunder. You may use the software subject to the license 97586SAli.Saidi@arm.com# terms below provided that you ensure that this notice is replicated 107586SAli.Saidi@arm.com# unmodified and in its entirety in all distributions of the software, 117586SAli.Saidi@arm.com# modified or unmodified, in source code or in binary form. 127586SAli.Saidi@arm.com# 137905SBrad.Beckmann@amd.com# Copyright (c) 2010-2011 Advanced Micro Devices, Inc. 145323Sgblack@eecs.umich.edu# Copyright (c) 2006-2008 The Regents of The University of Michigan 152934Sktlim@umich.edu# All rights reserved. 162934Sktlim@umich.edu# 172934Sktlim@umich.edu# Redistribution and use in source and binary forms, with or without 182934Sktlim@umich.edu# modification, are permitted provided that the following conditions are 192934Sktlim@umich.edu# met: redistributions of source code must retain the above copyright 202934Sktlim@umich.edu# notice, this list of conditions and the following disclaimer; 212934Sktlim@umich.edu# redistributions in binary form must reproduce the above copyright 222934Sktlim@umich.edu# notice, this list of conditions and the following disclaimer in the 232934Sktlim@umich.edu# documentation and/or other materials provided with the distribution; 242934Sktlim@umich.edu# neither the name of the copyright holders nor the names of its 252934Sktlim@umich.edu# contributors may be used to endorse or promote products derived from 262934Sktlim@umich.edu# this software without specific prior written permission. 272934Sktlim@umich.edu# 282934Sktlim@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292934Sktlim@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302934Sktlim@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312934Sktlim@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322934Sktlim@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332934Sktlim@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342934Sktlim@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352934Sktlim@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362934Sktlim@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372934Sktlim@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382934Sktlim@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392934Sktlim@umich.edu# 402934Sktlim@umich.edu# Authors: Kevin Lim 412934Sktlim@umich.edu 422934Sktlim@umich.edufrom m5.objects import * 432995Ssaidi@eecs.umich.edufrom Benchmarks import * 442934Sktlim@umich.edu 452934Sktlim@umich.educlass CowIdeDisk(IdeDisk): 462934Sktlim@umich.edu image = CowDiskImage(child=RawDiskImage(read_only=True), 472934Sktlim@umich.edu read_only=False) 482934Sktlim@umich.edu 492934Sktlim@umich.edu def childImage(self, ci): 502934Sktlim@umich.edu self.image.child.image_file = ci 512934Sktlim@umich.edu 526122SSteve.Reinhardt@amd.comclass MemBus(Bus): 536122SSteve.Reinhardt@amd.com badaddr_responder = BadAddr() 546122SSteve.Reinhardt@amd.com default = Self.badaddr_responder.pio 556122SSteve.Reinhardt@amd.com 566122SSteve.Reinhardt@amd.com 574520Ssaidi@eecs.umich.edudef makeLinuxAlphaSystem(mem_mode, mdesc = None): 584520Ssaidi@eecs.umich.edu class BaseTsunami(Tsunami): 594982Ssaidi@eecs.umich.edu ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 604520Ssaidi@eecs.umich.edu ide = IdeController(disks=[Parent.disk0, Parent.disk2], 614520Ssaidi@eecs.umich.edu pci_func=0, pci_dev=0, pci_bus=0) 622934Sktlim@umich.edu 632934Sktlim@umich.edu self = LinuxAlphaSystem() 643005Sstever@eecs.umich.edu if not mdesc: 653005Sstever@eecs.umich.edu # generic system 663304Sstever@eecs.umich.edu mdesc = SysConfig() 672995Ssaidi@eecs.umich.edu self.readfile = mdesc.script() 682934Sktlim@umich.edu self.iobus = Bus(bus_id=0) 696122SSteve.Reinhardt@amd.com self.membus = MemBus(bus_id=1) 704965Ssaidi@eecs.umich.edu self.bridge = Bridge(delay='50ns', nack_delay='4ns') 715266Sksewell@umich.edu self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) 722934Sktlim@umich.edu self.bridge.side_a = self.iobus.port 732934Sktlim@umich.edu self.bridge.side_b = self.membus.port 742934Sktlim@umich.edu self.physmem.port = self.membus.port 752934Sktlim@umich.edu self.disk0 = CowIdeDisk(driveID='master') 762934Sktlim@umich.edu self.disk2 = CowIdeDisk(driveID='master') 772995Ssaidi@eecs.umich.edu self.disk0.childImage(mdesc.disk()) 782934Sktlim@umich.edu self.disk2.childImage(disk('linux-bigswap2.img')) 792934Sktlim@umich.edu self.tsunami = BaseTsunami() 802934Sktlim@umich.edu self.tsunami.attachIO(self.iobus) 812934Sktlim@umich.edu self.tsunami.ide.pio = self.iobus.port 822934Sktlim@umich.edu self.tsunami.ethernet.pio = self.iobus.port 832995Ssaidi@eecs.umich.edu self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 842934Sktlim@umich.edu read_only = True)) 852934Sktlim@umich.edu self.intrctrl = IntrControl() 862953Sktlim@umich.edu self.mem_mode = mem_mode 875478Snate@binkert.org self.terminal = Terminal() 882934Sktlim@umich.edu self.kernel = binary('vmlinux') 893449Shsul@eecs.umich.edu self.pal = binary('ts_osfpal') 902934Sktlim@umich.edu self.console = binary('console') 912934Sktlim@umich.edu self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 922934Sktlim@umich.edu 932934Sktlim@umich.edu return self 942934Sktlim@umich.edu 957014SBrad.Beckmann@amd.comdef makeLinuxAlphaRubySystem(mem_mode, mdesc = None): 966765SBrad.Beckmann@amd.com class BaseTsunami(Tsunami): 976765SBrad.Beckmann@amd.com ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 986765SBrad.Beckmann@amd.com ide = IdeController(disks=[Parent.disk0, Parent.disk2], 996765SBrad.Beckmann@amd.com pci_func=0, pci_dev=0, pci_bus=0) 1006765SBrad.Beckmann@amd.com 1017014SBrad.Beckmann@amd.com physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) 1027014SBrad.Beckmann@amd.com self = LinuxAlphaSystem(physmem = physmem) 1036765SBrad.Beckmann@amd.com if not mdesc: 1046765SBrad.Beckmann@amd.com # generic system 1056765SBrad.Beckmann@amd.com mdesc = SysConfig() 1066765SBrad.Beckmann@amd.com self.readfile = mdesc.script() 1076765SBrad.Beckmann@amd.com 1086765SBrad.Beckmann@amd.com # Create pio bus to connect all device pio ports to rubymem's pio port 1096765SBrad.Beckmann@amd.com self.piobus = Bus(bus_id=0) 1106893SBrad.Beckmann@amd.com 1116893SBrad.Beckmann@amd.com # 1126893SBrad.Beckmann@amd.com # Pio functional accesses from devices need direct access to memory 1136893SBrad.Beckmann@amd.com # RubyPort currently does support functional accesses. Therefore provide 1146893SBrad.Beckmann@amd.com # the piobus a direct connection to physical memory 1156893SBrad.Beckmann@amd.com # 1167014SBrad.Beckmann@amd.com self.piobus.port = physmem.port 1176893SBrad.Beckmann@amd.com 1186765SBrad.Beckmann@amd.com self.disk0 = CowIdeDisk(driveID='master') 1196765SBrad.Beckmann@amd.com self.disk2 = CowIdeDisk(driveID='master') 1206765SBrad.Beckmann@amd.com self.disk0.childImage(mdesc.disk()) 1216765SBrad.Beckmann@amd.com self.disk2.childImage(disk('linux-bigswap2.img')) 1226765SBrad.Beckmann@amd.com self.tsunami = BaseTsunami() 1236765SBrad.Beckmann@amd.com self.tsunami.attachIO(self.piobus) 1246765SBrad.Beckmann@amd.com self.tsunami.ide.pio = self.piobus.port 1256765SBrad.Beckmann@amd.com self.tsunami.ethernet.pio = self.piobus.port 1266765SBrad.Beckmann@amd.com 1276893SBrad.Beckmann@amd.com # 1287633SBrad.Beckmann@amd.com # Store the dma devices for later connection to dma ruby ports. 1297633SBrad.Beckmann@amd.com # Append an underscore to dma_devices to avoid the SimObjectVector check. 1306893SBrad.Beckmann@amd.com # 1317633SBrad.Beckmann@amd.com self._dma_devices = [self.tsunami.ide, self.tsunami.ethernet] 1326765SBrad.Beckmann@amd.com 1336765SBrad.Beckmann@amd.com self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 1346765SBrad.Beckmann@amd.com read_only = True)) 1356765SBrad.Beckmann@amd.com self.intrctrl = IntrControl() 1366765SBrad.Beckmann@amd.com self.mem_mode = mem_mode 1376765SBrad.Beckmann@amd.com self.terminal = Terminal() 1386765SBrad.Beckmann@amd.com self.kernel = binary('vmlinux') 1396765SBrad.Beckmann@amd.com self.pal = binary('ts_osfpal') 1406765SBrad.Beckmann@amd.com self.console = binary('console') 1416765SBrad.Beckmann@amd.com self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 1426765SBrad.Beckmann@amd.com 1436765SBrad.Beckmann@amd.com return self 1446765SBrad.Beckmann@amd.com 1453584Ssaidi@eecs.umich.edudef makeSparcSystem(mem_mode, mdesc = None): 1464486Sbinkertn@umich.edu class CowMmDisk(MmDisk): 1474486Sbinkertn@umich.edu image = CowDiskImage(child=RawDiskImage(read_only=True), 1484486Sbinkertn@umich.edu read_only=False) 1494486Sbinkertn@umich.edu 1504486Sbinkertn@umich.edu def childImage(self, ci): 1514486Sbinkertn@umich.edu self.image.child.image_file = ci 1524486Sbinkertn@umich.edu 1533584Ssaidi@eecs.umich.edu self = SparcSystem() 1543584Ssaidi@eecs.umich.edu if not mdesc: 1553584Ssaidi@eecs.umich.edu # generic system 1563584Ssaidi@eecs.umich.edu mdesc = SysConfig() 1573584Ssaidi@eecs.umich.edu self.readfile = mdesc.script() 1583743Sgblack@eecs.umich.edu self.iobus = Bus(bus_id=0) 1596122SSteve.Reinhardt@amd.com self.membus = MemBus(bus_id=1) 1604972Ssaidi@eecs.umich.edu self.bridge = Bridge(delay='50ns', nack_delay='4ns') 1613743Sgblack@eecs.umich.edu self.t1000 = T1000() 1624104Ssaidi@eecs.umich.edu self.t1000.attachOnChipIO(self.membus) 1633743Sgblack@eecs.umich.edu self.t1000.attachIO(self.iobus) 1643823Ssaidi@eecs.umich.edu self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True) 1653814Ssaidi@eecs.umich.edu self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True) 1663743Sgblack@eecs.umich.edu self.bridge.side_a = self.iobus.port 1673743Sgblack@eecs.umich.edu self.bridge.side_b = self.membus.port 1683584Ssaidi@eecs.umich.edu self.physmem.port = self.membus.port 1693814Ssaidi@eecs.umich.edu self.physmem2.port = self.membus.port 1703584Ssaidi@eecs.umich.edu self.rom.port = self.membus.port 1713745Sgblack@eecs.umich.edu self.nvram.port = self.membus.port 1723745Sgblack@eecs.umich.edu self.hypervisor_desc.port = self.membus.port 1733745Sgblack@eecs.umich.edu self.partition_desc.port = self.membus.port 1743584Ssaidi@eecs.umich.edu self.intrctrl = IntrControl() 1753898Ssaidi@eecs.umich.edu self.disk0 = CowMmDisk() 1763898Ssaidi@eecs.umich.edu self.disk0.childImage(disk('disk.s10hw2')) 1773898Ssaidi@eecs.umich.edu self.disk0.pio = self.iobus.port 1784103Ssaidi@eecs.umich.edu self.reset_bin = binary('reset_new.bin') 1794103Ssaidi@eecs.umich.edu self.hypervisor_bin = binary('q_new.bin') 1804103Ssaidi@eecs.umich.edu self.openboot_bin = binary('openboot_new.bin') 1813745Sgblack@eecs.umich.edu self.nvram_bin = binary('nvram1') 1823745Sgblack@eecs.umich.edu self.hypervisor_desc_bin = binary('1up-hv.bin') 1833745Sgblack@eecs.umich.edu self.partition_desc_bin = binary('1up-md.bin') 1843584Ssaidi@eecs.umich.edu 1853584Ssaidi@eecs.umich.edu return self 1863584Ssaidi@eecs.umich.edu 1878061SAli.Saidi@ARM.comdef makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False): 1888061SAli.Saidi@ARM.com assert machine_type 1898061SAli.Saidi@ARM.com 1907586SAli.Saidi@arm.com if bare_metal: 1917586SAli.Saidi@arm.com self = ArmSystem() 1927586SAli.Saidi@arm.com else: 1937586SAli.Saidi@arm.com self = LinuxArmSystem() 1947586SAli.Saidi@arm.com 1957586SAli.Saidi@arm.com if not mdesc: 1967586SAli.Saidi@arm.com # generic system 1977586SAli.Saidi@arm.com mdesc = SysConfig() 1987586SAli.Saidi@arm.com 1997586SAli.Saidi@arm.com self.readfile = mdesc.script() 2007586SAli.Saidi@arm.com self.iobus = Bus(bus_id=0) 2017586SAli.Saidi@arm.com self.membus = MemBus(bus_id=1) 2027586SAli.Saidi@arm.com self.membus.badaddr_responder.warn_access = "warn" 2037586SAli.Saidi@arm.com self.bridge = Bridge(delay='50ns', nack_delay='4ns') 2047586SAli.Saidi@arm.com self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()), zero = True) 2057730SAli.Saidi@ARM.com self.diskmem = PhysicalMemory(range = AddrRange(Addr('128MB'), size = '128MB'), 2067730SAli.Saidi@ARM.com file = disk('ael-arm.ext2')) 2077586SAli.Saidi@arm.com self.bridge.side_a = self.iobus.port 2087586SAli.Saidi@arm.com self.bridge.side_b = self.membus.port 2097586SAli.Saidi@arm.com self.physmem.port = self.membus.port 2107730SAli.Saidi@ARM.com self.diskmem.port = self.membus.port 2117586SAli.Saidi@arm.com 2127586SAli.Saidi@arm.com self.mem_mode = mem_mode 2137586SAli.Saidi@arm.com 2147750SAli.Saidi@ARM.com #self.cf0 = CowIdeDisk(driveID='master') 2157750SAli.Saidi@ARM.com #self.cf0.childImage(mdesc.disk()) 2167750SAli.Saidi@ARM.com #self.cf_ctrl = IdeController(disks=[self.cf0], 2177750SAli.Saidi@ARM.com # pci_func = 0, pci_dev = 0, pci_bus = 0, 2187750SAli.Saidi@ARM.com # io_shift = 1, ctrl_offset = 2, Command = 0x1, 2197750SAli.Saidi@ARM.com # BAR0 = 0x18000000, BAR0Size = '16B', 2207750SAli.Saidi@ARM.com # BAR1 = 0x18000100, BAR1Size = '1B', 2217750SAli.Saidi@ARM.com # BAR0LegacyIO = True, BAR1LegacyIO = True,) 2227750SAli.Saidi@ARM.com #self.cf_ctrl.pio = self.iobus.port 2237750SAli.Saidi@ARM.com 2247586SAli.Saidi@arm.com if machine_type == "RealView_PBX": 2257586SAli.Saidi@arm.com self.realview = RealViewPBX() 2267586SAli.Saidi@arm.com elif machine_type == "RealView_EB": 2277586SAli.Saidi@arm.com self.realview = RealViewEB() 2287586SAli.Saidi@arm.com else: 2297586SAli.Saidi@arm.com print "Unknown Machine Type" 2307586SAli.Saidi@arm.com sys.exit(1) 2317586SAli.Saidi@arm.com 2328061SAli.Saidi@ARM.com if bare_metal: 2338061SAli.Saidi@ARM.com # EOT character on UART will end the simulation 2348061SAli.Saidi@ARM.com self.realview.uart.end_on_eot = True 2358061SAli.Saidi@ARM.com else: 2367586SAli.Saidi@arm.com self.machine_type = machine_type 2378061SAli.Saidi@ARM.com self.kernel = binary('vmlinux.arm') 2388061SAli.Saidi@ARM.com self.boot_osflags = 'earlyprintk mem=128MB console=ttyAMA0' + \ 2398061SAli.Saidi@ARM.com ' lpj=19988480 norandmaps slram=slram0,0x8000000,+0x8000000' + \ 2408061SAli.Saidi@ARM.com ' mtdparts=slram0:- rw loglevel=8 root=/dev/mtdblock0' 2417586SAli.Saidi@arm.com 2427586SAli.Saidi@arm.com self.realview.attachOnChipIO(self.membus) 2437586SAli.Saidi@arm.com self.realview.attachIO(self.iobus) 2447586SAli.Saidi@arm.com 2457586SAli.Saidi@arm.com self.intrctrl = IntrControl() 2467586SAli.Saidi@arm.com self.terminal = Terminal() 2477949SAli.Saidi@ARM.com self.vncserver = VncServer() 2487586SAli.Saidi@arm.com 2497586SAli.Saidi@arm.com return self 2507586SAli.Saidi@arm.com 2517586SAli.Saidi@arm.com 2525222Sksewell@umich.edudef makeLinuxMipsSystem(mem_mode, mdesc = None): 2535222Sksewell@umich.edu class BaseMalta(Malta): 2545222Sksewell@umich.edu ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 2555222Sksewell@umich.edu ide = IdeController(disks=[Parent.disk0, Parent.disk2], 2565222Sksewell@umich.edu pci_func=0, pci_dev=0, pci_bus=0) 2575222Sksewell@umich.edu 2585222Sksewell@umich.edu self = LinuxMipsSystem() 2595222Sksewell@umich.edu if not mdesc: 2605222Sksewell@umich.edu # generic system 2615222Sksewell@umich.edu mdesc = SysConfig() 2625222Sksewell@umich.edu self.readfile = mdesc.script() 2635222Sksewell@umich.edu self.iobus = Bus(bus_id=0) 2646122SSteve.Reinhardt@amd.com self.membus = MemBus(bus_id=1) 2655222Sksewell@umich.edu self.bridge = Bridge(delay='50ns', nack_delay='4ns') 2665222Sksewell@umich.edu self.physmem = PhysicalMemory(range = AddrRange('1GB')) 2675222Sksewell@umich.edu self.bridge.side_a = self.iobus.port 2685222Sksewell@umich.edu self.bridge.side_b = self.membus.port 2695222Sksewell@umich.edu self.physmem.port = self.membus.port 2705222Sksewell@umich.edu self.disk0 = CowIdeDisk(driveID='master') 2715222Sksewell@umich.edu self.disk2 = CowIdeDisk(driveID='master') 2725222Sksewell@umich.edu self.disk0.childImage(mdesc.disk()) 2735222Sksewell@umich.edu self.disk2.childImage(disk('linux-bigswap2.img')) 2745222Sksewell@umich.edu self.malta = BaseMalta() 2755222Sksewell@umich.edu self.malta.attachIO(self.iobus) 2765222Sksewell@umich.edu self.malta.ide.pio = self.iobus.port 2775222Sksewell@umich.edu self.malta.ethernet.pio = self.iobus.port 2785222Sksewell@umich.edu self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 2795222Sksewell@umich.edu read_only = True)) 2805222Sksewell@umich.edu self.intrctrl = IntrControl() 2815222Sksewell@umich.edu self.mem_mode = mem_mode 2825478Snate@binkert.org self.terminal = Terminal() 2835222Sksewell@umich.edu self.kernel = binary('mips/vmlinux') 2845222Sksewell@umich.edu self.console = binary('mips/console') 2855222Sksewell@umich.edu self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 2865222Sksewell@umich.edu 2875222Sksewell@umich.edu return self 2885222Sksewell@umich.edu 2895323Sgblack@eecs.umich.edudef x86IOAddress(port): 2905357Sgblack@eecs.umich.edu IO_address_space_base = 0x8000000000000000 2915323Sgblack@eecs.umich.edu return IO_address_space_base + port; 2925323Sgblack@eecs.umich.edu 2937905SBrad.Beckmann@amd.comdef connectX86ClassicSystem(x86_sys): 2947905SBrad.Beckmann@amd.com x86_sys.membus = MemBus(bus_id=1) 2957905SBrad.Beckmann@amd.com x86_sys.physmem.port = x86_sys.membus.port 2967905SBrad.Beckmann@amd.com 2977905SBrad.Beckmann@amd.com # North Bridge 2987905SBrad.Beckmann@amd.com x86_sys.iobus = Bus(bus_id=0) 2997905SBrad.Beckmann@amd.com x86_sys.bridge = Bridge(delay='50ns', nack_delay='4ns') 3007905SBrad.Beckmann@amd.com x86_sys.bridge.side_a = x86_sys.iobus.port 3017905SBrad.Beckmann@amd.com x86_sys.bridge.side_b = x86_sys.membus.port 3027905SBrad.Beckmann@amd.com 3037905SBrad.Beckmann@amd.com # connect the io bus 3047905SBrad.Beckmann@amd.com x86_sys.pc.attachIO(x86_sys.iobus) 3057905SBrad.Beckmann@amd.com 3067905SBrad.Beckmann@amd.comdef connectX86RubySystem(x86_sys): 3077905SBrad.Beckmann@amd.com # North Bridge 3087905SBrad.Beckmann@amd.com x86_sys.piobus = Bus(bus_id=0) 3097905SBrad.Beckmann@amd.com 3107905SBrad.Beckmann@amd.com # 3117905SBrad.Beckmann@amd.com # Pio functional accesses from devices need direct access to memory 3127905SBrad.Beckmann@amd.com # RubyPort currently does support functional accesses. Therefore provide 3137905SBrad.Beckmann@amd.com # the piobus a direct connection to physical memory 3147905SBrad.Beckmann@amd.com # 3157905SBrad.Beckmann@amd.com x86_sys.piobus.port = x86_sys.physmem.port 3167905SBrad.Beckmann@amd.com 3177905SBrad.Beckmann@amd.com x86_sys.pc.attachIO(x86_sys.piobus) 3187905SBrad.Beckmann@amd.com 3197905SBrad.Beckmann@amd.com 3207905SBrad.Beckmann@amd.comdef makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None, Ruby = False): 3215613Sgblack@eecs.umich.edu if self == None: 3225613Sgblack@eecs.umich.edu self = X86System() 3235613Sgblack@eecs.umich.edu 3245133Sgblack@eecs.umich.edu if not mdesc: 3255133Sgblack@eecs.umich.edu # generic system 3265133Sgblack@eecs.umich.edu mdesc = SysConfig() 3275133Sgblack@eecs.umich.edu self.readfile = mdesc.script() 3285133Sgblack@eecs.umich.edu 3296802Sgblack@eecs.umich.edu self.mem_mode = mem_mode 3306802Sgblack@eecs.umich.edu 3315133Sgblack@eecs.umich.edu # Physical memory 3325450Sgblack@eecs.umich.edu self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) 3335613Sgblack@eecs.umich.edu 3345613Sgblack@eecs.umich.edu # Platform 3355638Sgblack@eecs.umich.edu self.pc = Pc() 3367905SBrad.Beckmann@amd.com 3377905SBrad.Beckmann@amd.com # Create and connect the busses required by each memory system 3387905SBrad.Beckmann@amd.com if Ruby: 3397905SBrad.Beckmann@amd.com connectX86RubySystem(self) 3407937SBrad.Beckmann@amd.com # add the ide to the list of dma devices that later need to attach to 3417937SBrad.Beckmann@amd.com # dma controllers 3427937SBrad.Beckmann@amd.com self._dma_devices = [self.pc.south_bridge.ide] 3437905SBrad.Beckmann@amd.com else: 3447905SBrad.Beckmann@amd.com connectX86ClassicSystem(self) 3455613Sgblack@eecs.umich.edu 3465613Sgblack@eecs.umich.edu self.intrctrl = IntrControl() 3475613Sgblack@eecs.umich.edu 3485841Sgblack@eecs.umich.edu # Disks 3495841Sgblack@eecs.umich.edu disk0 = CowIdeDisk(driveID='master') 3505841Sgblack@eecs.umich.edu disk2 = CowIdeDisk(driveID='master') 3515841Sgblack@eecs.umich.edu disk0.childImage(mdesc.disk()) 3525841Sgblack@eecs.umich.edu disk2.childImage(disk('linux-bigswap2.img')) 3535841Sgblack@eecs.umich.edu self.pc.south_bridge.ide.disks = [disk0, disk2] 3545841Sgblack@eecs.umich.edu 3555615Sgblack@eecs.umich.edu # Add in a Bios information structure. 3565615Sgblack@eecs.umich.edu structures = [X86SMBiosBiosInformation()] 3575615Sgblack@eecs.umich.edu self.smbios_table.structures = structures 3585615Sgblack@eecs.umich.edu 3595641Sgblack@eecs.umich.edu # Set up the Intel MP table 3606135Sgblack@eecs.umich.edu for i in xrange(numCPUs): 3616135Sgblack@eecs.umich.edu bp = X86IntelMPProcessor( 3626135Sgblack@eecs.umich.edu local_apic_id = i, 3636135Sgblack@eecs.umich.edu local_apic_version = 0x14, 3646135Sgblack@eecs.umich.edu enable = True, 3656135Sgblack@eecs.umich.edu bootstrap = (i == 0)) 3666135Sgblack@eecs.umich.edu self.intel_mp_table.add_entry(bp) 3675644Sgblack@eecs.umich.edu io_apic = X86IntelMPIOAPIC( 3686135Sgblack@eecs.umich.edu id = numCPUs, 3695644Sgblack@eecs.umich.edu version = 0x11, 3705644Sgblack@eecs.umich.edu enable = True, 3715644Sgblack@eecs.umich.edu address = 0xfec00000) 3726135Sgblack@eecs.umich.edu self.pc.south_bridge.io_apic.apic_id = io_apic.id 3735644Sgblack@eecs.umich.edu self.intel_mp_table.add_entry(io_apic) 3745644Sgblack@eecs.umich.edu isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA') 3755644Sgblack@eecs.umich.edu self.intel_mp_table.add_entry(isa_bus) 3765843Sgblack@eecs.umich.edu pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI') 3775843Sgblack@eecs.umich.edu self.intel_mp_table.add_entry(pci_bus) 3785843Sgblack@eecs.umich.edu connect_busses = X86IntelMPBusHierarchy(bus_id=0, 3795843Sgblack@eecs.umich.edu subtractive_decode=True, parent_bus=1) 3805843Sgblack@eecs.umich.edu self.intel_mp_table.add_entry(connect_busses) 3815843Sgblack@eecs.umich.edu pci_dev4_inta = X86IntelMPIOIntAssignment( 3825843Sgblack@eecs.umich.edu interrupt_type = 'INT', 3835843Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 3845843Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 3855843Sgblack@eecs.umich.edu source_bus_id = 1, 3865843Sgblack@eecs.umich.edu source_bus_irq = 0 + (4 << 2), 3876044Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 3885843Sgblack@eecs.umich.edu dest_io_apic_intin = 16) 3896074Sgblack@eecs.umich.edu self.intel_mp_table.add_entry(pci_dev4_inta); 3906135Sgblack@eecs.umich.edu def assignISAInt(irq, apicPin): 3916135Sgblack@eecs.umich.edu assign_8259_to_apic = X86IntelMPIOIntAssignment( 3926135Sgblack@eecs.umich.edu interrupt_type = 'ExtInt', 3936135Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 3946135Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 3956135Sgblack@eecs.umich.edu source_bus_id = 0, 3966135Sgblack@eecs.umich.edu source_bus_irq = irq, 3976135Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 3986135Sgblack@eecs.umich.edu dest_io_apic_intin = 0) 3996135Sgblack@eecs.umich.edu self.intel_mp_table.add_entry(assign_8259_to_apic) 4006135Sgblack@eecs.umich.edu assign_to_apic = X86IntelMPIOIntAssignment( 4016135Sgblack@eecs.umich.edu interrupt_type = 'INT', 4026135Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 4036135Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 4046135Sgblack@eecs.umich.edu source_bus_id = 0, 4056135Sgblack@eecs.umich.edu source_bus_irq = irq, 4066135Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 4076135Sgblack@eecs.umich.edu dest_io_apic_intin = apicPin) 4086135Sgblack@eecs.umich.edu self.intel_mp_table.add_entry(assign_to_apic) 4096135Sgblack@eecs.umich.edu assignISAInt(0, 2) 4106135Sgblack@eecs.umich.edu assignISAInt(1, 1) 4116135Sgblack@eecs.umich.edu for i in range(3, 15): 4126135Sgblack@eecs.umich.edu assignISAInt(i, i) 4135641Sgblack@eecs.umich.edu 4147925Sgblack@eecs.umich.edudef setWorkCountOptions(system, options): 4157925Sgblack@eecs.umich.edu if options.work_item_id != None: 4167925Sgblack@eecs.umich.edu system.work_item_id = options.work_item_id 4177925Sgblack@eecs.umich.edu if options.work_begin_cpu_id_exit != None: 4187925Sgblack@eecs.umich.edu system.work_begin_cpu_id_exit = options.work_begin_cpu_id_exit 4197925Sgblack@eecs.umich.edu if options.work_end_exit_count != None: 4207925Sgblack@eecs.umich.edu system.work_end_exit_count = options.work_end_exit_count 4217925Sgblack@eecs.umich.edu if options.work_end_checkpoint_count != None: 4227925Sgblack@eecs.umich.edu system.work_end_ckpt_count = options.work_end_checkpoint_count 4237925Sgblack@eecs.umich.edu if options.work_begin_exit_count != None: 4247925Sgblack@eecs.umich.edu system.work_begin_exit_count = options.work_begin_exit_count 4257925Sgblack@eecs.umich.edu if options.work_begin_checkpoint_count != None: 4267925Sgblack@eecs.umich.edu system.work_begin_ckpt_count = options.work_begin_checkpoint_count 4277925Sgblack@eecs.umich.edu if options.work_cpus_checkpoint_count != None: 4287925Sgblack@eecs.umich.edu system.work_cpus_ckpt_count = options.work_cpus_checkpoint_count 4297925Sgblack@eecs.umich.edu 4307925Sgblack@eecs.umich.edu 4317925Sgblack@eecs.umich.edudef makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None, Ruby = False): 4325613Sgblack@eecs.umich.edu self = LinuxX86System() 4335613Sgblack@eecs.umich.edu 4347905SBrad.Beckmann@amd.com # Build up the x86 system and then specialize it for Linux 4357905SBrad.Beckmann@amd.com makeX86System(mem_mode, numCPUs, mdesc, self, Ruby) 4365613Sgblack@eecs.umich.edu 4375450Sgblack@eecs.umich.edu # We assume below that there's at least 1MB of memory. We'll require 2 4385450Sgblack@eecs.umich.edu # just to avoid corner cases. 4397069Snate@binkert.org assert(self.physmem.range.second.getValue() >= 0x200000) 4405450Sgblack@eecs.umich.edu 4415450Sgblack@eecs.umich.edu # Mark the first megabyte of memory as reserved 4425450Sgblack@eecs.umich.edu self.e820_table.entries.append(X86E820Entry( 4435450Sgblack@eecs.umich.edu addr = 0, 4445450Sgblack@eecs.umich.edu size = '1MB', 4455450Sgblack@eecs.umich.edu range_type = 2)) 4465450Sgblack@eecs.umich.edu 4475450Sgblack@eecs.umich.edu # Mark the rest as available 4485450Sgblack@eecs.umich.edu self.e820_table.entries.append(X86E820Entry( 4495450Sgblack@eecs.umich.edu addr = 0x100000, 4506072Sgblack@eecs.umich.edu size = '%dB' % (self.physmem.range.second - 0x100000 + 1), 4515450Sgblack@eecs.umich.edu range_type = 1)) 4525450Sgblack@eecs.umich.edu 4535330Sgblack@eecs.umich.edu # Command line 4545847Sgblack@eecs.umich.edu self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \ 4555845Sgblack@eecs.umich.edu 'root=/dev/hda1' 4565133Sgblack@eecs.umich.edu return self 4575133Sgblack@eecs.umich.edu 4583584Ssaidi@eecs.umich.edu 4593025Ssaidi@eecs.umich.edudef makeDualRoot(testSystem, driveSystem, dumpfile): 4602934Sktlim@umich.edu self = Root() 4612995Ssaidi@eecs.umich.edu self.testsys = testSystem 4622995Ssaidi@eecs.umich.edu self.drivesys = driveSystem 4634981Ssaidi@eecs.umich.edu self.etherlink = EtherLink() 4644981Ssaidi@eecs.umich.edu self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 4654981Ssaidi@eecs.umich.edu self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 4664981Ssaidi@eecs.umich.edu 4673025Ssaidi@eecs.umich.edu if dumpfile: 4683025Ssaidi@eecs.umich.edu self.etherdump = EtherDump(file=dumpfile) 4693025Ssaidi@eecs.umich.edu self.etherlink.dump = Parent.etherdump 4702934Sktlim@umich.edu 4712934Sktlim@umich.edu return self 4725253Sksewell@umich.edu 4735263Sksewell@umich.edudef setMipsOptions(TestCPUClass): 4745253Sksewell@umich.edu #CP0 Configuration 4755253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_PRId_CompanyOptions = 0 4765253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_PRId_CompanyID = 1 4775253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_PRId_ProcessorID = 147 4785253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_PRId_Revision = 0 4795253Sksewell@umich.edu 4805253Sksewell@umich.edu #CP0 Interrupt Control 4815253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_IntCtl_IPTI = 7 4825253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_IntCtl_IPPCI = 7 4835253Sksewell@umich.edu 4845253Sksewell@umich.edu # Config Register 4855253Sksewell@umich.edu #TestCPUClass.CoreParams.CP0_Config_K23 = 0 # Since TLB 4865253Sksewell@umich.edu #TestCPUClass.CoreParams.CP0_Config_KU = 0 # Since TLB 4875253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config_BE = 0 # Little Endian 4885253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config_AR = 1 # Architecture Revision 2 4895253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config_AT = 0 # MIPS32 4905253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config_MT = 1 # TLB MMU 4915253Sksewell@umich.edu #TestCPUClass.CoreParams.CP0_Config_K0 = 2 # Uncached 4925253Sksewell@umich.edu 4935253Sksewell@umich.edu #Config 1 Register 4945253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_M = 1 # Config2 Implemented 4955253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_MMU = 63 # TLB Size 4965253Sksewell@umich.edu # ***VERY IMPORTANT*** 4975253Sksewell@umich.edu # Remember to modify CP0_Config1 according to cache specs 4985253Sksewell@umich.edu # Examine file ../common/Cache.py 4995253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_IS = 1 # I-Cache Sets Per Way, 16KB cache, i.e., 1 (128) 5005253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_IL = 5 # I-Cache Line Size, default in Cache.py is 64, i.e 5 5015253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_IA = 1 # I-Cache Associativity, default in Cache.py is 2, i.e, a value of 1 5025253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_DS = 2 # D-Cache Sets Per Way (see below), 32KB cache, i.e., 2 5035253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_DL = 5 # D-Cache Line Size, default is 64, i.e., 5 5045253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_DA = 1 # D-Cache Associativity, default is 2, i.e. 1 5055253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_C2 = 0 # Coprocessor 2 not implemented(?) 5065253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_MD = 0 # MDMX ASE not implemented in Mips32 5075253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_PC = 1 # Performance Counters Implemented 5085253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_WR = 0 # Watch Registers Implemented 5095253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_CA = 0 # Mips16e NOT implemented 5105253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_EP = 0 # EJTag Not Implemented 5115253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_FP = 0 # FPU Implemented 5125253Sksewell@umich.edu 5135253Sksewell@umich.edu #Config 2 Register 5145253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_M = 1 # Config3 Implemented 5155253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_TU = 0 # Tertiary Cache Control 5165253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_TS = 0 # Tertiary Cache Sets Per Way 5175253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_TL = 0 # Tertiary Cache Line Size 5185253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_TA = 0 # Tertiary Cache Associativity 5195253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_SU = 0 # Secondary Cache Control 5205253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_SS = 0 # Secondary Cache Sets Per Way 5215253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_SL = 0 # Secondary Cache Line Size 5225253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_SA = 0 # Secondary Cache Associativity 5235253Sksewell@umich.edu 5245253Sksewell@umich.edu 5255253Sksewell@umich.edu #Config 3 Register 5265253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_M = 0 # Config4 Not Implemented 5275253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_DSPP = 1 # DSP ASE Present 5285253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_LPA = 0 # Large Physical Addresses Not supported in Mips32 5295253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_VEIC = 0 # EIC Supported 5305253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_VInt = 0 # Vectored Interrupts Implemented 5315253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_SP = 0 # Small Pages Supported (PageGrain reg. exists) 5325253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_MT = 0 # MT Not present 5335253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_SM = 0 # SmartMIPS ASE Not implemented 5345253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_TL = 0 # TraceLogic Not implemented 5355253Sksewell@umich.edu 5365253Sksewell@umich.edu #SRS Ctl - HSS 5375253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_SrsCtl_HSS = 3 # Four shadow register sets implemented 5385253Sksewell@umich.edu 5395253Sksewell@umich.edu 5405253Sksewell@umich.edu #TestCPUClass.CoreParams.tlb = TLB() 5415253Sksewell@umich.edu #TestCPUClass.CoreParams.UnifiedTLB = 1 542