FSConfig.py revision 7937
1955SN/A# Copyright (c) 2010 ARM Limited 2955SN/A# All rights reserved. 31762SN/A# 4955SN/A# The license below extends only to copyright in the software and shall 5955SN/A# not be construed as granting a license to any other intellectual 6955SN/A# property including but not limited to intellectual property relating 7955SN/A# to a hardware implementation of the functionality of the software 8955SN/A# licensed hereunder. You may use the software subject to the license 9955SN/A# terms below provided that you ensure that this notice is replicated 10955SN/A# unmodified and in its entirety in all distributions of the software, 11955SN/A# modified or unmodified, in source code or in binary form. 12955SN/A# 13955SN/A# Copyright (c) 2010-2011 Advanced Micro Devices, Inc. 14955SN/A# Copyright (c) 2006-2008 The Regents of The University of Michigan 15955SN/A# All rights reserved. 16955SN/A# 17955SN/A# Redistribution and use in source and binary forms, with or without 18955SN/A# modification, are permitted provided that the following conditions are 19955SN/A# met: redistributions of source code must retain the above copyright 20955SN/A# notice, this list of conditions and the following disclaimer; 21955SN/A# redistributions in binary form must reproduce the above copyright 22955SN/A# notice, this list of conditions and the following disclaimer in the 23955SN/A# documentation and/or other materials provided with the distribution; 24955SN/A# neither the name of the copyright holders nor the names of its 25955SN/A# contributors may be used to endorse or promote products derived from 26955SN/A# this software without specific prior written permission. 27955SN/A# 28955SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29955SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30955SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31955SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32955SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332632Sstever@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342632Sstever@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352632Sstever@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362632Sstever@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37955SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382632Sstever@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392632Sstever@eecs.umich.edu# 402632Sstever@eecs.umich.edu# Authors: Kevin Lim 412632Sstever@eecs.umich.edu 422632Sstever@eecs.umich.edufrom m5.objects import * 432632Sstever@eecs.umich.edufrom Benchmarks import * 442632Sstever@eecs.umich.edu 452632Sstever@eecs.umich.educlass CowIdeDisk(IdeDisk): 462632Sstever@eecs.umich.edu image = CowDiskImage(child=RawDiskImage(read_only=True), 472632Sstever@eecs.umich.edu read_only=False) 482632Sstever@eecs.umich.edu 492632Sstever@eecs.umich.edu def childImage(self, ci): 502632Sstever@eecs.umich.edu self.image.child.image_file = ci 512632Sstever@eecs.umich.edu 522632Sstever@eecs.umich.educlass MemBus(Bus): 532632Sstever@eecs.umich.edu badaddr_responder = BadAddr() 542632Sstever@eecs.umich.edu default = Self.badaddr_responder.pio 552632Sstever@eecs.umich.edu 562632Sstever@eecs.umich.edu 572632Sstever@eecs.umich.edudef makeLinuxAlphaSystem(mem_mode, mdesc = None): 58955SN/A class BaseTsunami(Tsunami): 59955SN/A ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 60955SN/A ide = IdeController(disks=[Parent.disk0, Parent.disk2], 61955SN/A pci_func=0, pci_dev=0, pci_bus=0) 62955SN/A 63955SN/A self = LinuxAlphaSystem() 64955SN/A if not mdesc: 651858SN/A # generic system 661858SN/A mdesc = SysConfig() 672632Sstever@eecs.umich.edu self.readfile = mdesc.script() 681852SN/A self.iobus = Bus(bus_id=0) 69955SN/A self.membus = MemBus(bus_id=1) 70955SN/A self.bridge = Bridge(delay='50ns', nack_delay='4ns') 71955SN/A self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) 722632Sstever@eecs.umich.edu self.bridge.side_a = self.iobus.port 732632Sstever@eecs.umich.edu self.bridge.side_b = self.membus.port 74955SN/A self.physmem.port = self.membus.port 751533SN/A self.disk0 = CowIdeDisk(driveID='master') 762632Sstever@eecs.umich.edu self.disk2 = CowIdeDisk(driveID='master') 771533SN/A self.disk0.childImage(mdesc.disk()) 78955SN/A self.disk2.childImage(disk('linux-bigswap2.img')) 79955SN/A self.tsunami = BaseTsunami() 802632Sstever@eecs.umich.edu self.tsunami.attachIO(self.iobus) 812632Sstever@eecs.umich.edu self.tsunami.ide.pio = self.iobus.port 82955SN/A self.tsunami.ethernet.pio = self.iobus.port 83955SN/A self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 84955SN/A read_only = True)) 85955SN/A self.intrctrl = IntrControl() 862632Sstever@eecs.umich.edu self.mem_mode = mem_mode 87955SN/A self.terminal = Terminal() 882632Sstever@eecs.umich.edu self.kernel = binary('vmlinux') 89955SN/A self.pal = binary('ts_osfpal') 90955SN/A self.console = binary('console') 912632Sstever@eecs.umich.edu self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 922632Sstever@eecs.umich.edu 932632Sstever@eecs.umich.edu return self 942632Sstever@eecs.umich.edu 952632Sstever@eecs.umich.edudef makeLinuxAlphaRubySystem(mem_mode, mdesc = None): 962632Sstever@eecs.umich.edu class BaseTsunami(Tsunami): 972632Sstever@eecs.umich.edu ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 982632Sstever@eecs.umich.edu ide = IdeController(disks=[Parent.disk0, Parent.disk2], 992632Sstever@eecs.umich.edu pci_func=0, pci_dev=0, pci_bus=0) 1002632Sstever@eecs.umich.edu 1012632Sstever@eecs.umich.edu physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) 1022632Sstever@eecs.umich.edu self = LinuxAlphaSystem(physmem = physmem) 1032632Sstever@eecs.umich.edu if not mdesc: 1042632Sstever@eecs.umich.edu # generic system 1052632Sstever@eecs.umich.edu mdesc = SysConfig() 1062632Sstever@eecs.umich.edu self.readfile = mdesc.script() 1072632Sstever@eecs.umich.edu 1082634Sstever@eecs.umich.edu # Create pio bus to connect all device pio ports to rubymem's pio port 1092634Sstever@eecs.umich.edu self.piobus = Bus(bus_id=0) 1102632Sstever@eecs.umich.edu 1112634Sstever@eecs.umich.edu # 1122632Sstever@eecs.umich.edu # Pio functional accesses from devices need direct access to memory 1132632Sstever@eecs.umich.edu # RubyPort currently does support functional accesses. Therefore provide 1142632Sstever@eecs.umich.edu # the piobus a direct connection to physical memory 1152632Sstever@eecs.umich.edu # 1162632Sstever@eecs.umich.edu self.piobus.port = physmem.port 1172632Sstever@eecs.umich.edu 1181858SN/A self.disk0 = CowIdeDisk(driveID='master') 1192634Sstever@eecs.umich.edu self.disk2 = CowIdeDisk(driveID='master') 1202634Sstever@eecs.umich.edu self.disk0.childImage(mdesc.disk()) 1212634Sstever@eecs.umich.edu self.disk2.childImage(disk('linux-bigswap2.img')) 1222634Sstever@eecs.umich.edu self.tsunami = BaseTsunami() 1232634Sstever@eecs.umich.edu self.tsunami.attachIO(self.piobus) 1242634Sstever@eecs.umich.edu self.tsunami.ide.pio = self.piobus.port 125955SN/A self.tsunami.ethernet.pio = self.piobus.port 126955SN/A 127955SN/A # 128955SN/A # Store the dma devices for later connection to dma ruby ports. 129955SN/A # Append an underscore to dma_devices to avoid the SimObjectVector check. 130955SN/A # 131955SN/A self._dma_devices = [self.tsunami.ide, self.tsunami.ethernet] 132955SN/A 1331858SN/A self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 1341858SN/A read_only = True)) 1352632Sstever@eecs.umich.edu self.intrctrl = IntrControl() 136955SN/A self.mem_mode = mem_mode 1371858SN/A self.terminal = Terminal() 1381105SN/A self.kernel = binary('vmlinux') 1391869SN/A self.pal = binary('ts_osfpal') 1401869SN/A self.console = binary('console') 1411869SN/A self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 1421869SN/A 1431869SN/A return self 1441065SN/A 1452632Sstever@eecs.umich.edudef makeSparcSystem(mem_mode, mdesc = None): 1462632Sstever@eecs.umich.edu class CowMmDisk(MmDisk): 147955SN/A image = CowDiskImage(child=RawDiskImage(read_only=True), 1481858SN/A read_only=False) 1491858SN/A 1501858SN/A def childImage(self, ci): 1511858SN/A self.image.child.image_file = ci 1521851SN/A 1531851SN/A self = SparcSystem() 1541858SN/A if not mdesc: 1552632Sstever@eecs.umich.edu # generic system 156955SN/A mdesc = SysConfig() 1571858SN/A self.readfile = mdesc.script() 1581858SN/A self.iobus = Bus(bus_id=0) 1591858SN/A self.membus = MemBus(bus_id=1) 1601858SN/A self.bridge = Bridge(delay='50ns', nack_delay='4ns') 1611858SN/A self.t1000 = T1000() 1621858SN/A self.t1000.attachOnChipIO(self.membus) 1631858SN/A self.t1000.attachIO(self.iobus) 1641858SN/A self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True) 1651858SN/A self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True) 1661858SN/A self.bridge.side_a = self.iobus.port 1671858SN/A self.bridge.side_b = self.membus.port 1681858SN/A self.physmem.port = self.membus.port 1691859SN/A self.physmem2.port = self.membus.port 1701858SN/A self.rom.port = self.membus.port 1711858SN/A self.nvram.port = self.membus.port 1721858SN/A self.hypervisor_desc.port = self.membus.port 1731859SN/A self.partition_desc.port = self.membus.port 1741859SN/A self.intrctrl = IntrControl() 1751862SN/A self.disk0 = CowMmDisk() 1761862SN/A self.disk0.childImage(disk('disk.s10hw2')) 1771862SN/A self.disk0.pio = self.iobus.port 1781862SN/A self.reset_bin = binary('reset_new.bin') 1791859SN/A self.hypervisor_bin = binary('q_new.bin') 1801859SN/A self.openboot_bin = binary('openboot_new.bin') 1811963SN/A self.nvram_bin = binary('nvram1') 1821963SN/A self.hypervisor_desc_bin = binary('1up-hv.bin') 1831859SN/A self.partition_desc_bin = binary('1up-md.bin') 1841859SN/A 1851859SN/A return self 1861859SN/A 1871859SN/Adef makeLinuxArmSystem(mem_mode, mdesc = None, bare_metal=False, 1881859SN/A machine_type = None): 1891859SN/A if bare_metal: 1901859SN/A self = ArmSystem() 1911862SN/A else: 1921859SN/A self = LinuxArmSystem() 1931859SN/A 1941859SN/A if not mdesc: 1951858SN/A # generic system 1961858SN/A mdesc = SysConfig() 1972139SN/A 1982139SN/A self.readfile = mdesc.script() 1992139SN/A self.iobus = Bus(bus_id=0) 2002155SN/A self.membus = MemBus(bus_id=1) 2012623SN/A self.membus.badaddr_responder.warn_access = "warn" 2022623SN/A self.bridge = Bridge(delay='50ns', nack_delay='4ns') 2032155SN/A self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()), zero = True) 2041869SN/A self.diskmem = PhysicalMemory(range = AddrRange(Addr('128MB'), size = '128MB'), 2051869SN/A file = disk('ael-arm.ext2')) 2061869SN/A self.bridge.side_a = self.iobus.port 2071869SN/A self.bridge.side_b = self.membus.port 2081869SN/A self.physmem.port = self.membus.port 2092139SN/A self.diskmem.port = self.membus.port 2101869SN/A 2112508SN/A self.mem_mode = mem_mode 2122508SN/A 2132508SN/A #self.cf0 = CowIdeDisk(driveID='master') 2142508SN/A #self.cf0.childImage(mdesc.disk()) 2152635Sstever@eecs.umich.edu #self.cf_ctrl = IdeController(disks=[self.cf0], 2162635Sstever@eecs.umich.edu # pci_func = 0, pci_dev = 0, pci_bus = 0, 2171869SN/A # io_shift = 1, ctrl_offset = 2, Command = 0x1, 2181869SN/A # BAR0 = 0x18000000, BAR0Size = '16B', 2191869SN/A # BAR1 = 0x18000100, BAR1Size = '1B', 2201869SN/A # BAR0LegacyIO = True, BAR1LegacyIO = True,) 2211869SN/A #self.cf_ctrl.pio = self.iobus.port 2221869SN/A 2231869SN/A if machine_type == "RealView_PBX": 2241869SN/A self.realview = RealViewPBX() 2251965SN/A elif machine_type == "RealView_EB": 2261965SN/A self.realview = RealViewEB() 2271965SN/A else: 2281869SN/A print "Unknown Machine Type" 2291869SN/A sys.exit(1) 2301869SN/A 2311869SN/A if not bare_metal and machine_type: 2321884SN/A self.machine_type = machine_type 2331884SN/A elif bare_metal: 2341884SN/A self.realview.uart.end_on_eot = True 2351869SN/A 2361858SN/A self.realview.attachOnChipIO(self.membus) 2371869SN/A self.realview.attachIO(self.iobus) 2381869SN/A 2391869SN/A self.intrctrl = IntrControl() 2401869SN/A self.terminal = Terminal() 2411869SN/A self.kernel = binary('vmlinux.arm') 2421858SN/A self.boot_osflags = 'earlyprintk mem=128MB console=ttyAMA0 lpj=19988480' + \ 2431869SN/A ' norandmaps slram=slram0,0x8000000,+0x8000000' + \ 2441869SN/A ' mtdparts=slram0:- rw loglevel=8 root=/dev/mtdblock0' 2451869SN/A 2461869SN/A return self 2471869SN/A 2481869SN/A 2491869SN/Adef makeLinuxMipsSystem(mem_mode, mdesc = None): 2501869SN/A class BaseMalta(Malta): 2511869SN/A ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 2521869SN/A ide = IdeController(disks=[Parent.disk0, Parent.disk2], 2531858SN/A pci_func=0, pci_dev=0, pci_bus=0) 254955SN/A 255955SN/A self = LinuxMipsSystem() 2561869SN/A if not mdesc: 2571869SN/A # generic system 2581869SN/A mdesc = SysConfig() 2591869SN/A self.readfile = mdesc.script() 2601869SN/A self.iobus = Bus(bus_id=0) 2611869SN/A self.membus = MemBus(bus_id=1) 2621869SN/A self.bridge = Bridge(delay='50ns', nack_delay='4ns') 2631869SN/A self.physmem = PhysicalMemory(range = AddrRange('1GB')) 2641869SN/A self.bridge.side_a = self.iobus.port 2651869SN/A self.bridge.side_b = self.membus.port 2661869SN/A self.physmem.port = self.membus.port 2671869SN/A self.disk0 = CowIdeDisk(driveID='master') 2681869SN/A self.disk2 = CowIdeDisk(driveID='master') 2691869SN/A self.disk0.childImage(mdesc.disk()) 2701869SN/A self.disk2.childImage(disk('linux-bigswap2.img')) 2711869SN/A self.malta = BaseMalta() 2721869SN/A self.malta.attachIO(self.iobus) 2731869SN/A self.malta.ide.pio = self.iobus.port 2741869SN/A self.malta.ethernet.pio = self.iobus.port 2751869SN/A self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 2761869SN/A read_only = True)) 2771869SN/A self.intrctrl = IntrControl() 2781869SN/A self.mem_mode = mem_mode 2791869SN/A self.terminal = Terminal() 2801869SN/A self.kernel = binary('mips/vmlinux') 2811869SN/A self.console = binary('mips/console') 2821869SN/A self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 2831869SN/A 2841869SN/A return self 2851869SN/A 2861869SN/Adef x86IOAddress(port): 2871869SN/A IO_address_space_base = 0x8000000000000000 2881869SN/A return IO_address_space_base + port; 2891869SN/A 2901869SN/Adef connectX86ClassicSystem(x86_sys): 2911869SN/A x86_sys.membus = MemBus(bus_id=1) 2921869SN/A x86_sys.physmem.port = x86_sys.membus.port 2931869SN/A 2941869SN/A # North Bridge 2952634Sstever@eecs.umich.edu x86_sys.iobus = Bus(bus_id=0) 2962634Sstever@eecs.umich.edu x86_sys.bridge = Bridge(delay='50ns', nack_delay='4ns') 2972634Sstever@eecs.umich.edu x86_sys.bridge.side_a = x86_sys.iobus.port 2982634Sstever@eecs.umich.edu x86_sys.bridge.side_b = x86_sys.membus.port 2992634Sstever@eecs.umich.edu 3002634Sstever@eecs.umich.edu # connect the io bus 3011869SN/A x86_sys.pc.attachIO(x86_sys.iobus) 3021869SN/A 303955SN/Adef connectX86RubySystem(x86_sys): 304955SN/A # North Bridge 305955SN/A x86_sys.piobus = Bus(bus_id=0) 306955SN/A 3071858SN/A # 3081858SN/A # Pio functional accesses from devices need direct access to memory 3091858SN/A # RubyPort currently does support functional accesses. Therefore provide 3102634Sstever@eecs.umich.edu # the piobus a direct connection to physical memory 3112634Sstever@eecs.umich.edu # 3122634Sstever@eecs.umich.edu x86_sys.piobus.port = x86_sys.physmem.port 3132634Sstever@eecs.umich.edu 3142634Sstever@eecs.umich.edu x86_sys.pc.attachIO(x86_sys.piobus) 3152634Sstever@eecs.umich.edu 3162634Sstever@eecs.umich.edu 3172634Sstever@eecs.umich.edudef makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None, Ruby = False): 3182634Sstever@eecs.umich.edu if self == None: 3192634Sstever@eecs.umich.edu self = X86System() 3202598SN/A 3212632Sstever@eecs.umich.edu if not mdesc: 3222632Sstever@eecs.umich.edu # generic system 3232632Sstever@eecs.umich.edu mdesc = SysConfig() 3242632Sstever@eecs.umich.edu self.readfile = mdesc.script() 3252632Sstever@eecs.umich.edu 3262634Sstever@eecs.umich.edu self.mem_mode = mem_mode 3272634Sstever@eecs.umich.edu 3282023SN/A # Physical memory 3292632Sstever@eecs.umich.edu self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) 3302632Sstever@eecs.umich.edu 3312632Sstever@eecs.umich.edu # Platform 3322632Sstever@eecs.umich.edu self.pc = Pc() 3332632Sstever@eecs.umich.edu 3342632Sstever@eecs.umich.edu # Create and connect the busses required by each memory system 3352632Sstever@eecs.umich.edu if Ruby: 3362632Sstever@eecs.umich.edu connectX86RubySystem(self) 3372632Sstever@eecs.umich.edu # add the ide to the list of dma devices that later need to attach to 3382632Sstever@eecs.umich.edu # dma controllers 3392632Sstever@eecs.umich.edu self._dma_devices = [self.pc.south_bridge.ide] 3402023SN/A else: 3412632Sstever@eecs.umich.edu connectX86ClassicSystem(self) 3422632Sstever@eecs.umich.edu 3431889SN/A self.intrctrl = IntrControl() 3441889SN/A 3452632Sstever@eecs.umich.edu # Disks 3462632Sstever@eecs.umich.edu disk0 = CowIdeDisk(driveID='master') 3472632Sstever@eecs.umich.edu disk2 = CowIdeDisk(driveID='master') 3482632Sstever@eecs.umich.edu disk0.childImage(mdesc.disk()) 3492632Sstever@eecs.umich.edu disk2.childImage(disk('linux-bigswap2.img')) 3502632Sstever@eecs.umich.edu self.pc.south_bridge.ide.disks = [disk0, disk2] 3512632Sstever@eecs.umich.edu 3522632Sstever@eecs.umich.edu # Add in a Bios information structure. 3532632Sstever@eecs.umich.edu structures = [X86SMBiosBiosInformation()] 3542632Sstever@eecs.umich.edu self.smbios_table.structures = structures 3552632Sstever@eecs.umich.edu 3562632Sstever@eecs.umich.edu # Set up the Intel MP table 3572632Sstever@eecs.umich.edu for i in xrange(numCPUs): 3582632Sstever@eecs.umich.edu bp = X86IntelMPProcessor( 3591888SN/A local_apic_id = i, 3601888SN/A local_apic_version = 0x14, 3611869SN/A enable = True, 3621869SN/A bootstrap = (i == 0)) 3631858SN/A self.intel_mp_table.add_entry(bp) 3642598SN/A io_apic = X86IntelMPIOAPIC( 3652598SN/A id = numCPUs, 3662598SN/A version = 0x11, 3672598SN/A enable = True, 3682598SN/A address = 0xfec00000) 3691858SN/A self.pc.south_bridge.io_apic.apic_id = io_apic.id 3701858SN/A self.intel_mp_table.add_entry(io_apic) 3711858SN/A isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA') 3721858SN/A self.intel_mp_table.add_entry(isa_bus) 3731858SN/A pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI') 3741858SN/A self.intel_mp_table.add_entry(pci_bus) 3751858SN/A connect_busses = X86IntelMPBusHierarchy(bus_id=0, 3761858SN/A subtractive_decode=True, parent_bus=1) 3771858SN/A self.intel_mp_table.add_entry(connect_busses) 3781871SN/A pci_dev4_inta = X86IntelMPIOIntAssignment( 3791858SN/A interrupt_type = 'INT', 3801858SN/A polarity = 'ConformPolarity', 3811858SN/A trigger = 'ConformTrigger', 3821858SN/A source_bus_id = 1, 3831858SN/A source_bus_irq = 0 + (4 << 2), 3841858SN/A dest_io_apic_id = io_apic.id, 3851858SN/A dest_io_apic_intin = 16) 3861858SN/A self.intel_mp_table.add_entry(pci_dev4_inta); 3871858SN/A def assignISAInt(irq, apicPin): 3881858SN/A assign_8259_to_apic = X86IntelMPIOIntAssignment( 3891858SN/A interrupt_type = 'ExtInt', 3901859SN/A polarity = 'ConformPolarity', 3911859SN/A trigger = 'ConformTrigger', 3921869SN/A source_bus_id = 0, 3931888SN/A source_bus_irq = irq, 3942632Sstever@eecs.umich.edu dest_io_apic_id = io_apic.id, 3951869SN/A dest_io_apic_intin = 0) 3961884SN/A self.intel_mp_table.add_entry(assign_8259_to_apic) 3971884SN/A assign_to_apic = X86IntelMPIOIntAssignment( 3981884SN/A interrupt_type = 'INT', 3991884SN/A polarity = 'ConformPolarity', 4001884SN/A trigger = 'ConformTrigger', 4011884SN/A source_bus_id = 0, 4021965SN/A source_bus_irq = irq, 4031965SN/A dest_io_apic_id = io_apic.id, 4041965SN/A dest_io_apic_intin = apicPin) 405955SN/A self.intel_mp_table.add_entry(assign_to_apic) 4061869SN/A assignISAInt(0, 2) 4071869SN/A assignISAInt(1, 1) 4082632Sstever@eecs.umich.edu for i in range(3, 15): 4091869SN/A assignISAInt(i, i) 4101869SN/A 4111869SN/Adef setWorkCountOptions(system, options): 4122632Sstever@eecs.umich.edu if options.work_item_id != None: 4132632Sstever@eecs.umich.edu system.work_item_id = options.work_item_id 4142632Sstever@eecs.umich.edu if options.work_begin_cpu_id_exit != None: 4152632Sstever@eecs.umich.edu system.work_begin_cpu_id_exit = options.work_begin_cpu_id_exit 416955SN/A if options.work_end_exit_count != None: 4172598SN/A system.work_end_exit_count = options.work_end_exit_count 4182598SN/A if options.work_end_checkpoint_count != None: 419955SN/A system.work_end_ckpt_count = options.work_end_checkpoint_count 420955SN/A if options.work_begin_exit_count != None: 421955SN/A system.work_begin_exit_count = options.work_begin_exit_count 4221530SN/A if options.work_begin_checkpoint_count != None: 423955SN/A system.work_begin_ckpt_count = options.work_begin_checkpoint_count 424955SN/A if options.work_cpus_checkpoint_count != None: 425955SN/A system.work_cpus_ckpt_count = options.work_cpus_checkpoint_count 426 427 428def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None, Ruby = False): 429 self = LinuxX86System() 430 431 # Build up the x86 system and then specialize it for Linux 432 makeX86System(mem_mode, numCPUs, mdesc, self, Ruby) 433 434 # We assume below that there's at least 1MB of memory. We'll require 2 435 # just to avoid corner cases. 436 assert(self.physmem.range.second.getValue() >= 0x200000) 437 438 # Mark the first megabyte of memory as reserved 439 self.e820_table.entries.append(X86E820Entry( 440 addr = 0, 441 size = '1MB', 442 range_type = 2)) 443 444 # Mark the rest as available 445 self.e820_table.entries.append(X86E820Entry( 446 addr = 0x100000, 447 size = '%dB' % (self.physmem.range.second - 0x100000 + 1), 448 range_type = 1)) 449 450 # Command line 451 self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \ 452 'root=/dev/hda1' 453 return self 454 455 456def makeDualRoot(testSystem, driveSystem, dumpfile): 457 self = Root() 458 self.testsys = testSystem 459 self.drivesys = driveSystem 460 self.etherlink = EtherLink() 461 self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 462 self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 463 464 if dumpfile: 465 self.etherdump = EtherDump(file=dumpfile) 466 self.etherlink.dump = Parent.etherdump 467 468 return self 469 470def setMipsOptions(TestCPUClass): 471 #CP0 Configuration 472 TestCPUClass.CoreParams.CP0_PRId_CompanyOptions = 0 473 TestCPUClass.CoreParams.CP0_PRId_CompanyID = 1 474 TestCPUClass.CoreParams.CP0_PRId_ProcessorID = 147 475 TestCPUClass.CoreParams.CP0_PRId_Revision = 0 476 477 #CP0 Interrupt Control 478 TestCPUClass.CoreParams.CP0_IntCtl_IPTI = 7 479 TestCPUClass.CoreParams.CP0_IntCtl_IPPCI = 7 480 481 # Config Register 482 #TestCPUClass.CoreParams.CP0_Config_K23 = 0 # Since TLB 483 #TestCPUClass.CoreParams.CP0_Config_KU = 0 # Since TLB 484 TestCPUClass.CoreParams.CP0_Config_BE = 0 # Little Endian 485 TestCPUClass.CoreParams.CP0_Config_AR = 1 # Architecture Revision 2 486 TestCPUClass.CoreParams.CP0_Config_AT = 0 # MIPS32 487 TestCPUClass.CoreParams.CP0_Config_MT = 1 # TLB MMU 488 #TestCPUClass.CoreParams.CP0_Config_K0 = 2 # Uncached 489 490 #Config 1 Register 491 TestCPUClass.CoreParams.CP0_Config1_M = 1 # Config2 Implemented 492 TestCPUClass.CoreParams.CP0_Config1_MMU = 63 # TLB Size 493 # ***VERY IMPORTANT*** 494 # Remember to modify CP0_Config1 according to cache specs 495 # Examine file ../common/Cache.py 496 TestCPUClass.CoreParams.CP0_Config1_IS = 1 # I-Cache Sets Per Way, 16KB cache, i.e., 1 (128) 497 TestCPUClass.CoreParams.CP0_Config1_IL = 5 # I-Cache Line Size, default in Cache.py is 64, i.e 5 498 TestCPUClass.CoreParams.CP0_Config1_IA = 1 # I-Cache Associativity, default in Cache.py is 2, i.e, a value of 1 499 TestCPUClass.CoreParams.CP0_Config1_DS = 2 # D-Cache Sets Per Way (see below), 32KB cache, i.e., 2 500 TestCPUClass.CoreParams.CP0_Config1_DL = 5 # D-Cache Line Size, default is 64, i.e., 5 501 TestCPUClass.CoreParams.CP0_Config1_DA = 1 # D-Cache Associativity, default is 2, i.e. 1 502 TestCPUClass.CoreParams.CP0_Config1_C2 = 0 # Coprocessor 2 not implemented(?) 503 TestCPUClass.CoreParams.CP0_Config1_MD = 0 # MDMX ASE not implemented in Mips32 504 TestCPUClass.CoreParams.CP0_Config1_PC = 1 # Performance Counters Implemented 505 TestCPUClass.CoreParams.CP0_Config1_WR = 0 # Watch Registers Implemented 506 TestCPUClass.CoreParams.CP0_Config1_CA = 0 # Mips16e NOT implemented 507 TestCPUClass.CoreParams.CP0_Config1_EP = 0 # EJTag Not Implemented 508 TestCPUClass.CoreParams.CP0_Config1_FP = 0 # FPU Implemented 509 510 #Config 2 Register 511 TestCPUClass.CoreParams.CP0_Config2_M = 1 # Config3 Implemented 512 TestCPUClass.CoreParams.CP0_Config2_TU = 0 # Tertiary Cache Control 513 TestCPUClass.CoreParams.CP0_Config2_TS = 0 # Tertiary Cache Sets Per Way 514 TestCPUClass.CoreParams.CP0_Config2_TL = 0 # Tertiary Cache Line Size 515 TestCPUClass.CoreParams.CP0_Config2_TA = 0 # Tertiary Cache Associativity 516 TestCPUClass.CoreParams.CP0_Config2_SU = 0 # Secondary Cache Control 517 TestCPUClass.CoreParams.CP0_Config2_SS = 0 # Secondary Cache Sets Per Way 518 TestCPUClass.CoreParams.CP0_Config2_SL = 0 # Secondary Cache Line Size 519 TestCPUClass.CoreParams.CP0_Config2_SA = 0 # Secondary Cache Associativity 520 521 522 #Config 3 Register 523 TestCPUClass.CoreParams.CP0_Config3_M = 0 # Config4 Not Implemented 524 TestCPUClass.CoreParams.CP0_Config3_DSPP = 1 # DSP ASE Present 525 TestCPUClass.CoreParams.CP0_Config3_LPA = 0 # Large Physical Addresses Not supported in Mips32 526 TestCPUClass.CoreParams.CP0_Config3_VEIC = 0 # EIC Supported 527 TestCPUClass.CoreParams.CP0_Config3_VInt = 0 # Vectored Interrupts Implemented 528 TestCPUClass.CoreParams.CP0_Config3_SP = 0 # Small Pages Supported (PageGrain reg. exists) 529 TestCPUClass.CoreParams.CP0_Config3_MT = 0 # MT Not present 530 TestCPUClass.CoreParams.CP0_Config3_SM = 0 # SmartMIPS ASE Not implemented 531 TestCPUClass.CoreParams.CP0_Config3_TL = 0 # TraceLogic Not implemented 532 533 #SRS Ctl - HSS 534 TestCPUClass.CoreParams.CP0_SrsCtl_HSS = 3 # Four shadow register sets implemented 535 536 537 #TestCPUClass.CoreParams.tlb = TLB() 538 #TestCPUClass.CoreParams.UnifiedTLB = 1 539