FSConfig.py revision 6802
15323Sgblack@eecs.umich.edu# Copyright (c) 2006-2008 The Regents of The University of Michigan 22934Sktlim@umich.edu# All rights reserved. 32934Sktlim@umich.edu# 42934Sktlim@umich.edu# Redistribution and use in source and binary forms, with or without 52934Sktlim@umich.edu# modification, are permitted provided that the following conditions are 62934Sktlim@umich.edu# met: redistributions of source code must retain the above copyright 72934Sktlim@umich.edu# notice, this list of conditions and the following disclaimer; 82934Sktlim@umich.edu# redistributions in binary form must reproduce the above copyright 92934Sktlim@umich.edu# notice, this list of conditions and the following disclaimer in the 102934Sktlim@umich.edu# documentation and/or other materials provided with the distribution; 112934Sktlim@umich.edu# neither the name of the copyright holders nor the names of its 122934Sktlim@umich.edu# contributors may be used to endorse or promote products derived from 132934Sktlim@umich.edu# this software without specific prior written permission. 142934Sktlim@umich.edu# 152934Sktlim@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 162934Sktlim@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 172934Sktlim@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 182934Sktlim@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 192934Sktlim@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 202934Sktlim@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 212934Sktlim@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 222934Sktlim@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 232934Sktlim@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 242934Sktlim@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 252934Sktlim@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 262934Sktlim@umich.edu# 272934Sktlim@umich.edu# Authors: Kevin Lim 282934Sktlim@umich.edu 292934Sktlim@umich.edufrom m5.objects import * 302995Ssaidi@eecs.umich.edufrom Benchmarks import * 312934Sktlim@umich.edu 322934Sktlim@umich.educlass CowIdeDisk(IdeDisk): 332934Sktlim@umich.edu image = CowDiskImage(child=RawDiskImage(read_only=True), 342934Sktlim@umich.edu read_only=False) 352934Sktlim@umich.edu 362934Sktlim@umich.edu def childImage(self, ci): 372934Sktlim@umich.edu self.image.child.image_file = ci 382934Sktlim@umich.edu 396122SSteve.Reinhardt@amd.comclass MemBus(Bus): 406122SSteve.Reinhardt@amd.com badaddr_responder = BadAddr() 416122SSteve.Reinhardt@amd.com default = Self.badaddr_responder.pio 426122SSteve.Reinhardt@amd.com 436122SSteve.Reinhardt@amd.com 444520Ssaidi@eecs.umich.edudef makeLinuxAlphaSystem(mem_mode, mdesc = None): 454520Ssaidi@eecs.umich.edu class BaseTsunami(Tsunami): 464982Ssaidi@eecs.umich.edu ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 474520Ssaidi@eecs.umich.edu ide = IdeController(disks=[Parent.disk0, Parent.disk2], 484520Ssaidi@eecs.umich.edu pci_func=0, pci_dev=0, pci_bus=0) 492934Sktlim@umich.edu 502934Sktlim@umich.edu self = LinuxAlphaSystem() 513005Sstever@eecs.umich.edu if not mdesc: 523005Sstever@eecs.umich.edu # generic system 533304Sstever@eecs.umich.edu mdesc = SysConfig() 542995Ssaidi@eecs.umich.edu self.readfile = mdesc.script() 552934Sktlim@umich.edu self.iobus = Bus(bus_id=0) 566122SSteve.Reinhardt@amd.com self.membus = MemBus(bus_id=1) 574965Ssaidi@eecs.umich.edu self.bridge = Bridge(delay='50ns', nack_delay='4ns') 585266Sksewell@umich.edu self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) 592934Sktlim@umich.edu self.bridge.side_a = self.iobus.port 602934Sktlim@umich.edu self.bridge.side_b = self.membus.port 612934Sktlim@umich.edu self.physmem.port = self.membus.port 622934Sktlim@umich.edu self.disk0 = CowIdeDisk(driveID='master') 632934Sktlim@umich.edu self.disk2 = CowIdeDisk(driveID='master') 642995Ssaidi@eecs.umich.edu self.disk0.childImage(mdesc.disk()) 652934Sktlim@umich.edu self.disk2.childImage(disk('linux-bigswap2.img')) 662934Sktlim@umich.edu self.tsunami = BaseTsunami() 672934Sktlim@umich.edu self.tsunami.attachIO(self.iobus) 682934Sktlim@umich.edu self.tsunami.ide.pio = self.iobus.port 692934Sktlim@umich.edu self.tsunami.ethernet.pio = self.iobus.port 702995Ssaidi@eecs.umich.edu self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 712934Sktlim@umich.edu read_only = True)) 722934Sktlim@umich.edu self.intrctrl = IntrControl() 732953Sktlim@umich.edu self.mem_mode = mem_mode 745478Snate@binkert.org self.terminal = Terminal() 752934Sktlim@umich.edu self.kernel = binary('vmlinux') 763449Shsul@eecs.umich.edu self.pal = binary('ts_osfpal') 772934Sktlim@umich.edu self.console = binary('console') 782934Sktlim@umich.edu self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 792934Sktlim@umich.edu 802934Sktlim@umich.edu return self 812934Sktlim@umich.edu 826765SBrad.Beckmann@amd.comdef makeLinuxAlphaRubySystem(mem_mode, rubymem, mdesc = None): 836765SBrad.Beckmann@amd.com class BaseTsunami(Tsunami): 846765SBrad.Beckmann@amd.com ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 856765SBrad.Beckmann@amd.com ide = IdeController(disks=[Parent.disk0, Parent.disk2], 866765SBrad.Beckmann@amd.com pci_func=0, pci_dev=0, pci_bus=0) 876765SBrad.Beckmann@amd.com 886765SBrad.Beckmann@amd.com 896765SBrad.Beckmann@amd.com self = LinuxAlphaSystem(physmem = rubymem) 906765SBrad.Beckmann@amd.com if not mdesc: 916765SBrad.Beckmann@amd.com # generic system 926765SBrad.Beckmann@amd.com mdesc = SysConfig() 936765SBrad.Beckmann@amd.com self.readfile = mdesc.script() 946765SBrad.Beckmann@amd.com 956765SBrad.Beckmann@amd.com # Create pio bus to connect all device pio ports to rubymem's pio port 966765SBrad.Beckmann@amd.com self.piobus = Bus(bus_id=0) 976765SBrad.Beckmann@amd.com 986765SBrad.Beckmann@amd.com self.disk0 = CowIdeDisk(driveID='master') 996765SBrad.Beckmann@amd.com self.disk2 = CowIdeDisk(driveID='master') 1006765SBrad.Beckmann@amd.com self.disk0.childImage(mdesc.disk()) 1016765SBrad.Beckmann@amd.com self.disk2.childImage(disk('linux-bigswap2.img')) 1026765SBrad.Beckmann@amd.com self.tsunami = BaseTsunami() 1036765SBrad.Beckmann@amd.com self.tsunami.attachIO(self.piobus) 1046765SBrad.Beckmann@amd.com self.tsunami.ide.pio = self.piobus.port 1056765SBrad.Beckmann@amd.com self.tsunami.ethernet.pio = self.piobus.port 1066765SBrad.Beckmann@amd.com 1076765SBrad.Beckmann@amd.com # connect the dma ports directly to ruby dma ports 1086765SBrad.Beckmann@amd.com self.tsunami.ide.dma = self.physmem.dma_port 1096765SBrad.Beckmann@amd.com self.tsunami.ethernet.dma = self.physmem.dma_port 1106765SBrad.Beckmann@amd.com 1116765SBrad.Beckmann@amd.com # connect the pio bus to rubymem 1126765SBrad.Beckmann@amd.com self.physmem.pio_port = self.piobus.port 1136765SBrad.Beckmann@amd.com 1146765SBrad.Beckmann@amd.com self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 1156765SBrad.Beckmann@amd.com read_only = True)) 1166765SBrad.Beckmann@amd.com self.intrctrl = IntrControl() 1176765SBrad.Beckmann@amd.com self.mem_mode = mem_mode 1186765SBrad.Beckmann@amd.com self.terminal = Terminal() 1196765SBrad.Beckmann@amd.com self.kernel = binary('vmlinux') 1206765SBrad.Beckmann@amd.com self.pal = binary('ts_osfpal') 1216765SBrad.Beckmann@amd.com self.console = binary('console') 1226765SBrad.Beckmann@amd.com self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 1236765SBrad.Beckmann@amd.com 1246765SBrad.Beckmann@amd.com return self 1256765SBrad.Beckmann@amd.com 1263584Ssaidi@eecs.umich.edudef makeSparcSystem(mem_mode, mdesc = None): 1274486Sbinkertn@umich.edu class CowMmDisk(MmDisk): 1284486Sbinkertn@umich.edu image = CowDiskImage(child=RawDiskImage(read_only=True), 1294486Sbinkertn@umich.edu read_only=False) 1304486Sbinkertn@umich.edu 1314486Sbinkertn@umich.edu def childImage(self, ci): 1324486Sbinkertn@umich.edu self.image.child.image_file = ci 1334486Sbinkertn@umich.edu 1343584Ssaidi@eecs.umich.edu self = SparcSystem() 1353584Ssaidi@eecs.umich.edu if not mdesc: 1363584Ssaidi@eecs.umich.edu # generic system 1373584Ssaidi@eecs.umich.edu mdesc = SysConfig() 1383584Ssaidi@eecs.umich.edu self.readfile = mdesc.script() 1393743Sgblack@eecs.umich.edu self.iobus = Bus(bus_id=0) 1406122SSteve.Reinhardt@amd.com self.membus = MemBus(bus_id=1) 1414972Ssaidi@eecs.umich.edu self.bridge = Bridge(delay='50ns', nack_delay='4ns') 1423743Sgblack@eecs.umich.edu self.t1000 = T1000() 1434104Ssaidi@eecs.umich.edu self.t1000.attachOnChipIO(self.membus) 1443743Sgblack@eecs.umich.edu self.t1000.attachIO(self.iobus) 1453823Ssaidi@eecs.umich.edu self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True) 1463814Ssaidi@eecs.umich.edu self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True) 1473743Sgblack@eecs.umich.edu self.bridge.side_a = self.iobus.port 1483743Sgblack@eecs.umich.edu self.bridge.side_b = self.membus.port 1493584Ssaidi@eecs.umich.edu self.physmem.port = self.membus.port 1503814Ssaidi@eecs.umich.edu self.physmem2.port = self.membus.port 1513584Ssaidi@eecs.umich.edu self.rom.port = self.membus.port 1523745Sgblack@eecs.umich.edu self.nvram.port = self.membus.port 1533745Sgblack@eecs.umich.edu self.hypervisor_desc.port = self.membus.port 1543745Sgblack@eecs.umich.edu self.partition_desc.port = self.membus.port 1553584Ssaidi@eecs.umich.edu self.intrctrl = IntrControl() 1563898Ssaidi@eecs.umich.edu self.disk0 = CowMmDisk() 1573898Ssaidi@eecs.umich.edu self.disk0.childImage(disk('disk.s10hw2')) 1583898Ssaidi@eecs.umich.edu self.disk0.pio = self.iobus.port 1594103Ssaidi@eecs.umich.edu self.reset_bin = binary('reset_new.bin') 1604103Ssaidi@eecs.umich.edu self.hypervisor_bin = binary('q_new.bin') 1614103Ssaidi@eecs.umich.edu self.openboot_bin = binary('openboot_new.bin') 1623745Sgblack@eecs.umich.edu self.nvram_bin = binary('nvram1') 1633745Sgblack@eecs.umich.edu self.hypervisor_desc_bin = binary('1up-hv.bin') 1643745Sgblack@eecs.umich.edu self.partition_desc_bin = binary('1up-md.bin') 1653584Ssaidi@eecs.umich.edu 1663584Ssaidi@eecs.umich.edu return self 1673584Ssaidi@eecs.umich.edu 1685222Sksewell@umich.edudef makeLinuxMipsSystem(mem_mode, mdesc = None): 1695222Sksewell@umich.edu class BaseMalta(Malta): 1705222Sksewell@umich.edu ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 1715222Sksewell@umich.edu ide = IdeController(disks=[Parent.disk0, Parent.disk2], 1725222Sksewell@umich.edu pci_func=0, pci_dev=0, pci_bus=0) 1735222Sksewell@umich.edu 1745222Sksewell@umich.edu self = LinuxMipsSystem() 1755222Sksewell@umich.edu if not mdesc: 1765222Sksewell@umich.edu # generic system 1775222Sksewell@umich.edu mdesc = SysConfig() 1785222Sksewell@umich.edu self.readfile = mdesc.script() 1795222Sksewell@umich.edu self.iobus = Bus(bus_id=0) 1806122SSteve.Reinhardt@amd.com self.membus = MemBus(bus_id=1) 1815222Sksewell@umich.edu self.bridge = Bridge(delay='50ns', nack_delay='4ns') 1825222Sksewell@umich.edu self.physmem = PhysicalMemory(range = AddrRange('1GB')) 1835222Sksewell@umich.edu self.bridge.side_a = self.iobus.port 1845222Sksewell@umich.edu self.bridge.side_b = self.membus.port 1855222Sksewell@umich.edu self.physmem.port = self.membus.port 1865222Sksewell@umich.edu self.disk0 = CowIdeDisk(driveID='master') 1875222Sksewell@umich.edu self.disk2 = CowIdeDisk(driveID='master') 1885222Sksewell@umich.edu self.disk0.childImage(mdesc.disk()) 1895222Sksewell@umich.edu self.disk2.childImage(disk('linux-bigswap2.img')) 1905222Sksewell@umich.edu self.malta = BaseMalta() 1915222Sksewell@umich.edu self.malta.attachIO(self.iobus) 1925222Sksewell@umich.edu self.malta.ide.pio = self.iobus.port 1935222Sksewell@umich.edu self.malta.ethernet.pio = self.iobus.port 1945222Sksewell@umich.edu self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 1955222Sksewell@umich.edu read_only = True)) 1965222Sksewell@umich.edu self.intrctrl = IntrControl() 1975222Sksewell@umich.edu self.mem_mode = mem_mode 1985478Snate@binkert.org self.terminal = Terminal() 1995222Sksewell@umich.edu self.kernel = binary('mips/vmlinux') 2005222Sksewell@umich.edu self.console = binary('mips/console') 2015222Sksewell@umich.edu self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 2025222Sksewell@umich.edu 2035222Sksewell@umich.edu return self 2045222Sksewell@umich.edu 2055323Sgblack@eecs.umich.edudef x86IOAddress(port): 2065357Sgblack@eecs.umich.edu IO_address_space_base = 0x8000000000000000 2075323Sgblack@eecs.umich.edu return IO_address_space_base + port; 2085323Sgblack@eecs.umich.edu 2096135Sgblack@eecs.umich.edudef makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None): 2105613Sgblack@eecs.umich.edu if self == None: 2115613Sgblack@eecs.umich.edu self = X86System() 2125613Sgblack@eecs.umich.edu 2135133Sgblack@eecs.umich.edu if not mdesc: 2145133Sgblack@eecs.umich.edu # generic system 2155133Sgblack@eecs.umich.edu mdesc = SysConfig() 2165841Sgblack@eecs.umich.edu mdesc.diskname = 'x86root.img' 2175133Sgblack@eecs.umich.edu self.readfile = mdesc.script() 2185133Sgblack@eecs.umich.edu 2196802Sgblack@eecs.umich.edu self.mem_mode = mem_mode 2206802Sgblack@eecs.umich.edu 2215133Sgblack@eecs.umich.edu # Physical memory 2226122SSteve.Reinhardt@amd.com self.membus = MemBus(bus_id=1) 2235450Sgblack@eecs.umich.edu self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) 2245133Sgblack@eecs.umich.edu self.physmem.port = self.membus.port 2255133Sgblack@eecs.umich.edu 2265613Sgblack@eecs.umich.edu # North Bridge 2275613Sgblack@eecs.umich.edu self.iobus = Bus(bus_id=0) 2285613Sgblack@eecs.umich.edu self.bridge = Bridge(delay='50ns', nack_delay='4ns') 2295613Sgblack@eecs.umich.edu self.bridge.side_a = self.iobus.port 2305613Sgblack@eecs.umich.edu self.bridge.side_b = self.membus.port 2315613Sgblack@eecs.umich.edu 2325613Sgblack@eecs.umich.edu # Platform 2335638Sgblack@eecs.umich.edu self.pc = Pc() 2345613Sgblack@eecs.umich.edu self.pc.attachIO(self.iobus) 2355613Sgblack@eecs.umich.edu 2365613Sgblack@eecs.umich.edu self.intrctrl = IntrControl() 2375613Sgblack@eecs.umich.edu 2385841Sgblack@eecs.umich.edu # Disks 2395841Sgblack@eecs.umich.edu disk0 = CowIdeDisk(driveID='master') 2405841Sgblack@eecs.umich.edu disk2 = CowIdeDisk(driveID='master') 2415841Sgblack@eecs.umich.edu disk0.childImage(mdesc.disk()) 2425841Sgblack@eecs.umich.edu disk2.childImage(disk('linux-bigswap2.img')) 2435841Sgblack@eecs.umich.edu self.pc.south_bridge.ide.disks = [disk0, disk2] 2445841Sgblack@eecs.umich.edu 2455615Sgblack@eecs.umich.edu # Add in a Bios information structure. 2465615Sgblack@eecs.umich.edu structures = [X86SMBiosBiosInformation()] 2475615Sgblack@eecs.umich.edu self.smbios_table.structures = structures 2485615Sgblack@eecs.umich.edu 2495641Sgblack@eecs.umich.edu # Set up the Intel MP table 2506135Sgblack@eecs.umich.edu for i in xrange(numCPUs): 2516135Sgblack@eecs.umich.edu bp = X86IntelMPProcessor( 2526135Sgblack@eecs.umich.edu local_apic_id = i, 2536135Sgblack@eecs.umich.edu local_apic_version = 0x14, 2546135Sgblack@eecs.umich.edu enable = True, 2556135Sgblack@eecs.umich.edu bootstrap = (i == 0)) 2566135Sgblack@eecs.umich.edu self.intel_mp_table.add_entry(bp) 2575644Sgblack@eecs.umich.edu io_apic = X86IntelMPIOAPIC( 2586135Sgblack@eecs.umich.edu id = numCPUs, 2595644Sgblack@eecs.umich.edu version = 0x11, 2605644Sgblack@eecs.umich.edu enable = True, 2615644Sgblack@eecs.umich.edu address = 0xfec00000) 2626135Sgblack@eecs.umich.edu self.pc.south_bridge.io_apic.apic_id = io_apic.id 2635644Sgblack@eecs.umich.edu self.intel_mp_table.add_entry(io_apic) 2645644Sgblack@eecs.umich.edu isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA') 2655644Sgblack@eecs.umich.edu self.intel_mp_table.add_entry(isa_bus) 2665843Sgblack@eecs.umich.edu pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI') 2675843Sgblack@eecs.umich.edu self.intel_mp_table.add_entry(pci_bus) 2685843Sgblack@eecs.umich.edu connect_busses = X86IntelMPBusHierarchy(bus_id=0, 2695843Sgblack@eecs.umich.edu subtractive_decode=True, parent_bus=1) 2705843Sgblack@eecs.umich.edu self.intel_mp_table.add_entry(connect_busses) 2715843Sgblack@eecs.umich.edu pci_dev4_inta = X86IntelMPIOIntAssignment( 2725843Sgblack@eecs.umich.edu interrupt_type = 'INT', 2735843Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 2745843Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 2755843Sgblack@eecs.umich.edu source_bus_id = 1, 2765843Sgblack@eecs.umich.edu source_bus_irq = 0 + (4 << 2), 2776044Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 2785843Sgblack@eecs.umich.edu dest_io_apic_intin = 16) 2796074Sgblack@eecs.umich.edu self.intel_mp_table.add_entry(pci_dev4_inta); 2806135Sgblack@eecs.umich.edu def assignISAInt(irq, apicPin): 2816135Sgblack@eecs.umich.edu assign_8259_to_apic = X86IntelMPIOIntAssignment( 2826135Sgblack@eecs.umich.edu interrupt_type = 'ExtInt', 2836135Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 2846135Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 2856135Sgblack@eecs.umich.edu source_bus_id = 0, 2866135Sgblack@eecs.umich.edu source_bus_irq = irq, 2876135Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 2886135Sgblack@eecs.umich.edu dest_io_apic_intin = 0) 2896135Sgblack@eecs.umich.edu self.intel_mp_table.add_entry(assign_8259_to_apic) 2906135Sgblack@eecs.umich.edu assign_to_apic = X86IntelMPIOIntAssignment( 2916135Sgblack@eecs.umich.edu interrupt_type = 'INT', 2926135Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 2936135Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 2946135Sgblack@eecs.umich.edu source_bus_id = 0, 2956135Sgblack@eecs.umich.edu source_bus_irq = irq, 2966135Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 2976135Sgblack@eecs.umich.edu dest_io_apic_intin = apicPin) 2986135Sgblack@eecs.umich.edu self.intel_mp_table.add_entry(assign_to_apic) 2996135Sgblack@eecs.umich.edu assignISAInt(0, 2) 3006135Sgblack@eecs.umich.edu assignISAInt(1, 1) 3016135Sgblack@eecs.umich.edu for i in range(3, 15): 3026135Sgblack@eecs.umich.edu assignISAInt(i, i) 3035641Sgblack@eecs.umich.edu 3045613Sgblack@eecs.umich.edu 3056135Sgblack@eecs.umich.edudef makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None): 3065613Sgblack@eecs.umich.edu self = LinuxX86System() 3075613Sgblack@eecs.umich.edu 3085613Sgblack@eecs.umich.edu # Build up a generic x86 system and then specialize it for Linux 3096135Sgblack@eecs.umich.edu makeX86System(mem_mode, numCPUs, mdesc, self) 3105613Sgblack@eecs.umich.edu 3115450Sgblack@eecs.umich.edu # We assume below that there's at least 1MB of memory. We'll require 2 3125450Sgblack@eecs.umich.edu # just to avoid corner cases. 3135450Sgblack@eecs.umich.edu assert(self.physmem.range.second >= 0x200000) 3145450Sgblack@eecs.umich.edu 3155450Sgblack@eecs.umich.edu # Mark the first megabyte of memory as reserved 3165450Sgblack@eecs.umich.edu self.e820_table.entries.append(X86E820Entry( 3175450Sgblack@eecs.umich.edu addr = 0, 3185450Sgblack@eecs.umich.edu size = '1MB', 3195450Sgblack@eecs.umich.edu range_type = 2)) 3205450Sgblack@eecs.umich.edu 3215450Sgblack@eecs.umich.edu # Mark the rest as available 3225450Sgblack@eecs.umich.edu self.e820_table.entries.append(X86E820Entry( 3235450Sgblack@eecs.umich.edu addr = 0x100000, 3246072Sgblack@eecs.umich.edu size = '%dB' % (self.physmem.range.second - 0x100000 + 1), 3255450Sgblack@eecs.umich.edu range_type = 1)) 3265450Sgblack@eecs.umich.edu 3275330Sgblack@eecs.umich.edu # Command line 3285847Sgblack@eecs.umich.edu self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \ 3295845Sgblack@eecs.umich.edu 'root=/dev/hda1' 3305133Sgblack@eecs.umich.edu return self 3315133Sgblack@eecs.umich.edu 3323584Ssaidi@eecs.umich.edu 3333025Ssaidi@eecs.umich.edudef makeDualRoot(testSystem, driveSystem, dumpfile): 3342934Sktlim@umich.edu self = Root() 3352995Ssaidi@eecs.umich.edu self.testsys = testSystem 3362995Ssaidi@eecs.umich.edu self.drivesys = driveSystem 3374981Ssaidi@eecs.umich.edu self.etherlink = EtherLink() 3384981Ssaidi@eecs.umich.edu self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 3394981Ssaidi@eecs.umich.edu self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 3404981Ssaidi@eecs.umich.edu 3413025Ssaidi@eecs.umich.edu if dumpfile: 3423025Ssaidi@eecs.umich.edu self.etherdump = EtherDump(file=dumpfile) 3433025Ssaidi@eecs.umich.edu self.etherlink.dump = Parent.etherdump 3442934Sktlim@umich.edu 3452934Sktlim@umich.edu return self 3465253Sksewell@umich.edu 3475263Sksewell@umich.edudef setMipsOptions(TestCPUClass): 3485253Sksewell@umich.edu #CP0 Configuration 3495253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_PRId_CompanyOptions = 0 3505253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_PRId_CompanyID = 1 3515253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_PRId_ProcessorID = 147 3525253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_PRId_Revision = 0 3535253Sksewell@umich.edu 3545253Sksewell@umich.edu #CP0 Interrupt Control 3555253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_IntCtl_IPTI = 7 3565253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_IntCtl_IPPCI = 7 3575253Sksewell@umich.edu 3585253Sksewell@umich.edu # Config Register 3595253Sksewell@umich.edu #TestCPUClass.CoreParams.CP0_Config_K23 = 0 # Since TLB 3605253Sksewell@umich.edu #TestCPUClass.CoreParams.CP0_Config_KU = 0 # Since TLB 3615253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config_BE = 0 # Little Endian 3625253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config_AR = 1 # Architecture Revision 2 3635253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config_AT = 0 # MIPS32 3645253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config_MT = 1 # TLB MMU 3655253Sksewell@umich.edu #TestCPUClass.CoreParams.CP0_Config_K0 = 2 # Uncached 3665253Sksewell@umich.edu 3675253Sksewell@umich.edu #Config 1 Register 3685253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_M = 1 # Config2 Implemented 3695253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_MMU = 63 # TLB Size 3705253Sksewell@umich.edu # ***VERY IMPORTANT*** 3715253Sksewell@umich.edu # Remember to modify CP0_Config1 according to cache specs 3725253Sksewell@umich.edu # Examine file ../common/Cache.py 3735253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_IS = 1 # I-Cache Sets Per Way, 16KB cache, i.e., 1 (128) 3745253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_IL = 5 # I-Cache Line Size, default in Cache.py is 64, i.e 5 3755253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_IA = 1 # I-Cache Associativity, default in Cache.py is 2, i.e, a value of 1 3765253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_DS = 2 # D-Cache Sets Per Way (see below), 32KB cache, i.e., 2 3775253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_DL = 5 # D-Cache Line Size, default is 64, i.e., 5 3785253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_DA = 1 # D-Cache Associativity, default is 2, i.e. 1 3795253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_C2 = 0 # Coprocessor 2 not implemented(?) 3805253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_MD = 0 # MDMX ASE not implemented in Mips32 3815253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_PC = 1 # Performance Counters Implemented 3825253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_WR = 0 # Watch Registers Implemented 3835253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_CA = 0 # Mips16e NOT implemented 3845253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_EP = 0 # EJTag Not Implemented 3855253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_FP = 0 # FPU Implemented 3865253Sksewell@umich.edu 3875253Sksewell@umich.edu #Config 2 Register 3885253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_M = 1 # Config3 Implemented 3895253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_TU = 0 # Tertiary Cache Control 3905253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_TS = 0 # Tertiary Cache Sets Per Way 3915253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_TL = 0 # Tertiary Cache Line Size 3925253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_TA = 0 # Tertiary Cache Associativity 3935253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_SU = 0 # Secondary Cache Control 3945253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_SS = 0 # Secondary Cache Sets Per Way 3955253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_SL = 0 # Secondary Cache Line Size 3965253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_SA = 0 # Secondary Cache Associativity 3975253Sksewell@umich.edu 3985253Sksewell@umich.edu 3995253Sksewell@umich.edu #Config 3 Register 4005253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_M = 0 # Config4 Not Implemented 4015253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_DSPP = 1 # DSP ASE Present 4025253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_LPA = 0 # Large Physical Addresses Not supported in Mips32 4035253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_VEIC = 0 # EIC Supported 4045253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_VInt = 0 # Vectored Interrupts Implemented 4055253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_SP = 0 # Small Pages Supported (PageGrain reg. exists) 4065253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_MT = 0 # MT Not present 4075253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_SM = 0 # SmartMIPS ASE Not implemented 4085253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_TL = 0 # TraceLogic Not implemented 4095253Sksewell@umich.edu 4105253Sksewell@umich.edu #SRS Ctl - HSS 4115253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_SrsCtl_HSS = 3 # Four shadow register sets implemented 4125253Sksewell@umich.edu 4135253Sksewell@umich.edu 4145253Sksewell@umich.edu #TestCPUClass.CoreParams.tlb = TLB() 4155253Sksewell@umich.edu #TestCPUClass.CoreParams.UnifiedTLB = 1 416