FSConfig.py revision 6122
15323Sgblack@eecs.umich.edu# Copyright (c) 2006-2008 The Regents of The University of Michigan 22934Sktlim@umich.edu# All rights reserved. 32934Sktlim@umich.edu# 42934Sktlim@umich.edu# Redistribution and use in source and binary forms, with or without 52934Sktlim@umich.edu# modification, are permitted provided that the following conditions are 62934Sktlim@umich.edu# met: redistributions of source code must retain the above copyright 72934Sktlim@umich.edu# notice, this list of conditions and the following disclaimer; 82934Sktlim@umich.edu# redistributions in binary form must reproduce the above copyright 92934Sktlim@umich.edu# notice, this list of conditions and the following disclaimer in the 102934Sktlim@umich.edu# documentation and/or other materials provided with the distribution; 112934Sktlim@umich.edu# neither the name of the copyright holders nor the names of its 122934Sktlim@umich.edu# contributors may be used to endorse or promote products derived from 132934Sktlim@umich.edu# this software without specific prior written permission. 142934Sktlim@umich.edu# 152934Sktlim@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 162934Sktlim@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 172934Sktlim@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 182934Sktlim@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 192934Sktlim@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 202934Sktlim@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 212934Sktlim@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 222934Sktlim@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 232934Sktlim@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 242934Sktlim@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 252934Sktlim@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 262934Sktlim@umich.edu# 272934Sktlim@umich.edu# Authors: Kevin Lim 282934Sktlim@umich.edu 292934Sktlim@umich.eduimport m5 302969Sktlim@umich.edufrom m5 import makeList 312934Sktlim@umich.edufrom m5.objects import * 322995Ssaidi@eecs.umich.edufrom Benchmarks import * 332934Sktlim@umich.edu 342934Sktlim@umich.educlass CowIdeDisk(IdeDisk): 352934Sktlim@umich.edu image = CowDiskImage(child=RawDiskImage(read_only=True), 362934Sktlim@umich.edu read_only=False) 372934Sktlim@umich.edu 382934Sktlim@umich.edu def childImage(self, ci): 392934Sktlim@umich.edu self.image.child.image_file = ci 402934Sktlim@umich.edu 416122SSteve.Reinhardt@amd.comclass MemBus(Bus): 426122SSteve.Reinhardt@amd.com badaddr_responder = BadAddr() 436122SSteve.Reinhardt@amd.com default = Self.badaddr_responder.pio 446122SSteve.Reinhardt@amd.com 456122SSteve.Reinhardt@amd.com 464520Ssaidi@eecs.umich.edudef makeLinuxAlphaSystem(mem_mode, mdesc = None): 474520Ssaidi@eecs.umich.edu class BaseTsunami(Tsunami): 484982Ssaidi@eecs.umich.edu ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 494520Ssaidi@eecs.umich.edu ide = IdeController(disks=[Parent.disk0, Parent.disk2], 504520Ssaidi@eecs.umich.edu pci_func=0, pci_dev=0, pci_bus=0) 512934Sktlim@umich.edu 522934Sktlim@umich.edu self = LinuxAlphaSystem() 533005Sstever@eecs.umich.edu if not mdesc: 543005Sstever@eecs.umich.edu # generic system 553304Sstever@eecs.umich.edu mdesc = SysConfig() 562995Ssaidi@eecs.umich.edu self.readfile = mdesc.script() 572934Sktlim@umich.edu self.iobus = Bus(bus_id=0) 586122SSteve.Reinhardt@amd.com self.membus = MemBus(bus_id=1) 594965Ssaidi@eecs.umich.edu self.bridge = Bridge(delay='50ns', nack_delay='4ns') 605266Sksewell@umich.edu self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) 612934Sktlim@umich.edu self.bridge.side_a = self.iobus.port 622934Sktlim@umich.edu self.bridge.side_b = self.membus.port 632934Sktlim@umich.edu self.physmem.port = self.membus.port 642934Sktlim@umich.edu self.disk0 = CowIdeDisk(driveID='master') 652934Sktlim@umich.edu self.disk2 = CowIdeDisk(driveID='master') 662995Ssaidi@eecs.umich.edu self.disk0.childImage(mdesc.disk()) 672934Sktlim@umich.edu self.disk2.childImage(disk('linux-bigswap2.img')) 682934Sktlim@umich.edu self.tsunami = BaseTsunami() 692934Sktlim@umich.edu self.tsunami.attachIO(self.iobus) 702934Sktlim@umich.edu self.tsunami.ide.pio = self.iobus.port 712934Sktlim@umich.edu self.tsunami.ethernet.pio = self.iobus.port 722995Ssaidi@eecs.umich.edu self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 732934Sktlim@umich.edu read_only = True)) 742934Sktlim@umich.edu self.intrctrl = IntrControl() 752953Sktlim@umich.edu self.mem_mode = mem_mode 765478Snate@binkert.org self.terminal = Terminal() 772934Sktlim@umich.edu self.kernel = binary('vmlinux') 783449Shsul@eecs.umich.edu self.pal = binary('ts_osfpal') 792934Sktlim@umich.edu self.console = binary('console') 802934Sktlim@umich.edu self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 812934Sktlim@umich.edu 822934Sktlim@umich.edu return self 832934Sktlim@umich.edu 843584Ssaidi@eecs.umich.edudef makeSparcSystem(mem_mode, mdesc = None): 854486Sbinkertn@umich.edu class CowMmDisk(MmDisk): 864486Sbinkertn@umich.edu image = CowDiskImage(child=RawDiskImage(read_only=True), 874486Sbinkertn@umich.edu read_only=False) 884486Sbinkertn@umich.edu 894486Sbinkertn@umich.edu def childImage(self, ci): 904486Sbinkertn@umich.edu self.image.child.image_file = ci 914486Sbinkertn@umich.edu 923584Ssaidi@eecs.umich.edu self = SparcSystem() 933584Ssaidi@eecs.umich.edu if not mdesc: 943584Ssaidi@eecs.umich.edu # generic system 953584Ssaidi@eecs.umich.edu mdesc = SysConfig() 963584Ssaidi@eecs.umich.edu self.readfile = mdesc.script() 973743Sgblack@eecs.umich.edu self.iobus = Bus(bus_id=0) 986122SSteve.Reinhardt@amd.com self.membus = MemBus(bus_id=1) 994972Ssaidi@eecs.umich.edu self.bridge = Bridge(delay='50ns', nack_delay='4ns') 1003743Sgblack@eecs.umich.edu self.t1000 = T1000() 1014104Ssaidi@eecs.umich.edu self.t1000.attachOnChipIO(self.membus) 1023743Sgblack@eecs.umich.edu self.t1000.attachIO(self.iobus) 1033823Ssaidi@eecs.umich.edu self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True) 1043814Ssaidi@eecs.umich.edu self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True) 1053743Sgblack@eecs.umich.edu self.bridge.side_a = self.iobus.port 1063743Sgblack@eecs.umich.edu self.bridge.side_b = self.membus.port 1073584Ssaidi@eecs.umich.edu self.physmem.port = self.membus.port 1083814Ssaidi@eecs.umich.edu self.physmem2.port = self.membus.port 1093584Ssaidi@eecs.umich.edu self.rom.port = self.membus.port 1103745Sgblack@eecs.umich.edu self.nvram.port = self.membus.port 1113745Sgblack@eecs.umich.edu self.hypervisor_desc.port = self.membus.port 1123745Sgblack@eecs.umich.edu self.partition_desc.port = self.membus.port 1133584Ssaidi@eecs.umich.edu self.intrctrl = IntrControl() 1143898Ssaidi@eecs.umich.edu self.disk0 = CowMmDisk() 1153898Ssaidi@eecs.umich.edu self.disk0.childImage(disk('disk.s10hw2')) 1163898Ssaidi@eecs.umich.edu self.disk0.pio = self.iobus.port 1174103Ssaidi@eecs.umich.edu self.reset_bin = binary('reset_new.bin') 1184103Ssaidi@eecs.umich.edu self.hypervisor_bin = binary('q_new.bin') 1194103Ssaidi@eecs.umich.edu self.openboot_bin = binary('openboot_new.bin') 1203745Sgblack@eecs.umich.edu self.nvram_bin = binary('nvram1') 1213745Sgblack@eecs.umich.edu self.hypervisor_desc_bin = binary('1up-hv.bin') 1223745Sgblack@eecs.umich.edu self.partition_desc_bin = binary('1up-md.bin') 1233584Ssaidi@eecs.umich.edu 1243584Ssaidi@eecs.umich.edu return self 1253584Ssaidi@eecs.umich.edu 1265222Sksewell@umich.edudef makeLinuxMipsSystem(mem_mode, mdesc = None): 1275222Sksewell@umich.edu class BaseMalta(Malta): 1285222Sksewell@umich.edu ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 1295222Sksewell@umich.edu ide = IdeController(disks=[Parent.disk0, Parent.disk2], 1305222Sksewell@umich.edu pci_func=0, pci_dev=0, pci_bus=0) 1315222Sksewell@umich.edu 1325222Sksewell@umich.edu self = LinuxMipsSystem() 1335222Sksewell@umich.edu if not mdesc: 1345222Sksewell@umich.edu # generic system 1355222Sksewell@umich.edu mdesc = SysConfig() 1365222Sksewell@umich.edu self.readfile = mdesc.script() 1375222Sksewell@umich.edu self.iobus = Bus(bus_id=0) 1386122SSteve.Reinhardt@amd.com self.membus = MemBus(bus_id=1) 1395222Sksewell@umich.edu self.bridge = Bridge(delay='50ns', nack_delay='4ns') 1405222Sksewell@umich.edu self.physmem = PhysicalMemory(range = AddrRange('1GB')) 1415222Sksewell@umich.edu self.bridge.side_a = self.iobus.port 1425222Sksewell@umich.edu self.bridge.side_b = self.membus.port 1435222Sksewell@umich.edu self.physmem.port = self.membus.port 1445222Sksewell@umich.edu self.disk0 = CowIdeDisk(driveID='master') 1455222Sksewell@umich.edu self.disk2 = CowIdeDisk(driveID='master') 1465222Sksewell@umich.edu self.disk0.childImage(mdesc.disk()) 1475222Sksewell@umich.edu self.disk2.childImage(disk('linux-bigswap2.img')) 1485222Sksewell@umich.edu self.malta = BaseMalta() 1495222Sksewell@umich.edu self.malta.attachIO(self.iobus) 1505222Sksewell@umich.edu self.malta.ide.pio = self.iobus.port 1515222Sksewell@umich.edu self.malta.ethernet.pio = self.iobus.port 1525222Sksewell@umich.edu self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 1535222Sksewell@umich.edu read_only = True)) 1545222Sksewell@umich.edu self.intrctrl = IntrControl() 1555222Sksewell@umich.edu self.mem_mode = mem_mode 1565478Snate@binkert.org self.terminal = Terminal() 1575222Sksewell@umich.edu self.kernel = binary('mips/vmlinux') 1585222Sksewell@umich.edu self.console = binary('mips/console') 1595222Sksewell@umich.edu self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 1605222Sksewell@umich.edu 1615222Sksewell@umich.edu return self 1625222Sksewell@umich.edu 1635323Sgblack@eecs.umich.edudef x86IOAddress(port): 1645357Sgblack@eecs.umich.edu IO_address_space_base = 0x8000000000000000 1655323Sgblack@eecs.umich.edu return IO_address_space_base + port; 1665323Sgblack@eecs.umich.edu 1675613Sgblack@eecs.umich.edudef makeX86System(mem_mode, mdesc = None, self = None): 1685613Sgblack@eecs.umich.edu if self == None: 1695613Sgblack@eecs.umich.edu self = X86System() 1705613Sgblack@eecs.umich.edu 1715133Sgblack@eecs.umich.edu if not mdesc: 1725133Sgblack@eecs.umich.edu # generic system 1735133Sgblack@eecs.umich.edu mdesc = SysConfig() 1745841Sgblack@eecs.umich.edu mdesc.diskname = 'x86root.img' 1755133Sgblack@eecs.umich.edu self.readfile = mdesc.script() 1765133Sgblack@eecs.umich.edu 1775133Sgblack@eecs.umich.edu # Physical memory 1786122SSteve.Reinhardt@amd.com self.membus = MemBus(bus_id=1) 1795450Sgblack@eecs.umich.edu self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) 1805133Sgblack@eecs.umich.edu self.physmem.port = self.membus.port 1815133Sgblack@eecs.umich.edu 1825613Sgblack@eecs.umich.edu # North Bridge 1835613Sgblack@eecs.umich.edu self.iobus = Bus(bus_id=0) 1845613Sgblack@eecs.umich.edu self.bridge = Bridge(delay='50ns', nack_delay='4ns') 1855613Sgblack@eecs.umich.edu self.bridge.side_a = self.iobus.port 1865613Sgblack@eecs.umich.edu self.bridge.side_b = self.membus.port 1875613Sgblack@eecs.umich.edu 1885613Sgblack@eecs.umich.edu # Platform 1895638Sgblack@eecs.umich.edu self.pc = Pc() 1905613Sgblack@eecs.umich.edu self.pc.attachIO(self.iobus) 1915613Sgblack@eecs.umich.edu 1925613Sgblack@eecs.umich.edu self.intrctrl = IntrControl() 1935613Sgblack@eecs.umich.edu 1945841Sgblack@eecs.umich.edu # Disks 1955841Sgblack@eecs.umich.edu disk0 = CowIdeDisk(driveID='master') 1965841Sgblack@eecs.umich.edu disk2 = CowIdeDisk(driveID='master') 1975841Sgblack@eecs.umich.edu disk0.childImage(mdesc.disk()) 1985841Sgblack@eecs.umich.edu disk2.childImage(disk('linux-bigswap2.img')) 1995841Sgblack@eecs.umich.edu self.pc.south_bridge.ide.disks = [disk0, disk2] 2005841Sgblack@eecs.umich.edu 2015615Sgblack@eecs.umich.edu # Add in a Bios information structure. 2025615Sgblack@eecs.umich.edu structures = [X86SMBiosBiosInformation()] 2035615Sgblack@eecs.umich.edu self.smbios_table.structures = structures 2045615Sgblack@eecs.umich.edu 2055641Sgblack@eecs.umich.edu # Set up the Intel MP table 2065641Sgblack@eecs.umich.edu bp = X86IntelMPProcessor( 2075641Sgblack@eecs.umich.edu local_apic_id = 0, 2085641Sgblack@eecs.umich.edu local_apic_version = 0x14, 2095641Sgblack@eecs.umich.edu enable = True, 2105641Sgblack@eecs.umich.edu bootstrap = True) 2115641Sgblack@eecs.umich.edu self.intel_mp_table.add_entry(bp) 2125644Sgblack@eecs.umich.edu io_apic = X86IntelMPIOAPIC( 2135644Sgblack@eecs.umich.edu id = 1, 2145644Sgblack@eecs.umich.edu version = 0x11, 2155644Sgblack@eecs.umich.edu enable = True, 2165644Sgblack@eecs.umich.edu address = 0xfec00000) 2175644Sgblack@eecs.umich.edu self.intel_mp_table.add_entry(io_apic) 2185644Sgblack@eecs.umich.edu isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA') 2195644Sgblack@eecs.umich.edu self.intel_mp_table.add_entry(isa_bus) 2205843Sgblack@eecs.umich.edu pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI') 2215843Sgblack@eecs.umich.edu self.intel_mp_table.add_entry(pci_bus) 2225843Sgblack@eecs.umich.edu connect_busses = X86IntelMPBusHierarchy(bus_id=0, 2235843Sgblack@eecs.umich.edu subtractive_decode=True, parent_bus=1) 2245843Sgblack@eecs.umich.edu self.intel_mp_table.add_entry(connect_busses) 2255843Sgblack@eecs.umich.edu pci_dev4_inta = X86IntelMPIOIntAssignment( 2265843Sgblack@eecs.umich.edu interrupt_type = 'INT', 2275843Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 2285843Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 2295843Sgblack@eecs.umich.edu source_bus_id = 1, 2305843Sgblack@eecs.umich.edu source_bus_irq = 0 + (4 << 2), 2316044Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 2325843Sgblack@eecs.umich.edu dest_io_apic_intin = 16) 2336074Sgblack@eecs.umich.edu self.intel_mp_table.add_entry(pci_dev4_inta); 2345828Sgblack@eecs.umich.edu assign_8259_0_to_apic = X86IntelMPIOIntAssignment( 2355644Sgblack@eecs.umich.edu interrupt_type = 'ExtInt', 2365644Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 2375644Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 2385644Sgblack@eecs.umich.edu source_bus_id = 0, 2395644Sgblack@eecs.umich.edu source_bus_irq = 0, 2406044Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 2415644Sgblack@eecs.umich.edu dest_io_apic_intin = 0) 2425828Sgblack@eecs.umich.edu self.intel_mp_table.add_entry(assign_8259_0_to_apic) 2435828Sgblack@eecs.umich.edu assign_0_to_apic = X86IntelMPIOIntAssignment( 2445828Sgblack@eecs.umich.edu interrupt_type = 'INT', 2455828Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 2465828Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 2475828Sgblack@eecs.umich.edu source_bus_id = 0, 2485828Sgblack@eecs.umich.edu source_bus_irq = 0, 2496044Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 2505828Sgblack@eecs.umich.edu dest_io_apic_intin = 2) 2515828Sgblack@eecs.umich.edu self.intel_mp_table.add_entry(assign_0_to_apic) 2525828Sgblack@eecs.umich.edu assign_8259_1_to_apic = X86IntelMPIOIntAssignment( 2535828Sgblack@eecs.umich.edu interrupt_type = 'ExtInt', 2545828Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 2555828Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 2565828Sgblack@eecs.umich.edu source_bus_id = 0, 2575828Sgblack@eecs.umich.edu source_bus_irq = 1, 2586044Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 2595828Sgblack@eecs.umich.edu dest_io_apic_intin = 0) 2605828Sgblack@eecs.umich.edu self.intel_mp_table.add_entry(assign_8259_1_to_apic) 2615828Sgblack@eecs.umich.edu assign_1_to_apic = X86IntelMPIOIntAssignment( 2625828Sgblack@eecs.umich.edu interrupt_type = 'INT', 2635828Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 2645828Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 2655828Sgblack@eecs.umich.edu source_bus_id = 0, 2665828Sgblack@eecs.umich.edu source_bus_irq = 1, 2676044Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 2685828Sgblack@eecs.umich.edu dest_io_apic_intin = 1) 2695828Sgblack@eecs.umich.edu self.intel_mp_table.add_entry(assign_1_to_apic) 2705918Sgblack@eecs.umich.edu assign_8259_4_to_apic = X86IntelMPIOIntAssignment( 2715918Sgblack@eecs.umich.edu interrupt_type = 'ExtInt', 2725918Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 2735918Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 2745918Sgblack@eecs.umich.edu source_bus_id = 0, 2755918Sgblack@eecs.umich.edu source_bus_irq = 4, 2766044Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 2775918Sgblack@eecs.umich.edu dest_io_apic_intin = 0) 2785918Sgblack@eecs.umich.edu self.intel_mp_table.add_entry(assign_8259_4_to_apic) 2795918Sgblack@eecs.umich.edu assign_4_to_apic = X86IntelMPIOIntAssignment( 2805918Sgblack@eecs.umich.edu interrupt_type = 'INT', 2815918Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 2825918Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 2835918Sgblack@eecs.umich.edu source_bus_id = 0, 2845918Sgblack@eecs.umich.edu source_bus_irq = 4, 2856044Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 2865918Sgblack@eecs.umich.edu dest_io_apic_intin = 4) 2875918Sgblack@eecs.umich.edu self.intel_mp_table.add_entry(assign_4_to_apic) 2885828Sgblack@eecs.umich.edu assign_8259_12_to_apic = X86IntelMPIOIntAssignment( 2895828Sgblack@eecs.umich.edu interrupt_type = 'ExtInt', 2905828Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 2915828Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 2925828Sgblack@eecs.umich.edu source_bus_id = 0, 2935828Sgblack@eecs.umich.edu source_bus_irq = 12, 2946044Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 2955828Sgblack@eecs.umich.edu dest_io_apic_intin = 0) 2965828Sgblack@eecs.umich.edu self.intel_mp_table.add_entry(assign_8259_12_to_apic) 2975828Sgblack@eecs.umich.edu assign_12_to_apic = X86IntelMPIOIntAssignment( 2985828Sgblack@eecs.umich.edu interrupt_type = 'INT', 2995828Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 3005828Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 3015828Sgblack@eecs.umich.edu source_bus_id = 0, 3025828Sgblack@eecs.umich.edu source_bus_irq = 12, 3036044Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 3045828Sgblack@eecs.umich.edu dest_io_apic_intin = 12) 3055828Sgblack@eecs.umich.edu self.intel_mp_table.add_entry(assign_12_to_apic) 3065843Sgblack@eecs.umich.edu assign_8259_14_to_apic = X86IntelMPIOIntAssignment( 3075843Sgblack@eecs.umich.edu interrupt_type = 'ExtInt', 3085843Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 3095843Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 3105843Sgblack@eecs.umich.edu source_bus_id = 0, 3115843Sgblack@eecs.umich.edu source_bus_irq = 14, 3126044Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 3135843Sgblack@eecs.umich.edu dest_io_apic_intin = 0) 3145843Sgblack@eecs.umich.edu self.intel_mp_table.add_entry(assign_8259_14_to_apic) 3155843Sgblack@eecs.umich.edu assign_14_to_apic = X86IntelMPIOIntAssignment( 3165843Sgblack@eecs.umich.edu interrupt_type = 'INT', 3175843Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 3185843Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 3195843Sgblack@eecs.umich.edu source_bus_id = 0, 3205843Sgblack@eecs.umich.edu source_bus_irq = 14, 3216044Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 3225843Sgblack@eecs.umich.edu dest_io_apic_intin = 14) 3235843Sgblack@eecs.umich.edu self.intel_mp_table.add_entry(assign_14_to_apic) 3245641Sgblack@eecs.umich.edu 3255613Sgblack@eecs.umich.edu 3265613Sgblack@eecs.umich.edudef makeLinuxX86System(mem_mode, mdesc = None): 3275613Sgblack@eecs.umich.edu self = LinuxX86System() 3285613Sgblack@eecs.umich.edu 3295613Sgblack@eecs.umich.edu # Build up a generic x86 system and then specialize it for Linux 3305613Sgblack@eecs.umich.edu makeX86System(mem_mode, mdesc, self) 3315613Sgblack@eecs.umich.edu 3325450Sgblack@eecs.umich.edu # We assume below that there's at least 1MB of memory. We'll require 2 3335450Sgblack@eecs.umich.edu # just to avoid corner cases. 3345450Sgblack@eecs.umich.edu assert(self.physmem.range.second >= 0x200000) 3355450Sgblack@eecs.umich.edu 3365450Sgblack@eecs.umich.edu # Mark the first megabyte of memory as reserved 3375450Sgblack@eecs.umich.edu self.e820_table.entries.append(X86E820Entry( 3385450Sgblack@eecs.umich.edu addr = 0, 3395450Sgblack@eecs.umich.edu size = '1MB', 3405450Sgblack@eecs.umich.edu range_type = 2)) 3415450Sgblack@eecs.umich.edu 3425450Sgblack@eecs.umich.edu # Mark the rest as available 3435450Sgblack@eecs.umich.edu self.e820_table.entries.append(X86E820Entry( 3445450Sgblack@eecs.umich.edu addr = 0x100000, 3456072Sgblack@eecs.umich.edu size = '%dB' % (self.physmem.range.second - 0x100000 + 1), 3465450Sgblack@eecs.umich.edu range_type = 1)) 3475450Sgblack@eecs.umich.edu 3485330Sgblack@eecs.umich.edu # Command line 3495847Sgblack@eecs.umich.edu self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \ 3505845Sgblack@eecs.umich.edu 'root=/dev/hda1' 3515133Sgblack@eecs.umich.edu return self 3525133Sgblack@eecs.umich.edu 3533584Ssaidi@eecs.umich.edu 3543025Ssaidi@eecs.umich.edudef makeDualRoot(testSystem, driveSystem, dumpfile): 3552934Sktlim@umich.edu self = Root() 3562995Ssaidi@eecs.umich.edu self.testsys = testSystem 3572995Ssaidi@eecs.umich.edu self.drivesys = driveSystem 3584981Ssaidi@eecs.umich.edu self.etherlink = EtherLink() 3594981Ssaidi@eecs.umich.edu self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 3604981Ssaidi@eecs.umich.edu self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 3614981Ssaidi@eecs.umich.edu 3623025Ssaidi@eecs.umich.edu if dumpfile: 3633025Ssaidi@eecs.umich.edu self.etherdump = EtherDump(file=dumpfile) 3643025Ssaidi@eecs.umich.edu self.etherlink.dump = Parent.etherdump 3652934Sktlim@umich.edu 3662934Sktlim@umich.edu return self 3675253Sksewell@umich.edu 3685263Sksewell@umich.edudef setMipsOptions(TestCPUClass): 3695253Sksewell@umich.edu #CP0 Configuration 3705253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_PRId_CompanyOptions = 0 3715253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_PRId_CompanyID = 1 3725253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_PRId_ProcessorID = 147 3735253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_PRId_Revision = 0 3745253Sksewell@umich.edu 3755253Sksewell@umich.edu #CP0 Interrupt Control 3765253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_IntCtl_IPTI = 7 3775253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_IntCtl_IPPCI = 7 3785253Sksewell@umich.edu 3795253Sksewell@umich.edu # Config Register 3805253Sksewell@umich.edu #TestCPUClass.CoreParams.CP0_Config_K23 = 0 # Since TLB 3815253Sksewell@umich.edu #TestCPUClass.CoreParams.CP0_Config_KU = 0 # Since TLB 3825253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config_BE = 0 # Little Endian 3835253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config_AR = 1 # Architecture Revision 2 3845253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config_AT = 0 # MIPS32 3855253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config_MT = 1 # TLB MMU 3865253Sksewell@umich.edu #TestCPUClass.CoreParams.CP0_Config_K0 = 2 # Uncached 3875253Sksewell@umich.edu 3885253Sksewell@umich.edu #Config 1 Register 3895253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_M = 1 # Config2 Implemented 3905253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_MMU = 63 # TLB Size 3915253Sksewell@umich.edu # ***VERY IMPORTANT*** 3925253Sksewell@umich.edu # Remember to modify CP0_Config1 according to cache specs 3935253Sksewell@umich.edu # Examine file ../common/Cache.py 3945253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_IS = 1 # I-Cache Sets Per Way, 16KB cache, i.e., 1 (128) 3955253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_IL = 5 # I-Cache Line Size, default in Cache.py is 64, i.e 5 3965253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_IA = 1 # I-Cache Associativity, default in Cache.py is 2, i.e, a value of 1 3975253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_DS = 2 # D-Cache Sets Per Way (see below), 32KB cache, i.e., 2 3985253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_DL = 5 # D-Cache Line Size, default is 64, i.e., 5 3995253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_DA = 1 # D-Cache Associativity, default is 2, i.e. 1 4005253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_C2 = 0 # Coprocessor 2 not implemented(?) 4015253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_MD = 0 # MDMX ASE not implemented in Mips32 4025253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_PC = 1 # Performance Counters Implemented 4035253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_WR = 0 # Watch Registers Implemented 4045253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_CA = 0 # Mips16e NOT implemented 4055253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_EP = 0 # EJTag Not Implemented 4065253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_FP = 0 # FPU Implemented 4075253Sksewell@umich.edu 4085253Sksewell@umich.edu #Config 2 Register 4095253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_M = 1 # Config3 Implemented 4105253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_TU = 0 # Tertiary Cache Control 4115253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_TS = 0 # Tertiary Cache Sets Per Way 4125253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_TL = 0 # Tertiary Cache Line Size 4135253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_TA = 0 # Tertiary Cache Associativity 4145253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_SU = 0 # Secondary Cache Control 4155253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_SS = 0 # Secondary Cache Sets Per Way 4165253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_SL = 0 # Secondary Cache Line Size 4175253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_SA = 0 # Secondary Cache Associativity 4185253Sksewell@umich.edu 4195253Sksewell@umich.edu 4205253Sksewell@umich.edu #Config 3 Register 4215253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_M = 0 # Config4 Not Implemented 4225253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_DSPP = 1 # DSP ASE Present 4235253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_LPA = 0 # Large Physical Addresses Not supported in Mips32 4245253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_VEIC = 0 # EIC Supported 4255253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_VInt = 0 # Vectored Interrupts Implemented 4265253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_SP = 0 # Small Pages Supported (PageGrain reg. exists) 4275253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_MT = 0 # MT Not present 4285253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_SM = 0 # SmartMIPS ASE Not implemented 4295253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_TL = 0 # TraceLogic Not implemented 4305253Sksewell@umich.edu 4315253Sksewell@umich.edu #SRS Ctl - HSS 4325253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_SrsCtl_HSS = 3 # Four shadow register sets implemented 4335253Sksewell@umich.edu 4345253Sksewell@umich.edu 4355253Sksewell@umich.edu #TestCPUClass.CoreParams.tlb = TLB() 4365253Sksewell@umich.edu #TestCPUClass.CoreParams.UnifiedTLB = 1 437